NJU26902

NJU26902 Digital Audio Delay ! General Description The NJU26902 is a digital audio delay. The NJU26902 provides delay-time adjustment function and digital audio interface. ! Package ! FEATURES NJU26902VM1 • 2-Channel Audio Delay (24 bits data width). Delay Time 85msec at fs = 48kHz ( 128msec at fs = 32kHz , 43msec at fs = 96kHz) • To make long delay time, the NJU26902 can be connected serially. • Non-audio-signal data can be delayed by the NJU26902. ! Hardware Specification • Digital Audio Interface • Digital Audio Format • Audio Bit Clock (BCK) Frequency • Package • Power Supply : : : : : 1 Input port, 1 Output port LJ / RJ / I2S 24bit BCK : 64fs / 32fs, Slave Mode 13MHz Max ( approximate fs=200KHz) SSOP20-M1 Pb-Free 2.5V ( +3.3V input tolerant ) ! Function Block Diagram NJU26902 BCK LRI LRI BCK SDI SERIAL AUDIO INTERFACE Delay RAM SERIAL AUDIO INTERFACE L/R in L/R ｏｕｔ SDO Control Logic RESETb COUNT[5:0] MODE[1:0] SDO_OD BYPASS FS Ver.2005-01-11 -1- NJU26902 ! Pin Assignment RESETb SDI LRI COUNT[2] COUNT[3] BCKI COUNT[4] COUNT[5] VSS VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD VDD SDO FS BYPASS SDO_OD COUNT[1] MODE[1] COUNT[0] MODE[0] NJU26902 ! Pin Description No. Symbol I/O RESETb I△ 1 SDI I 2 LRI I 3 COUNT[2] I△ 4 COUNT[3] I△ 5 BCKI I 6 COUNT[4] I△ 7 COUNT[5] I△ 8 VSS 9 VSS 10 MODE[0] I▼ 11 COUNT[0] I△ 12 MODE[1] I△ 13 COUNT[1] I△ 14 SDO_OD I▼ 15 BYPASS I▼ 16 FS I△ 17 SDO O 18 VDD 19 VDD 20 I : Input, I△ : Input(internal pull-up), I▼ Description Reset (Active low) Audio Data Input LR Clock Input Delay Time Control 2 Delay Time Control 3 Bit Clock Input Delay Time Control 4 Delay Time Control 5 GND GND Digital Audio Interface Format Select Delay Time Control 0 Digital Audio Interface Format Select Delay Time Control 1 SDO pin Open Drain Select SDO pin BYPASS Control BCK fs Select Audio Data Output (CMOS Output / Open Drain Output) Power Supply +2.5V Power Supply +2.5V : Input(internal pull-down), O : Output, P: +Power, G : GND -2- Ver.2005-01-11 NJU26902 1. Electric Characteristics 1.1 Absolute Maximum Ratings Table1-1 Absolute Maximum Ratings (VSS=0V, Ta=25℃) Parameter Power Supply Voltage Symbol VDD Rating -0.3 to +3.0 Units V Input Pin Voltage VX(IN) -0.3 to +3.6 V 1 SDO Pin Voltage * -0.3 to VDD+0.3 V VX(O) (CMOS Output) SDO Pin Voltage *2 -0.3 to +3.6 V VX(OD) (Open Drain Output) Power Dissipation PD 300 mW Storage Temperature Tstg -40 to +125 °C *1 This specification is applied to VX (O) at the SDO pin. in case of SDO_OD= “Low”. *2 This specification is applied to VX (OD) at the SDO pin. in case of SDO_OD= “High”. Ver.2005-01-11 -3- NJU26902 1.2 Electric Characteristics Table1-2 Electric Characteristics (VDD=2.5V, VSS=0V, Ta=25℃) Parameter Operating VDD Voltage Operating Current Operating Temperature High Level Input Voltage Low Level Input Voltage High Level Output Voltage (SDO_OD=”Low”) Low Level Output Voltage Open Drain Output Current (SDO_OD=”High”) Input Current Input Current (Internal Pull-up Pin) Input Current (Internal Pull-down Pin) Input Capacitance Input Rise/Fall transition Time Symbol VDD IDD TOPR VIH VIL VOH VOL IOD IIN IIN(PU) IIN(PD) CIN tr / tf IOH= -2mA IOH= -100uA IOL= 2mA IOL= 100uA VIN= 3.3V VIN= VSS to 3.3V VIN= VSS to 3.3V VIN= VSS to 3.3V BCKI:13MHz SDO:CL=25pF Test Condition Min. 2.25 -40 2.0 VDD-0.4 VDD-0.1 0 0 -15 -15 -100 -15 Typ. 2.5 1.0 25 10 Max. 2.75 85 3.3 0.5 VDD VDD 0.4 0.1 +15 +15 +15 +200 100 uA uA uA pF ns Units V mA ℃ V V V V ! Equivalent Circuit VDD PU VDD Input terminal Output terminal VSS VDD Input terminal VSS PD VSS Input Pin （SDI, LRI, BCKI） Input Pin （Internal Pull-up (PU) : RESETb, MODE[1], FS, COUNT[5], COUNT[4], COUNT[3], COUNT[2], COUNT[1], COUNT[0], Internal Pull-down (PD) : MODE[0], SDO_OD,BYPASS） Output Pin （SDO） Fig. 1-1 I/O Equivalent Circuits -4- Ver.2005-01-11 NJU26902 2. Serial Audio Data Transmitting Diagram LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB 23 SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 2-1 Left-Justified Data Format 64fs, 24bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 2-2 Right-Justified Data Format 64fs, 24bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 2-3 I2S Data Format 64fs, 24bit Data Ver.2005-01-11 -5- NJU26902 LRI, LRO BCKI, BCKO M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 2-4 Left-Justified Data Format 32fs, 16bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB M SB 16 Clocks 16 Clocks LSB SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 2-5 Right-Justified Data Format 32fs, 16bit Data LRI, LRO BCKI, BCKO M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 2-6 I2S Data Format 32fs, 16bit Data -6- Ver.2005-01-11 NJU26902 2.1 Serial Audio Timing Table 2-1 Serial Audio Input Timing Parameters Parameter BCKI Frequency BCKI Period L Pulse Width H Pulse Width BCKI to LRI Time LRI to BCKI Time Data Setup Time Data Hold Time Data Output Delay Symbol fBCK tSIL tSIH TSLI tLSI tDS tDH tDOD SDO:CL=25pF SDO_OD=”Low” Test Condition Min 35 35 15 15 15 15 Typ. Max 13 15 Units MHz ns ns ns ns ns ns LRI tSIH tSIL tSLI tLSI BCKI tDS tDH SDI SDO tDOD Fig. 2-7 Serial Audio Input / Output Timing Ver.2005-01-11 -7- NJU26902 3. Function Description ・ SDI(#2) is a serial audio input pin. The input audio signal should be connected to this pin. ・ LRI(#3) is a LR clock input pin. This LR clock frequency is the same frequency of the input audio signal. In case of I2S format, LRI=”Low” shows SDI and SDO data are left channel data, and LRI=”High” shows SDI and SDO data are right channel data. ・ BCKI(#6) is bit clock input pin. This BCKI clock frequency is 32 times (32fs) or 64 times (64fs) as large as the pin input audio signal. A bit length is 16bit precision in 32fs mode, and a bit length is 24bit precision in 64fs mode. ・ MODE [1:0](#13,#11) and FS(#17) pins select serial audio format. Refer to Table3-1”Mode pin, FS pin Setup”. ・ SDO(#18) is serial audio output pin. The delayed audio data come out through this pin. ・ SDO is 2.5V CMOS output in case of SDO_OD(#15)= "Low". SDO is open drain output in case of SDO_OD= "High", SDO can be pulled up to 3.3V. In case of SDO_OD= "Low" & BYPASS= "High", the bypass mode is selected. ・ The next combination is reserved. Do not use this combination. SDO_OD= "High" & BYPASS= "High". Refer to Table3-2 ”SDO_OD pin, BYPASS pin Setup”. ・ COUNT [5:0](#8, #7, #5, #4, #14, #12) pins select delay time. When the setup is changed, SDO outputs a "Low" level (mute) during the period selected by COUNT [5:0]. Refer to 4. Delay Time. ・ When RESETb is "Low", the NJU26902 is initialized on the rise edge of BCKI. SDO outputs a "Low" level (mute) during the period selected by COUNT [5:0]. ・ In case of not using RESETb, connect RESETb to VDD. ・ VDD is a power supply pin. Connect VDD to the power supply 2.5V. VSS is a GND pin. The decoupling capacitor is necessary between VDD and VSS. ・ The input pins can interface to 3.3V ICs. Refer to Table 1-2”Electric Characteristics”. ・ After Power supply or serial audio format changing, there is possibility the NJU26902 generates random data for the delay time period set by COUNT[5:1] pins. If necessary, the mute circuit should be added or reset NJU26902. Table 3-1 Mode pin, FS pin Setup MODE[1] (13pin) 0 0 1 0 0 1 Other * : 0=Low, 1=High *1 : Do not use. FS (17pin) 0 0 0 1 1 1 MODE[0] (11pin) 0 1 0 0 1 0 Setup RJ 16bit 32fs LJ 16bit 32fs I2S 16bit 32fs RJ 24bit 64fs LJ 24bit 64fs I2S 24bit 64fs Reserved *1 Table 3-2 SDO_OD pin, BYPASS pin Setup SDO_OD BYPASS (15pin) (16pin) 0 0 0 1 1 0 1 1 * : 0=Low, 1=High *1 : Do not use. NJU26902 Function Delay Operation, SDO=CMOS Output Bypass Operation, SDO=CMOS Output Delay Operation, SDO=Open Drain Output Reserved *1 -8- Ver.2005-01-11 NJU26902 4. Delay Time ・ The NJU26902 provides maximum 4097 samples delay and slave-mode audio interface. The delay time depends on sampling frequency. ・ The next formula shows how to calculate the delay time. Refer to Table 4-1”Delaty Sample Number Setup Example”. ・ Total delay sample number = COUNT[0]*2048+COUNT[1]*1024+COUNT[2]*512+COUNT[3]*256+COUNT[4]*128+COUNT[5]*64+64+1 Table 4-1 Delay Sample Number Setup Example COUNT[0] COUNT[1] COUNT[2] COUNT[3] COUNT[4] COUNT[5] (12pin) (14pin) (4pin) (5pin) (7pin) (8pin) 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 * : 0=Low, 1=High Total Delay Sample Number 65 (minimum) 1601 3201 4097 (maximum) Ver.2005-01-11 -9- NJU26902 5. Package Dimensions SSOP20-M1 0 ～1 0 ﾟ 6. 5 -0.1 +0.2 20 11 4.4 ± 0.2 6.4 ± 0.2 1 0 .3 2 5T YP 10 0 . 65 0 .1 5 -0.06 +0.05 0.9 ±0.05 1. 1MAX Mold Base 0 .0 8 0 .2 2 ± 0. 1 0. 1 0 M 0.1 ± 0.0 5 UNIT : mm 0 .6 ± 0 .1 - 10 Ver.2005-01-11 NJU26902 Version V0.4 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2005-01-11 - 11 -