NJU3430FG1

NJU3430 NJU3430 16-CHARACTER 1-LINE DOT MATRIX VFD CONTROLLER DRIVER 16-CHARACTER n GENERAL DESCRIPTION GENERAL The NJU3430 is a Dot Matrix VFD (Vacuum Fluorescent Display) The Controller Driver for 16-character 1-line with Icon display. It contains character generator ROM/RAM, address counter, oscillation circuit, command register, Icon display RAM, high voltage drivers, and serial interface circuit. The display data or the command data is transmitted with the serial interface circuits. The character generator consists of 8,400 bits ROM and 35 x 8 bits RAM. The CG RAM stores 8 kinds of character by 5 x 7dots maximum. The 16-common and 37-segment (35 for character, 2 for icon) drivers operated up to 45V drive the display of 16-character 1-line with 32Icon. Furthermore, the NJU3430 incorporates one Output port which drives the LED. n FEATURES FEATURES l 16-character 1-line Dot Matrix VFD Controller Driver 16-character l Serial Interface with Microprocessor Serial l Display Data RAM Display l Character Generator ROM Character l Character Generator RAM Character l Icon Display RAM Icon l VFD Driving Voltage VFD Timing Signal Segment Signal l Output Port for LED : 1 Output l Display ON/OFF Function Display l Digit Scan Function Digit l Display Duty (Contrast Control) : 8-step (8/16 to 15/16) Display l Character / Icon Shift Function Character l Display Mode (9 to 16 Digits) Display l Oscillation Circuit on-chip (External Resistor and Capacitor Required) Oscillation l Operating Voltage Operating l Package Outline Package l C-MOS Technology C-MOS 3.0V to 5.5V (Except VFD Driving Voltage) QFP 64 : 16 : 35 (Except for Icon Segment Signal) 16 x 8 bits 8,400 bits 35 x 8 bits 16 x 2 bits : 16-character 1-line Display : 240 Characters for 5 x 7 Dots : 8 Patterns (5 x 7 Dots) : Maximum 32 Icon n PACKAGE OUTLINE PACKAGE NJU3430FG1 NJU3430FG1 45V | VDD-V FDP | ≤ 45V Jul. 2003 Ver. 3 NJU3430 NJU3430 n PIN CONFIGURATION PIN V F DP T 16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 48 V SS O SC 1 O SC 2 RST CS CLK SI RS VDD P1 M K2 M K1 S1 S2 S3 S4 64 1 49 T2 33 32 T1 S 35 S 34 S 33 S 32 S 31 S 30 S 29 S 28 S 27 S 26 S 25 S 24 S 23 S 22 NJU3430 17 16 S 21 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 n BLOCK DIAGRAM BLOCK RST R ESET Instruction SI C S CLK Reg. R S 8bits Shift Line Address Counter Decoder MK RA M 16x2bit S20 S5 S6 S7 S8 S9 Icon Driver MK1∼MK2 CG RA M 35x8bit Segment Driver S1∼S35 Port Driver Timing Gen. State Reg. Address Selector CG RO M 8,400bit P1 OSC1 OSC2 VDD VSS VFD P Read C R OSC. Display Control Address Counter DD RAM 16x8bit Timing Driver T1∼T16 NJU3430 NJU3430 n TERMINAL DESCRIPTION TERMINAL No. 57 49 48 50 51 54 SYMBOL VDD V SS VFDP OSC1 OSC2 CLK I/O I O I Power Source GND FUNCTION : VD D =+3.0 to 5.5V : VSS =0V VFD Driving Power Sourse V D D -20V to V D D -45V CR Oscillation Terminal External R and C connect to these terminals. (Target f O S C = 3 6 0 k H z ) Serial Clock Input Terminal The serial data input synchronizing the rise edge of this terminal. Chip Select Terminal When the CS terminal is "H" the serial data input is not available. Serial Data Input Terminal The data input is MSB first. Register Selection Signal Input Terminal RS="0" : Instruction Register RS="1" : Data Register Reset Terminal RST="L" : Reset -Each Address -Each RAM Data -Display Digits -Contrast Control -All Display Off -All Outputs are "L" : : : : (00)H Unfixed 16-digit 8/16 Dury 53 CS I 55 SI I 56 RS I 52 RST I 61 to 64, 1 to 31 32 to 47 60 59 58 S 1 to S 3 5 T1 to T1 6 MK 1 MK 2 P1 O O O O Segment Output Terminals (Internal Pull-down Resistance) Timing Output Terminals (Internal Pull-down Resistance) Icon Output Terminals (Internal Pull-down Resistance) Output Port Terminal This terminal is suitable for LED. NJU3430 NJU3430 n FUNCTION DESCRIPTION FUNCTION (1)CG RAM data and Character Dot Matrix The character generator RAM (CG RAM) stores any kinds of character pattern by 5 x 7 dots written by the user program to display user’s original character pattern. The CG RAM stores 8 kinds of character by 5 x 7 dots maximum. To display user’s original character pattern stored in the CG RAM, the address data (00)H - (07) should be written to the DD RAM as shown in Table 2. Table 1.Correspondence of CG RAM address, DD RAM character code and CG RAM character pattern(5 x 7 dots). Character Code (DD RAM Data) CG RAM Address AC5 AC4 AC3 AC2 0 0 0 (00) H 0 0 0 0 1 1 1 1 0 0 0 (01) H 0 0 1 0 1 1 1 1 : : : : : : 0 0 0 (07) H 1 1 1 0 1 1 1 1 AC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 : : : 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 S1 S6 S 11 S 16 S 21 S 26 S 31 S2 S7 S 12 S 17 S 22 S 27 S 32 AC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S1 S6 S 11 S 16 S 21 S 26 S 31 Correspondence of CG RAM Data and SEG Terminal SC4 S1 S6 S 11 S 16 S 21 S 26 S 31 SC3 S2 S7 S 12 S 17 S 22 S 27 S 32 SC2 S3 S8 S 13 S 18 S 23 S 28 S 33 SC1 S4 S9 S 14 S 19 S 24 S 29 S 34 SC0 S5 S 10 S 15 S 20 S 25 S 30 S 35 Invalid Address S2 S7 S 12 S 17 S 22 S 27 S 32 S3 S8 S 13 S 18 S 23 S 28 S 33 S4 S9 S 14 S 19 S 24 S 29 S 34 S5 S 10 S 15 S 20 S 25 S 30 S 35 Invalid Address : : : S3 S8 S 13 S 18 S 23 S 28 S 33 S4 S9 S 14 S 19 S 24 S 29 S 34 S5 S 10 S 15 S 20 S 25 S 30 S 35 Invalid Address * When the data is written to CG RAM successively, the invalid address is skipped automatically. (Ex.)CG RAM Address : (06)H CG CG RAM Address : (08)H After After data writing operation NJU3430 NJU3430 Table Table 2.CG ROM Character Pattern (ROM version -02) NJU3430 NJU3430 (2)Reset (2)Reset Function (2-1)Initialization by Reset Terminal The NJU3430 incorporates RST terminal to initialize the all system. When the "L" level is input over 1us to the RST terminal, the reset sequence is executed. The Initialization flow is shown below : Each RAM Address Each Each RAM Data Output Port Display Digits Contrast Control All Display ON/OFF --- (00)H --- Unfixed --- "L" Level (V SS) --- 16-digit --- 8/16 Duty --- All Display OFF (2-2)Initialization (After the Reset) Reset ↓ Display Digits Set ↓ Contrast Control Set ↓ DD RAM Address Set → Data Writing Data ↓ CG RAM Address Set → Data Writing Data ↓ MK RAM Address Set → Data Writing Data ↓ Output Port Set ↓ All Display Off ← Data set should be executed because Data the data in DD RAM is unfixed. ← Data set should be executed because Data the data in CG RAM is unfixed. ← Data set should be executed because Data the data in MK RAM is unfixed. ← (Initialization : All “Low” level) (Initialization ← (Initialization : 8/16 Duty) (Initialization ← (Initialization : 16-digit) (Initialization NJU3430 NJU3430 (3)Instruction (3)Instruction Each instruction is shown in the Table 3. The data should be written to the RAM continuously after the RAM address set. The order of data writing is MSB first. Table 3. Table of Instruction MSB INSTRUCTION RS Maker Test Output Port Set Display On/Off Display Duty Set Display Shift Display Blink Set Display Digits Set 0 0 0 0 0 0 B7 0 0 0 0 0 0 B6 0 0 0 0 0 0 B5 0 0 0 0 0 1 B4 0 0 0 0 1 B2 B3 0 0 0 1 0 B1 B2 0 0 1 D2 LR B0 B1 0 1 M D1 M M B0 0 P1 Output Port Control D Set the Display On/Off (Character and Icon) Serial Data LSB DESCRIPTION D0 Set the Contrast Control D D Set the Display Shift (Character and Icon) Set the Blink Interval (Character and Icon) 0 0 1 0 0 0 0 0 0 1 0 C2 C1 C0 Set the Display Digits (9 to 16 degits) AD3 AD2 AM3 AM2 RAM Address Set 0 1 0 1 Set the RAM Address (AD0 to AD3 : DD RAM) (AM0 to AM3 : MK RAM) AM1 AM0 (AC0 to AC5 : CG RAM) AD1 AD0 AC1 AC0 After the RAM Address Set, the data should be written to RAM (SD0 to SD7 : DD RAM) SM1 SM0 (SM0 to SM1 : MK RAM) (SC0 to SC4 : CG RAM) SC1 SC0 SD1 SD0 AC5 AC4 AC3 AC2 SD7 SD6 SD5 SD4 SD3 SD2 Write Data to RAM 1 0 0 0 0 0 0 0 0 0 SC4 SC3 SC2 *Instruction is executed within 32uS from the rise edge of the Chip Select CS Signal. (at fOSC=250kHz) NJU3430 NJU3430 (3-1)Description (3-1)Description of each Instruction (a)Maker Testing RS 0 B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 0 Set Set the test mode. (b)Output Port Set RS 0 B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 1 B0 P1 Set Set the Output Port (1 bit static operation)."P1" is Output Port name. *P1 does not drive VFD. P1 0 1 "L" level is output. "H" level is output. FUNCTION (c)Display On/Off RS 0 B7 0 B6 0 B5 0 B4 0 B3 0 B2 1 B1 M B0 D Set Set the Display On/Off (Character and Icon). All Display are Off after Reset. M 0 0 1 1 D 0 1 0 1 F U N C T I O N Icon Display "Off", Character Display "Off" Icon Display "Off", Character Display "On" Icon Icon Display Display "On", "On", Character Character Display Display "Off" "On" (d)Display Duty Set RS 0 B7 0 B6 0 B5 0 B4 0 B3 1 B2 D2 B1 D1 B0 D0 One One duty is selected from among eight kinds of duty by Display Duty Set. 8/16 Duty (lowest contrast) is set after reset, an optional duty should be selected before display operation. B2 0 0 : 1 1 B1 0 0 : 1 1 B0 0 1 : 0 1 Duty 8/16 9/16 : 14/16 15/16 NJU3430 NJU3430 (e)Display (e)Display Shift RS 0 B7 0 B6 0 B5 0 B4 1 B3 0 B2 LR B1 M B0 D The The display positions of Character and Icon are shifted by Display Shift instruction. When the codes of "LR", "M" and "D" mentioned below are written into "B2", "B1" and "B0", the display positions are shifted individually. LR 0 1 F U N C T I O N Shift the display position to the right. Shift the display position to the left. M 0 1 F U N C T I O N The shift operation is not available. The shift oparation is selected for Icon. D 0 1 FUNCTION The shift operation is not available. The shift oparation is selected for Character. 16-digit 16-digit Display Example [Input Data] 1-digit 00010001 (DD RAM right shift) 00010010 (MK RAM right shift) 00010011 (DD,MK RAM right shift) 00 0F [Correspondence of DD RAM, MK RAM Address and Display] 8-digit 16-digit 01 00 02 01 03 02 04 03 05 04 06 05 07 06 08 07 09 08 0A 09 0B 0A 0C 0B 0D 0C 0E 0D 0F 0E ← MK RAM MK ← DD RAM DD ← MK RAM MK ← DD RAM DD ← MK RAM MK ← DD RAM DD 0F 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 0A 0A 0B 0B 0C 0C 0D 0D 0E 0E 0F 0F 0F 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 0A 0A 0B 0B 0C 0C 0D 0D 0E 0E 9-digit Display Example [Input Data] 1-digit 00010001 (DD RAM right shift) 00010010 (MK RAM right shift) 00010011 (DD,MK RAM right shift) 00 0F [Correspondence of DD RAM, MK RAM Address and Display] 8-digit 01 00 02 01 03 02 04 03 05 04 06 05 07 06 08 07 ← MK RAM MK ← DD RAM DD ← MK RAM MK ← DD RAM DD ← MK RAM MK ← DD RAM DD 0F 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 0F 0F 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 *In spite of display digits, the data of 16-digit is required to write into DD RAM. NJU3430 NJU3430 (f)Display (f)Display Blink Set RS 0 B7 0 B6 0 B5 1 B4 B2 B3 B1 B2 B0 B1 M B0 D One One blink state of Character and Icon is selected from among eight-step blink state by Display Blink Set. NonBlink is selected after Reset. The optional blink state should be selected before display operation. B2 0 0 : 1 1 B1 0 0 : 1 1 B0 0 1 : 0 1 Blink Blink at at about about 0.6s 0.7s Non-Blink Blink at about 0.1s : S T A T U S M 0 1 F U N C T I O N The blink operation is not available. The blink oparation is selected for Icon. D 0 1 F U N C T I O N The blink operation is not available. The blink oparation is selected for Character. *At *At fOSC=360kHz (g)Display Digits Set RS 0 B7 0 B6 1 B5 0 B4 0 B3 0 B2 C2 B1 C1 B0 C0 The The number of display digits is selected from among 9-digit to 16-digit by Display Digits Set. 16-digit is selected after Reset. The optional number of display digits should be selected before display operation. C2 0 0 : 1 1 C1 0 0 : 1 1 C0 0 1 : 0 1 Display Digits 16-digit display 9-digit : 14-digit display 15-digit display display NJU3430 NJU3430 (h)RAM (h)RAM Address Set RS B7 1 0 1 1 B6 0 0 1 B5 0 0 AC5 B4 0 1 AC4 B3 B2 B1 AD1 B0 AD0 AD3 AD2 ← DD RAM Addredd Set:(00)H to (0F)H DD to ← MK RAM Address Set:(00)H to (0F)H MK to ← CG RAM Address Set:(00)H to (3F)H CG to AM3 AM2 AM1 AM0 AC3 AC2 AC1 AC0 The The DD RAM, MK RAM and CG RAM Address are set by RAM Address Set. Correspondences of each RAM address and Display position are shown below : Correspondence Correspondence of DD RAM Address and Timing terminals (Not shift) DD RAM Address 00 Digits 1 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 0E 15 0F 16 Correspondence Correspondence of MK RAM Address and Timing terminals (Not shift) MK RAM Address 00 Digits 1 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 0E 15 0F 16 About the detail of CG RAM Address, refer to "(1)CG RAM data and Character Dot Matrix”. (i)Write Data to RAM RS B7 SD7 1 0 0 B6 SD6 0 0 B5 SD5 0 0 B4 SD4 0 SC4 B3 B2 B1 SD1 B0 SD0 SD3 SD2 0 0 ← DD RAM Data Set:(00)H to (FF)H DD to ← MK RAM Data Set:(00)H to (03)H MK to ← CG RAM Data Set:(00)H to (1F)H CG to SM1 SM0 SC1 SC0 SC3 SC2 The The data are written into DD RAM, MK RAM and CG RAM by Write Data to RAM. The writing data address is used that is set the address just before writing data. Therefore, when the new data writing, the address set should be executed before writing data. The address is increased by 1 automatically after writing data, therefore, the MPU writes the data into the each RAM without any address setting after the start address. (Writing (Writing example) 1Byte 10000011 DD RAM Address set(03) set(03)H 2Byte 01010101 set set CG ROM(55)H 3Byte 11111000 set set CG ROM(F8)H 4Byte 00110101 set set CG ROM(35)H DD RAM Address(03)H DD RAM Address(04)H DD RAM Address(05)H DD DD The The writing data in the each RAM are shown below. DD RAM Data[SD7 to SD0] --- Character code of each digit MK MK RAM Data[SM1 to SM0] --- Icon display of each digit CG CG RAM Data[SC4 to SC0] --- Character code : (00)H to (FF)H to : SM1→MK2, SM0→MK1 : (00)H to (0F)H Dot Data to Dot (About the detail, refer to "(1)CG RAM data and Character Dot Matrix”.) NJU3430 NJU3430 n Interface with MPU Interface The instruction and RAM data are input through the serial port. The data form is 8-bit per word, and data transfer is performed by synchronizing clock. The shift clock is input from external, and the data is loaded at the rising edge of the shift clock. One time transfer is executed by 8-bit unit. The transfer period is from falling edge to rising of the CS signal from external. Therefore, when the rising edge of the CS signal is input, the operation is started. When more than 8-bit data is input, the last 8-bit data is valid. The input data is judged as instruction or RAM data by the RS signal at the rising edge of the CS signal (RS=”H” : RAM data, RS=”L” : Instruction). When the input data is RAM data, the RAM address is increased one by one automatically after data writing. CS CLK RS SI B7 B6 B5 B4 B3 B2 B1 B0 MSB 1Byte (Instruction) LSB B7 B6 B5 B4 B3 B2 B1 B0 MSB 2Byte (Data) Character Code Data LSB B7 B6 B5 B4 B3 B2 B1 B0 MSB 3Byte (Data) Character Code Data of the Next Address LSB [For example] DD RAM writing Select the Address n ABSOLUTE MAXIMUM RATINGS ABSOLUTE PARAMETER Supply Voltage (1) Supply Voltage (2) Input Voltage Power Dissipation Storage Temperature Operating Temperature SYMBOL RATINGS -0.3 to 6.5 - 4 0 t o V D D +0.3 - 0 . 3 t o V D D +0.3 800 -55 to 125 -40 to 85 -40 -20 -10 -4.0 -100 100 UNIT V V V mW °C °C mA mA mA mA mA mA CONDITIONS V DD V FDP V IN PD T stg Topr IO 1 IO 2 Ta ≤ 2 5 ° C QFP-64 T 1 - T 16 M K 1 - MK2 S 1 - S 35 P 1(LED drive is available) All Terminals at "H" level All Terminals at "L" level Output Current IO 3 IO 4 Total Output Current Σ IOH Σ IO L Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note 2) Decoupling capacitor should be connected between VDD and VSS, VFDP and VSS due to the stabilized and and due operation for the LSI. Note 3) All voltage values are specified as VSS = 0V. 0V. The relation : VDD > VSS, VDD > VSS ≥ VFDP, VSS=0V must be maintained. NJU3430 NJU3430 - Timing Chart Timing tCSU CS P CS W tCYCE tSC tSC tSISU tSIH VIH VIL tCH VIH VIL CLK SI tRS tRH VIH VIL VIH RS Fig.1 Data Input Timing VIL VDD tPRZ tRSOFF tRSON tRSL tRSL 0.8 DD V VSS VIH VIL RST VIH SI Fig.2 Reset Timing VIL tR tR 0.8 DD V 0.2 FDP V Fig.3 Output Timing (CL=100pF, tR=20 to 80% or 80 to 20%) NJU3430 NJU3430 n VFD DRIVING WAVE FORM VFD tC E YC OSC1 tDG tB K T1 T2 T3 : : T16 tS P S1 to S35 MK1 to MK2 Oscillation Frequency Minimum Blanking Time (Duty15/16) 1-character Display Time 1-cycle Display Time : tCYCE : tBK=t CYCE x 4 : tDG=t BK x 16 16 : tSP=t DG x Digits Digits NJU3430 NJU3430 n APPLICATION CIRCUIT APPLICATION 5x7 Dot Matrix V FD Display H eater AO N DE A O E ND G RID VDD VDD MK1-M 2 S1 - 35 K S T1 -T16 VDD MC U O ut p ut P or t RS T CS CL K S I RS VS S NJU3 4 30 P1 VS S VFDP O C1 S O SC2 LD E VFDP Z D MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.