NJU3553L

NJU3553 PRELIMINARY 4-BIT SINGLE CHIP OTP MICRO CONTROLLER s GENERAL DESCRIPTION The NJU3553 is the C-MOS 4-bit Single Chip OTP type Micro Controller with programmable Flash Memory. It is completely compatible with the NJU3503 in function and the pin configuration. Therefore, the NJU3553 is suitable for the final evaluation before NJU3503 mask generation, the small quantity production and short leadtime. * In this data sheet, only OTP programming and the difference between NJU3553 and NJU3503 are mentioned mainly. Therefore the detail function and specification should be referred on the NJU3503 data sheet. s PACKAGE OUTLINE NJU3553L NJU3553M s FEATURES q q q q q Internal One Time Programmable ROM 2,048 X 8bits Internal Data RAM 128 X 4bits W ide operating voltage range 2.7V ~ 5.5V Package outline SDIP28 / SDMP30 (Compatible with NJU3503) ROM programmer “SUPERPRO/L” by XELTEK co,. s PIN CONFIGURATION IN OTP PROGRAMMING MODE [ SDIP28 ] [ SDMP30 ] D3 D4 D5 D6 D7 VDD CNT1 CNT2 1 2 3 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD RESET D2 D1 D0 D3 D4 D5 Open D6 D7 VDD CNT1 CNT2 7 8 9 10 11 12 13 VSS 14 NJU3553L 5 6 Open Open Open PROM REQ CLK VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD RESET D2 D1 D0 NJU3553M Open PROM Open REQ CLK Note) The pin configuration in Normal operating mode is the same as NJU3503. -1- NJU3553 s BLOCK DIAGRAM -2NJU3553 Interrupt CPU CORE Logic VDD VSS INT1 EXTI/PF0 INT2 TIMER1 STACK X Reg Y Reg AC TEST RESET INT3 CNTI/PF1 TIMER2 X’ Reg MUX Y’ Reg TLU addr PC INT4 SDO/PG0 PRESCALER SDI(O)/PG1 SIO SCK/CKOUT OTP ROM ALU CPU TIMING GENERATOR 2048 x 8 bits AIN0/PD0 OSC OSC1 OSC2 AIN1/PD1 AIN2/PD2 AIN3/PD3 IR RAM 128 x 4 bits ID AIN4/PE0 STANDBY CONTROLLER A/D AIN5/PE1 PE2 VREF/PC1 ADCK/PC0 AVDD PORT_A PORT_B PA0 PA1 PA2 PA3 PB0 PB1 PB2 * Refer [INPUT OUTPUT TERMINAL TYPE] NJU3553 s TERMINAL DESCRIPTION IN OTP PROGRAMMING MODE No. NJU NJU 3553L 3553M 27 24-26, 1-5 7, 8 16 15 17 6, 28 14 Note 1) 2) 29 26-28, 1-3, 5, 6 8, 9 17 16 19 7, 30 15 SYMBOL RESET D0 - D7 CNT1 CNT2 REQ CLK PROM VDD VSS INPUT / OUTPUT INPUT FUNCTION RESET terminal. When the low-level input-signal, the system is initialized. INPUT/OUTPUT Data bus INPUT INPUT OUTPUT INPUT INPUT OTP control input terminal Request output terminal Clock input terminal OTP programming enable terminal Power Source (5V) Power Source (0V) Use at VDD=5V in OTP programming mode. Non connect anything to the other terminals. s Difference between NJU3553 (OTP version) and NJU3503 (MASK version) q Operating mode NJU3553 has two operating modes. One is ”Normal operating mode” and the other is “OTP programming mode”. • Normal operating mode The ”TEST” terminal is set to low level. (The terminal is recommended to connect to GND.) Operating voltage range; 2.7V ~ 5.5V. OTP Programming mode User program is read out from or written into the OTP by the universal programmer “SUPERPRO/L” and converting adapter made by XELTEK co,.(USA). Reset Terminal Type Internal Pull-up Resistance NJU3553 W ith Pull-up NJU3503 W ithout Pull-up • q q Option information set in the initialization When the initialization is performed(RESET terminal is “L”), the operation information stored in option area is set as shown in the following timing chart . The option information is set in the term of 1 / fOSC x 512clock after RESET releasing and oscillation stability time. After information set, the program counter is set to 0000H and the NJU3553 operates in normal. [ TIMING CHART ] Oscillation Stability Time Oscillator Clock Option information setting 1/fOSCx512clock Normal Operation Oscillation Start PC=0000H RESET about 128µsec fOSC=4MHz -3- NJU3553 s ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER Supply Voltage Input Voltage Output Voltage Analog Supply Voltage Analog Reference Voltage Analog Input Voltage Operating Temperature Storage Temperature SYMBOL VDD VIN VOUT AVDD VREF AIN0 ~ AIN5 Topr Tstg RATINGS -0.3 ~ +7.0 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -0.3 ~ AVDD + 0.3 -0.3 ~ AVDD + 0.3 -20 ~ +75 -55 ~ +125 UNIT V V V V V V °C °C Note) The difference of electrical characteristics between NJU3553 (OTP version) and NJU3503 (MASK version) NJU3503 • NJU3553 → → → → → → → → → 2.7V Supply Voltage (VDD) MIN. Supply Current 5V (IDD1) Max. (IDD2) Max. (IDD3) Max. (IDD4) Max. (IDD5) Max. 3V (IDD1) Max. (IDD2) Max. (IDD3) Max. (IDD4) Max. (IDD5) Max. 2.4V • 1.2mA 1.2mA 1.6mA 3.6mA 4.0µA 0.5mA 0.5mA 0.6mA 1.0mA 2.0µA 30mA 30mA 30mA 30mA 20µA 20mA 20mA 20mA 20mA 20µA -4- NJU3553 s ELECTRICAL CHARACTERISTICS SYM BOL VDD DC CHARACTERISTICS 1-1 (VDD=3.6~5.5V, VSS=0V, Ta=-20~75°C) PARAMETER Supply Voltage CONDITIONS MIN 3.6 TYP MAX 5.5 30 UNIT NOTE V mA *3 VDD VDD IDD1 VDD=5V, fOSC=2MHz X’tal Oscillation in Reset VDD IDD2 VDD=5V, fOSC=2MHz Ceramic Oscillation in Reset VDD IDD3 VDD=5V, fOSC=2MHz Supply Current CR Oscillation in Reset VDD IDD4 VDD=5V, fOSC=4MHz Operating (Except ADC) VDD IDD5 VDD=5V, STANDBY Mode AVDD IADD AVDD=VDD=5V, ADCK=225kHz PA0~PA3, AIN0/PD0~ AIN3/PD3, VIH1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT High-Level Input Voltage PB0~PB2, ADCK/PC0, VREF/PC1, VIH2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIH3 PA0~PA3, AIN0/PD0~ AIN3/PD3, VIL1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT Low-level Input Voltage PB0~PB2, ADCK/PC0, VREF/PC1, VIL2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIL3 *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. 30 mA *3 30 mA *3 30 20 3.0 0.7VDD 0.8VDD VDD-1.0 0 0 0 5.0 VDD VDD VDD 0.3VDD 0.2VDD 1.0 mA µA mA V V V V V V *3 *3 *3 *1 *1 *1 *1 -5- NJU3553 s ELECTRICAL CHARACTERISTICS SYM BOL DC CHARACTERISTICS 1-2 (VDD=3.6~5.5V, VSS=0V, Ta=-20~75°C) PARAMETER CONDITIONS MIN TYP MAX UNIT NOTE VDD=5.5V, VIN=5.5V PA0~PA3, PB0~PB2, ADCK/PC0, High-Level VREF/PC1, AIN0/PD0~AIN3/PD3, IIH Input Current AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET VDD=5.5V, VIN=0V Without pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL1 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, Low-Level SCK/CKOUT Input Current VDD=5.5V, VIN=0V With pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL2 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET IOH=-100µA High-Level VOH PB0~PB2, SDO/PG0, SDI(O)/PG1, Output Voltage SCK/CKOUT IOL1=400µA VOL1 PB0~PB2, SDO/PG0, SDI(O)/PG1, Low-Level SCK/CKOUT Output Voltage IOL2=15mA VOL2 PA0~PA3, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2 VDD=5.5V, VOH=5.5V Output Leakage IOD PA0~PA3, AIN0/PD0~AIN3/PD3, Current AIN4/PE0, AIN5/PE1, PE2 Except VDD, VSS terminals Input Capacitance CIN fOSC=1MHz Other terminals : 0V *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. 10 µA *1 -10 µA *1 -100 µA *1 VDD-0.5 V *2 0.5 V *2 2.0 V µA pF *2 10 *2 10 20 -6- NJU3553 s ELECTRICAL CHARACTERISTICS SYM BOL VDD DC CHARACTERISTICS 2-1 (VDD=2.7~3.6V, VSS=0V, Ta=-20~75°C) PARAMETER Supply Voltage CONDITIONS MIN 2.7 TYP MAX 3.6 20 UNIT NOTE V mA *3 VDD VDD IDD1 VDD=3V, fOSC=1MHz X’tal Oscillation in Reset VDD IDD2 VDD=3V, fOSC=1MHz Ceramic Oscillation in Reset VDD IDD3 VDD=3V, fOSC=1MHz Supply Current CR Oscillation in Reset VDD IDD4 VDD=3V, fOSC=2MHz Operating (Except ADC) VDD IDD5 VDD=3V, STANDBY Mode AVDD IADD AVDD=VDD=3V, ADCK=225kHz PA0~PA3, AIN0/PD0~AIN3/PD3, VIH1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT High-Level Input Current PB0~PB2, ADCK/PC0, VREF/PC1, VIH2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIH3 PA0~PA3, AIN0/PD0~AIN3/PD3, VIL1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT Low-Level Input Voltage PB0~PB2, ADCK/PC0, VREF/PC1, VIL2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIL3 *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. 20 mA *3 20 mA *3 20 20 2.5 0.8VDD 0.85VDD VDD-0.3 0 0 0 3.5 VDD VDD VDD 0.2VDD 0.15VDD 0.3 mA µA mA V V V V V V *3 *3 *3 *1 *1 *1 *1 -7- NJU3553 s ELECTRICAL CHARACTERISTICS SYM BOL DC CHARACTERISTICS 2-2 (VDD=2.7~3.6V, VSS=0V, Ta=-20~75°C) PARAMETER CONDITIONS MIN TYP MAX UNIT NOTE VDD=3.6V, VIN=3.6V PA0~PA3, PB0~PB2, ADCK/PC0, High-Level VREF/PC1, AIN0/PD0~AIN3/PD3, IIH Input Current AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET VDD=3.6V, VIN=0V Without pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL1 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, Low-Level SCK/CKOUT Input Current VDD=3.6V, VIN=0V With pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL2 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET IOH=-80µA High-Level VOH PB0~PB2, SDO/PG0, SDI(O)/PG1, Output Voltage SCK/CKOUT IOL1=350µA VOL1 PB0~PB2, SDO/PG0, SDI(O)/PG1, Low-Level SCK/CKOUT Output Voltage IOL2=5mA VOL2 PA0~PA3, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2 VDD=3.6V, VOH=3.6V Output Leakage IOD PA0~PA3, AIN0/PD0~AIN3/PD3, Current AIN4/PE0, AIN5/PE1, PE2 Except VDD, VSS terminals fOSC=1MHz Input Capacitance CIN Other terminals : 0Ｖ *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. 10 µA *1 -10 µA *1 -100 µA *1 VDD-0.5 V *2 0.5 V *2 1.0 V µA *2 10 *2 10 20 pF -8- NJU3553 s ELECTRICAL CHARACTERISTICS SYM BOL AC CHARACTERISTICS 1 (VSS=0V, Ta= -20~75°C) PARAMETER CONDITIONS X’tal Resonator Ceramic Resonator External Resistor Oscillation External Clock X’tal Resonator Ceramic Resonator External Resistor Oscillation External Clock MIN 0.03 0.03 0.03 0.03 0.03 0.03 0.03 0.03 TYP MAX 2.0 2.0 1.0 2.0 4.0 4.0 2.0 4.0 UNIT VDD=2.7~3.6V Operating Frequency fOSC VDD=3.6~5.5V MHz Instruction Cycle Time External Clock Pulse Width External Clock Rise Time Fall Time RESET Low-Level Width RESET Rise Time Port Input Level Width Edge Detection (PB1) Rise Time Fall Time Restart Signal (PB0) Rise Time External interrupt input (EXTI) Rise Time Fall Time CNTI Clock Frequency CNTI High-Level Width CNTI Rise Time Fall Time tC tCPH tCPL tCPR tCPF tRST tRSR tPIN tEDR tEDF tSTR VDD=2.7~3.6V VDD=3.6~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V 6/fOSC 4/fOSC 250 125 6/fOSC 16600 16600 20 s ns ns s 20 ms s 200 200 ns ns tEXR tEXF fCT tCT tCTR tCTF VDD=2.7~5.5V 200 ns VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V 6/fOSC fOSC/64 Hz s 200 ns -9- NJU3553 s AC CHARACTERISTICS 1 EXTERNAL CLOCK OSC1 TIMING CHART 1/fOSC VIH3 VIL3 tCPH tCPF tRST tCPL tRSR VIH2 VIL2 tCPR RESET INPUT RESET PORT INPUT tPIN VIH1, VIH2 PORT VIL1, VIL2 EDGE DETECTOR INPUT tEDR VIH2 VIL2 RESTART SIGNAL INPUT tSTR VIH2 PB0 VIL2 EXTERNAL INTERRUPT tEXR VIH2 EXTI VIL2 TIMER2 EXTERNAL CLOCK TIMING CHART 1/fCT CNTI VIH2 VIL2 tCTR tCT tCTF tEXF tEDF PB1 - 10 - NJU3553 s ELECTRICAL CHARACTERISTICS SYM BOL fSC AC CHARACTERISTICS 2 SERIAL INTERFACE (VSS=0V, VDD=2.7~5.5V, Ta= -20~75°C) PARAMETER Serial Operating Frequency Clock Pulse Width Low-Level CONDITIONS Internal Clock External Clock Internal Clock External Clock Clock Pulse Width High-Level Internal Clock VDD=2.7~3.6V fOSC=2MHz VDD=3.6~5.5V fOSC=4MHz VDD=2.7~3.6V fOSC=2MHz VDD=3.6~5.5V fOSC=4MHz MIN TYP MAX UNIT (1/12)×fOSC* Hz 500k 3.0 1.5 1.0 3.0 1.5 1.0 0.5 0.5 0.5 µs µs µs µs µs tSCL tSCH External Clock SDI setup Time tDS To SCK SDI Hold time tDH To SCK SDO Data t Fix Time To SCK DCD * The dividing ratio of the internal clock is 1/2. s AC CHARACTERISTICS 2 SERIAL INTERFACE TIMING CHART 1/fSC tSCL tSCH VIH1 SCK VIL1 tDS SDI(O) tDH VIH1 INPUT DATA VIL1 tDCD VOH SDO/SDI(O) VOL1 OUTPUT DATA - 11 - NJU3553 s ELECTRICAL CHARACTERISTICS A/D CONVERTER CHARACTERISTICS (VDD=AVDD=2.7~5.5V, VSS=0V, Ta=25°C, fOSC=4MHz) PARAMETER Resolution Absolute Accuracy Conversion Time Reference Voltage Analog Input Voltage ADCK Frequency SYMBOL tCONV VREF VIA fADCK VDD=5V, AVDD=5V, VREF=5V VDD=5V, AVDD=5V, VREF=5V 40 2.7 VSS AVDD VREF 225 CONDITIONS MIN TYP 8 MAX ±2 UNIT bits LSB µs V V kHz - 12 - NJU3553 s OPTION as same as mask version (NJU3503) 1) INPUT OUTPUT Terminal Selection All of input-output terminals select a terminal type for each port from the following table1 and table2 by the mask option. [ CIRCUIT TYPE TABLE 1 ] TERMINAL TYPES Input / Output Terminal*1 SYMBOL Programmable Input / Output Port of Output Port of Input EXTRA FUNCTION REMARKS PA0 PA1 PA2 PA3 PB0 PB1 PB2 ISP IS ISP IS OC OC IOP IO IOP IO IOP IO IOP IO Restart signal input Edge detection E D R F D With restart input Without restart input Rise edge detection Fall edge detection Without edge detection ISP OC IS ACP External clock input ADCK / PC0 ISP AC (ADCK) *2 IS AD Reference input VREF / PC1 ISP (VREF) *2 IS AD Analog input to ADC AIN0 / PD0 ICP ONP (AIN0) *2 IC ON AD Analog input to ADC AIN1 / PD1 ICP ONP (AIN1) *2 IC ON AD Analog input to ADC AIN2/ PD2 ICP ONP (AIN2) *2 IC ON AD Analog input to ADC AIN3 / PD3 ICP ONP (AIN3) *2 IC ON AD Analog input to ADC AIN4 / PE0 ICP ONP (AIN4) *2 IC ON AD Analog input to ADC AIN5 / PE1 ICP ONP (AIN5) *2 IC ON PE2 ICP ONP IC ON Note) The symbol in the above table is the same as in mask option generator software. *1) The symbol and the detail circuits of INPUT OUTPUT TERMINAL are written in INPUT OUTPUT TERMINAL TYPE. *2) The pull-up resistance is added to the terminal selected as the extra function. - 13 - NJU3553 [ CIRCUIT TYPE TABLE 2 ] TERMINAL TYPES Input / Output Terminal*1 SYMBOL Programmable Input / Output Port of Output Port of Input EXTRA FUNCTION REMARKS EXTI / PF0 CNTI /PF1 SDO / PG0 SDI(O) / PG1 *2 SCK / CKOUT *2 *3 ISP IS ISP IS ICP IC OC OC IIP II IIP II SO SDP SD SCP SC - External interrupt input R Rise interrupt input (EXTI) F Fall interrupt input External clock of Timer 2 input (CNTI) Serial data output MSB MSB first Serial data input/output LSB LSB first Serial clock input/output Output clock divide by pre-scaler Note) The symbol in the above table is the same as in mask option generator software. *1) The symbol and the detail circuits of INPUT OUTPUT TERMINAL are written in INPUT OUTPUT TERMINAL TYPE. *2) The pull-up resistance is added to the terminal selected as the extra function. *3) When Serial INPUT-OUTPUT is selected, “SCK” is selected automatically. When it is not selected, “CKOUT” is selected automatically. - 14 - NJU3553 [MASK OPTION LIST] SYM BOL ICP ISP IC IS ONP OC ON IIP II SDP SD SO SCP SC AD ACP AC IOP IO FUNCTION C-MOS input with pull-up resistance C-MOS Schmitt trigger input with pull-up resistance C-MOS input C-MOS Schmitt trigger input Nch-FET Open-Drain output with pull-up resistance C-MOS output Nch-FET Open-Drain output External interrupt resistance External interrupt input Serial data resistance input/output with pull-up input with pull-up SYM BOL R F D MSB LSB 1 2 3 4 5 6 7 8 9 a b c E D FUNCTION Rise edge detection Fall edge detection Prohibition of edge detection Serial data order MSB first Serial data order LSB first 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096 permission prohibit Serial data input/output Serial data output Serial clock input/output with pull-up resistance Serial clock input/output A/D converter External clock input with pull-up resistance for ADC External clock input for ADC Programmable input/output with pull-up resistance Programmable input/output - 15 - NJU3553 [ INPUT OUTPUT TERMINAL TYPE ] Types With Pull-up Type ICP Without Pull-up Type IC Terminals AIN0/PD0 ~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1 C-MOS INPUT TERMINAL Type ISP SCHMITT TRIGGER Type IS PB0~PB2, ADCK/PC0, VREF/PC1, EXTI/PF0, CNTI/PF1 Type ON PB0~PB2, SDO/PG0, SDI(O)/PG1 C-MOS OUTPUT TERMINAL Type ONP N-channel(Nch) OPEN DRAIN Type ON AIN0/PD0 ~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2 PROGRAMMABLE INPUT OUTPUT TERMINAL Type IOP Type IO PA0~PA3 C-MOS INPUT / Nch OPEN DRAIN OUTPUT - 16 - NJU3553 2) Re-start signal Input Selection PB0 terminal performs as the re-start terminal to return from “STANDBY” mode. It is selected by mask option. The STANDBY mode is released by the rising edge of the input signal to PB0 terminal, and the CPU restarts the execution from the last address before the STANDBY mode in. 3) Edge Detector Selection PB1 terminal is added the “Edge detect function” by the mask option. Rising edge Falling edge 4) External Interrupt of the edge Selection When the interrupt function is set by mask option. PF0 terminal performs as the interrupt input terminal. The polarity of the edge, rising as “low to high” or falling as “high to low”, is selected by the mask option. Rising edge Falling edge 5) The data order (MSB, LSB) of the Serial Interface The data order of the Serial Interface is selected select either MSB or LSB first by the mask option. 6) A/D Control Clock A/D Control Clock is selected either the external clock from ADCK terminal or the internal clock from the prescaler by the mask option. 7) Dividing ration of the internal clock Each dividing ration of the count clocks of Timer1 and Timer2, the Internal shift clock of the Serial Interface, the clock of the A/D control clock and the output clock through the SCK/CKOUT terminal is selected among the following by the mask option. The frequency of each clock is determined by the dividing ration and the 1-instruction term (1/fOSCx6). 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024, 1/2048, 1/4096 Note) As Timer2 clock, the external clock or the internal is selected by the program. As the shift clock of the serial interface, the external clock or the internal is selected by the program. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 17 -