NJU3610FR3

NJU3610 1bit Delta-Sigma Stereo ADC General Description The NJU3610 is the stereo Analog to Digital Convector (ADC) that covers from 8 to 192 kHz sampling frequency. The NJU3610 provides 1bit Delta-Sigma technology with high accuracy and low power consumption. The analog inputs are differential signal and stereo 4-1 selectors are provided. The NJU3610 provides two power-supply 1.8V / 3.3V(typical) or single power-supply 3.3V(typical) application. Package Features NJU3610FR3 1bit Delta-Sigma stereo ADC 64fs over sampling (MCK=256fs, 384fs) 32fs over sampling (MCK=128fs) Digital Filter High-pass filter Stereo 4-1 selectors Sampling Rate : 8 to 192kHz Dynamic Range : 100dB(typ@3.3V, 96kHz) S/N : 100dB(typ@3.3V, 96kHz) S/(N+D) : 90dB(typ@3.3V, 48kHz, -1.0dBFS) Master Clock : 128fs(8 to 192kHz), 256fs / 384fs(8 to 96kHz) Power Supply : Single power supply 3.0 to 3.6V(3.3Vtyp) B uilt-in regulator using together : Two power supply 3.0 to 3.6V(Analog, I/O:3.3Vtyp) 1.65 to 2.0V(Digital:1.8Vtyp) Digital Audio Format : 24/16bit Left-justified, I2S Master/Slave Operating Temperature : -40 to +85°C Package : LQFP48-R3 (Pb-Free) Ver.2009.12.4 -1- NJU3610 Function Block Diagram AINLP1 AINLN1 AINLP2 AINLN2 AINLP3 AINLN3 AINLP4 AINLN4 SEL0 SEL1 AINRP1 AINRN1 AINRP2 AINRN2 AINRP3 AINRN3 AINRP4 AINRN4 VCOM REFLP REFLN REFRP REFRN VREGI VREGO 4-1 Selector Lch 5th Order Delta-Sigma Modulator Lch 1bit PDM 24bit PCM Feedback 1bit DAC Lch Decimation Digital Filter with BCK LRCK Serial Audio Interface SDO Feedback 1bit DAC Rch 4-1 Selector Rch 5th Order Delta-Sigma Modulator Rch Reference each Analog Blocks High-Pass Filter FMT0 FMT1 24bit PCM 1bit PDM Clock(64 or 32Fs) / Control Signal Reference Voltage Regulator Power Clock and Timing Control Power Control Power MCK MODE0 MODE1 HPF RESETb PDNb AVDD AVSS VDD18 VDD33 VSS AVDD/AVSS : Analog Power Supply (typ:3.3V) VDD18 : Digital Logic (typ:1.8V) VDD33 : Digital I/O (typ:3.3V) VSS : Digital GND and Regulator GND Fig. 1 NJU3610 Block Diagram -2- Ver. 2009.12.4 NJU3610 Pin Configuration AINRN3 AINRN2 AINRN1 AINRP3 AINRP2 AINRP1 AIVSS AVDD RESETb 26 MODE1 MODE0 36 35 34 33 32 31 30 29 28 27 25 PDNb AINRN4 AINRP4 REFRP REFRN VCOM AVDD AVSS TEST REFLN REFLP AINLP4 AINLN4 37 38 39 40 41 42 43 44 45 46 47 48 10 12 11 24 23 22 21 20 19 18 17 16 15 14 13 SEL1 SEL0 FMT1 FMT0 MCK VDD33 VDD18 VSS HPF BCK LRCK SDO NJU3610FR3 1 2 3 4 5 6 7 8 AVDD AINLP3 AINLP2 AINLP1 AINLN3 AINLN2 AINLN1 VDD33 9 Fig.2 NJU3610 Pin Configuration Ver.2009.12.4 VREGO AVSS VSS VREGI -3- NJU3610 Pin Description Table.1 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol AINLP3 AINLN3 AINLP2 AINLN2 AINLP1 AINLN1 AVSS AVDD VDD33 VSS VREGI VREGO SDO LRCK BCK HPF VSS VDD18 VDD33 MCK FMT0 FMT1 SEL0 SEL1 PDNb RESETb MODE0 MODE1 AVDD AVSS AINRN1 AINRP1 AINRN2 AINRP2 AINRN3 AINRP3 AINRN4 AINRP4 REFRP REFRN VCOM AVDD AVSS TEST REFLN REFLP AINLP4 AINLN4 I/O AI AI AI AI AI AI AG AP DP DG RI RO DO DIO DIO DI DG DL DP DI DI DI DI DI DI DI DI DI AP AG AI AI AI AI AI AI AI AI AI AI AO AP AG AI AI AI AI AI Description Lch Analog Positive Input 3 Pin Lch Analog Negative Input 3 Pin Lch Analog Positive Input 2 Pin Lch Analog Negative Input 2 Pin Lch Analog Positive Input 1 Pin Lch Analog Negative Input 1 Pin Analog Ground Pin Analog Power Supply Pin, 3.3V Digital Power Supply Pin, 3.3V Digital Ground Pin Built-in Regulator Input Pin, 3.3V Built-in Regulator Output Pin, 1.8V (typ) Audio Serial Data Output Pin LR Clock Bit Clock HPF for Off-set Cancel (“H”: ON, “L”: OFF) Digital Ground Pin Digital Power Supply Pin, 1.8V Digital Power Supply Pin, 3.3V Master Clock Input Pin Control Serial Data Format 0 Pin Control Serial Data Format 1 Pin Control Input Selector 0 Pin Control Input Selector 1 Pin Power Down Mode Pin (”H”: Power up, “L”: Power down) Reset Pin (“H”: Reset OFF, “L”: Reset ON) Control Mode 0 Pin Control Mode 1 Pin Analog Power Supply Pin, 3.3V Analog Ground Pin Rch Analog Negative Input 1 Pin Rch Analog Positive Input 1 Pin Rch Analog Negative Input 2 Pin Rch Analog Positive Input 2 Pin Rch Analog Negative Input 3 Pin Rch Analog Positive Input 3 Pin Rch Analog Negative Input 4 Pin Rch Analog Positive Input 4 Pin Rch Voltage Reference Input Pin, AVDD Rch Voltage Reference Input Pin, GND Common Voltage Output Pin, AVDD/2 Connected to AVSS with a 10uF electrolytic capacitor. Analog Power Supply Pin, 3.3V Analog Ground Pin Test Pin (Connected to AVSS) Lch Voltage Reference Input Pin, GND Lch Voltage Reference Input Pin, AVDD Lch Analog Positive Input 4 Pin Lch Analog Negative Input 4 Pin * AP : Analog power supply, 3.3V AO : Analog output DL : Digital power supply, 1.8V RI : built-in regulator input DI : Digital input DIO : Bi-directional of Digital AG : Analog ground AI : Analog input DP : Digital power supply, 3.3V DG : Digital ground and built-in regulator ground RO : built-in regulator output DO : Digital output -4- Ver. 2009.12.4 NJU3610 Absolute Maximum Ratings Table 2. Absolute Maximum Ratings Parameter Analog Digital Power supplies Built-in Regulator Input Built-in Regulator Output Digital Input Pin Voltage Digital Output Analog Input VCOM Output Power Dissipation Operating Temperature Storage Temperature * AVDD * VDD33 * VDD18 * VREGI * VREGO * VX(IN) * VX(OUT) * VX(AIN) * VX(VCOM) Note 1) Symbol AVDD VDD33 VDD18 VREGI VREGO Vx(IN) Vx(OUT) Vx(AIN) Vx(VCOM) PD TOPR TSTR 800 Mounted on two-layer board of based on the JEDEC. (VSS=AVSS=0V=GND, Ta=25°C) Rating -0.3 to +4.2 -0.3 to +2.3 -0.3 to +4.2 -0.3 to +2.3 -0.3 to +5.5 (VDD33≥3.0V) -0.3 to +4.2 (VDD3396KHz, MCK should be 128fs. The ADC operates with the next frequency. The operate frequency is 64fs in case of fs≦96KHz. The operate frequency is 32fs in case of fs>96KHz. Mode0 and mode1 terminals select the MCK frequency and ADC operating frequency. In case that ADC operating frequency is 32fs, the effective bandwidth is 1/4fs. Between 1/4fs and 1/2fs, ADC shaping noise exists. The NJU3610 digital audio format provides Left-justified and I2S 24bit(BCK=64clocks/fs) in Master mode. The NJU3610 digital audio format provides Left-justified, I2S 16bit (BCK=32clocks/fs) and I2S 24bit(BCK=64clocks/fs) in Slave mode. FMT0 and FMT1 terminals select the above digital audio format. When FMT0, FMT1, MODE0 and MODE1 are changed, RESET should be done again. MCK, BCK and LRCK frequency is shown in table11. Digital Audio Format and operation mode is shown in table12. In Master mode, BCK and LRCK terminals generate clocks. BCK output clock is fixed at 64fs in Master mode. In Slave mode, BCK and LRCK terminals are assigned input. Table 11. LRCK(kHz) Master: Generation from MCK Slave: From outside M CK, BCK, LRCK (1) BCK(MHz) 384fs 32fs S lave only: from outside MCK (MHz) 128fs 256fs 64fs Master: Generation from MCK Slave: From outside 8 -*2 2.048 3.072 0.256 0.512 16 -*2 4.096 6.144 0.512 1.024 22.05 -*2 5.6448 8.4672 0.7056 1.4112 32 -*2 8.192 12.288 1.024 2.048 44.1 -*2 11.2896 16.9344 1.4112 2.8224 48 -*2 12.288 18.432 1.536 3.072 64 -*2 16.384 24.576 2.048 4.096 88.2 -*2 22.5792 33.8688 2.8224 5.6448 96 -*2 24.576 36.864 3.072 6.144 *1 176.4 22.5792 5.6448 11.2896 192 *1 24.576 6.144 12.288 *1 It is only a setting of “CKMODE[1:0]=10,11”. At this time, frequency bandwidth is up to 1/4fs. The shaping noise of the ADC is included in the band from 1/4fs to 1/2fs. *2 Because an effective bandwidth is limited, it is not practicable. Ver.2009.12.4 - 11 - NJU3610 CMKODE 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 FMT 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 12. MCK,BCK,LRCK (2) Master / A/D MCK Slave mode (fs) Slave 64fs Master Slave 64fs Master Slave 32fs Master Slave 32fs Master 256fs (≦96kHz) Format I2S (32 or 64fs) Left-justified(32 or 64fs) I2S (64fs) Left-justified(64fs) I2S (32 or 64fs) Left-justified(32 or 64fs) I2S (64fs) Left-justified(64fs) I2S (32 or 64fs) Left-justified(32 or 64fs) I2S (64fs) Left-justified(64fs) I2S (32 or 64fs) Left-justified(32 or 64fs) I2S (64fs) Left-justified(64fs) 384fs (≦96kHz) 256fs (>96kHz) 128fs (>96kHz) LRCK BCK M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB 23 SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.6 Left-justified Data Format 64fs, 24bit Data LRCK BCK M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.7 I2S Data Format 64fs, 24bit Data LRCK BCK M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.8 Left-justified Data Format 32fs, 16bit Data LRCK BCK M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig.9 I S Data Format 32fs, 16bit Data 2 - 12 - Ver. 2009.12.4 NJU3610 2.2 High Pass Filter for offset-cancel The NJU3610 provides High Pass Filter (digital filter) to cancel offset. Normally HPF terminal is set “High”. In case of HFP=”High”, High Pass Filter is active. The frequency characteristics are shown in table 8. The cutoff frequency is set at low frequency. But sampling rate changes the cutoff frequency. HFP terminal setting can be changed during NJU3610 operating. But changing HPF setup makes pop noise that is caused by offset change. 2.3 Analog Input and 4-1 Selector The NJU3610 provides four differential-stereo-inputs. SEL0 and SEL1 terminals select one of four stereo-input. After this selector, input signal goes to ADC input. SEL0 and SEL1 combination is shown in table13. Table 13. SEL1, SEL0 combination Lch Rch Non-reversing Reversing Non-reversing Reversing input input input input AINLP1 AINLN1 AINRP1 AINRN1 AINLP2 AINLN2 AINRP2 AINRN2 AINLP3 AINLN3 AINRP3 AINRN3 AINLP4 AINLN4 AINRP4 AINRN4 SEL1 0 0 1 1 SEL0 0 1 0 1 Each differential-signal input should be biased with VCOM reference level. The half of AVDD level is available instead of VCOM reference level. Input full-scale level (0dBFS) is “AVDDx0.7Vpp”. In differential signal, Input full-scale level is “AVDDx1.4Vpp”. Maximum available input range is from GND to AVDD with distortion. But in this case, the distortion occurs. When AMP with high voltage power-supply is used before the ADC, the input level should not exceed the ADC input range. SEL0 and SEL1 settings are taken in at MCK rising edge. In case of RESETb=”Low”, AINLP1, AINLN1, AINRP1 and AINRN1 are selected regardless of SEL0/SEL1 settings. In case that PDNb level is changed from “high” to “Low”, the latest condition is maintained. The terminals that are not selected by SEL0/SEL1 are pull-upped by VCOM bias via 58ohm resisters. The analog input terminals that are not used should be left open or adds the capacitors between terminals and GND. If these terminals connect directly to power-supply or GND, VCOM fluctuates and the NJU3610 does not operate properly. The NJU3610 operates with 32fs over sampling at Mode1=”High”. The NJU3610 operates with 64fs over sampling at Mode1=”Low”. If noise exists around over sampling frequency, the noise folds back. To avoid this folding back noise, passive RC filter is required. The example of input buffer circuit is shown in figure10. VCOM output is used for bias level. The J1 selects RCA or XLR input. The RC-passive-filter is consist of Ra/Rb(220ohm), Ca/Cb(100pF) and Cc(200pF). The cutoff frequency of RC-passive-filter is 1447KHz. This input buffer circuit should be implemented to analog input terminals as far as short distance. The layout pattern should be symmetric. C1 R2 47μ RCA Ra=220 R1 VCOM_OUT BIAS(VDDAx0.5) 10μ AIN*N* BIAS Ca=100p C1 XLR R2 47μ 1 2 3 Cc=200p NJU3610 Cb=100p R1 Rb=220 J1 AIN*P* BIAS Fig.10 Input buffer example Ver.2009.12.4 - 13 - NJU3610 Package dimension LQFP48-R3 (Pb-Free) 9±0.1 7±0.1 0∼10° 36 25 37 24 7±0.1 48 13 1 12 0.6±0.1 1.4±0.05 0.5 0.22±0.1 1.5±0.1 0.17TYP 0 .076 0.1±0.05 9±0.1 モールド底面 Mold Plating: Sn-Bi [CAUTION] The specifications on this data book are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 14 - Ver. 2009.12.4