NJU6539

厂商：
NJRC
封装：
描述：
NJU6539 - 1/8, 1/9, 1/10 DUTY BITMAP LCD DRIVER WITH KEY SCAN - New Japan Radio

数据手册：

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数据手册
价格&库存

NJU6539 数据手册

NJU6539 PRELIMINARY 1/8, 1/9, 1/10 Duty BITMAP LCD DRIVER with KEY SCAN GENERAL DESCRIPTION The NJU6539 is a 10-common x 65-segment bitmap LCD driver to display graphics or characters. It contains 650 bits display data RAM, microprocessor interface circuit, common and segment drivers, key scan circuit, and general output ports. An image data from MPU through the serial interface is stored into the 650 bits internal displayed on the LCD panel through the commons and segments drivers. The NJU6539 displays 10 x 65 dots graphics or 11-character 1-line by 5 x 7 dots character + 3 x 65 dots icons. It contains key scan circuit transmitting the 25-keys maximum (5 x 5 = 25) to MPU. Also it provides 4 general purpose output ports with PWM output function maximum to drive LEDs or others directly. Furthermore, the NJU6539 can select a LCD driving voltage out of 16 steps voltage by the instruction adjust the display contrast of LCD panel. PACKAGE OUTLINE NJU6539FG1 NJU6539FC2 FEATURES Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM : 650-bits LCD Drivers : 65-seg, 10-com Serial interface (SIO, SCL, CS) Programmable Duty Ratio 1/8 Duty, 1/9 Duty, 1/10Duty Bias Ratio 1/4 bias 25-key scan Function (5 x 5 matrix) Needless for anti-reverse current diodes in key scan General Output Ports with 128-steps PWM output (possible LED driving) maximum 4-ports Useful Instruction Set Display ON/OFF, Page Address Set, Column Address Set, ADC Select, Inverse Display ON/OFF, whole display ON/OFF, Reset, EVR Register Set, Duty Select, Power Save mode set, General Output Port set, General Output Port PWM data set, PWM slope set, PWM program Execute, General Output Port / Key scan output select, Display Data write, Bleeder Resistance On-chip Software Contrast Control (16 steps) Operating Voltage Logic Operating Voltage 2.7 to 5.5V LCD Driving Voltage 5.0 to 10.0V Package Outline QFP100-G1 QFP100-C2 C-MOS Technology (Substrate: P) Ver.2004-03-01 -1- NJU6539 -2- PIN CONFIGRATION S1/Po4 S2 S3 S4 S5 K1 K2 K3 K4 K5 VDD VLCD1 VLCD2 V0 V1 V2 VSS OSC RESb CE Po1 Po2 Po3 S1/Po4 S2 S3 S4 S5 K1 K2 K3 K4 K5 VDD VLCD1 VLCD2 V0 V1 V2 VSS OSC RESb CE SCL SIO NJU6539FG1 NJU6539FC2 SCL SIO SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 Po3 Po 2 Po 1 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 Ver.2004-03-01 NJU6539 BLOCK DIAGRAM COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 VLCD1 E.V.R. Common Driver VLCD2 V0 Instruction Decoder V1 V2 VSS Instruction Data Buffer Page Address Decoder Input Buffer Segment Driver Display Data RAM Column Address Decoder OSC Oscillator Timing Generator Key Data Buffer RESb Power ON Reset RESET Serial I/F Key Scan Control General Output Driver S5 S4 S3 S2 Ver.2004-03-01 Po4/S1 SCL SIO Po3 Po2 Po1 CE K1 K2 K3 K4 K5 SEG63 SEG64 SEG65 SEG1 SEG2 SEG3 Reset -3- NJU6539 TERMINAL DESCRIPTION No. FG1 FC2 1 to 65 3 to 67 66 to 72 68 to 74 73 to 75 75 to 77 76 to 78 78 to 80 Symbol SEG1 to SEG65 COM1 to COM7 COM8 to COM10 Po1 to Po3 I/O O O O O Description Segment output terminal. Common output terminal. Icon common output terminal. General output port 128-step PWM waveform output by MPU control. General output port / Key scanning input terminal Select General output port or Key scanning input terminal by the instruction. A function must be selected either Po3 or S0 General output port 128-step PWM waveform output by MPU control. Key scanning input terminals (No need for anti-reverse current diode in key scan) 79 81 Po4/S1 O 80 to 83 84 to 88 89 90 91 92 93 94 95 96 97 98 99 100 82 to 85 86 to 90 91 92 93 94 94 96 97 98 99 100 1 2 S2 to S5 K1 to K5 VDD VLCD1 VLCD2 V0 V1 V2 VSS OSC RESb CE SCL SIO O I I I I/O I I I I/O Key scanning input terminals. (No need for anti-reverse current diode in key scan) Key scanning input terminals. (with internal pull-down resistor) Power supply terminal.(2.7V to 5.5V) LCD driving voltage input terminal. LCD driving voltage stabilization capacitor terminals. Connect the capacitor between each terminal and Vss. Ground terminal. Osclator terminal. Conect the external resistor. Reset terminal. (with internal pull-up resistor) In case of only Power-on Reset should be open. Chip enable terminal Serial clock input terminal Serial Data input or output terminal -4- Ver.2004-03-01 NJU6539 APPLICATION CIRCUIT VDD VSS *1 VDD VSS RESb CE SC SIO COM1 COM10 ---SEG1 ---- 10com 65seg matrix LCD panel MPU *2 VLCD *3 *3 *3 *3 *3 VSS VLCD1 VLCD2 V0 V1 V2 NJU6539 SEG65 General output ports Po1 Po2 Po3 Po4/S1 VSS OSC Po4/S1 S2 S3 S4 S5 5 x5 key matrix *4 K1 K2 K3 K4 K5 *1 *2 *3 *4 The rising time of Power source voltage at Power on and the falling time at Power off must keep over than 1ms because of Voltage detection type Reset circuit operation. SO terminal requires external pull-up resistor connecting to Power source of external MPU because of Open-drain type output. This capacitor for bias voltage stabilization should be connected in accordance with display quality in application. PO3 / S0 terminal is general output ports and Key scan signal output duplicated-function terminals. A function must be selected either Segment output or other. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2004-03-01 -5-

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NJU6539

1. 物料型号： - NJU6539FG1 - NJU6539FC2

2. 器件简介： - NJU6539是一款10共x65段位图LCD驱动器，用于显示图形或字符。它包含650位显示数据RAM、微处理器接口电路、公共和段驱动器、按键扫描电路和通用输出端口。通过串行接口，微处理器单元（MPU）的图像数据存储到内部并显示在LCD面板上。NJU6539能够显示10x65点的图形或11个字符的单行（5x7点字符+3x65点图标）。

3. 引脚分配： - 1至65号引脚：SEGi至SEG65，段输出端。 - 66至72号引脚：COMi至COM7，公共输出端。 - 73至75号引脚：COMs至COM10，图标公共输出端。 - 76至78号引脚：Po1至Po3，通用输出端口，128步PWM波形输出。 - 79号引脚：Po4/S1，通用输出端口/按键扫描输入端。 - 80至83号引脚：S2至S5，按键扫描输入端。 - 84至88号引脚：K1至K5，按键扫描输入端（内置下拉电阻）。 - 89号引脚：VDD，电源供电端（2.7V至5.5V）。 - 90号引脚：VLCD1，LCD驱动电压输入端。 - 91号引脚：VLCD2。 - 92号引脚：Vo，LCD驱动电压稳定电容端。 - 93至96号引脚：V1至V2，连接每个端子和Vss之间的电容。 - 97号引脚：Vss，地端。 - 98号引脚：OSC，振荡器端，连接外部电阻。 - 99号引脚：RESb，复位端（内置上拉电阻）。 - 100号引脚：CE，芯片使能端。 - 101号引脚：SCL，串行时钟输入端。 - 102号引脚：SIO，串行数据输入/输出端。

4. 参数特性： - 显示数据RAM：650位。 - LCD驱动：65段，10共。 - 串行接口：SIO, SCL, CS。 - 可编程占空比：1/8占空比，1/9占空比，1/10占空比。 - 偏置比：1/4偏置。 - 最多25键扫描功能（5x5矩阵）。 - 通用输出端口：128步PWM输出（可能的LED驱动）最多4端口。 - 软件对比度控制：16步。

5. 功能详解： - 显示开/关、页地址设置、列地址设置、ADC选择、反显开/关、全显示开/关、复位、EVR寄存器设置、占空比选择、省电模式设置、通用输出端口设置、通用输出端口PWM数据设置、PWM斜率设置、PWM程序执行、通用输出端口/按键扫描输出选择、显示数据写入、数据写入。

6. 应用信息： - 应用电路图提供了详细的连接方式，包括电源电压上升时间和下降时间需保持超过1ms，SO终端需要外部上拉电阻连接到外部MPU的电源，以及偏置电压稳定的电容器连接。

7. 封装信息： - QFP100-G1 - QFP100-C2

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