NJU6645

Preliminary 16-CHARACTER 6-LINE LCD DRIVER with JAPANESE KANJI ROM ! GENERAL DESCRIPTION The NJU6645 is a 16-character 6-line (16x16dots size Japanese Kanji) or 96 x 256 dots LCD driver with Japanese Kanji ROM. It contains 8-bit parallel or serial interface, instruction decoder, character generator ROM/RAM, common and segment drivers, bleeder resistor and voltage booster. The NJU6645 supports the character font of JIS level-1 and level-2, non-kanji and half-size character and symbol. It is suitable for the low operation voltage and low power applications by low operating voltage 2.4 to 3.6V. NJU6645 ! PACKAGE OUTLINE NJU6645CJ ! FEATURES ! ! ! ! ! ! 16-character 6-line Kanji Character Display or 96 x 256 dots Graphic Display LCD controller driver LCD Driver Output : 96-common x 256-segment + 2-icon com 8-bit Parallel Interface Serial Interface Display Data RAM 1,536 bits at Full-size 96 Characters Character Generator ROM :JIS Level-1 Kanji 16 x 16 dots 2,965 fonts :JIS Level-2 Kanji 16 x 16 dots 3,388 fonts :JIS Non-Kanji 16 x 16 dots 524 fonts :Half Size Display 8 x 16 dots 256 fonts Character Generator RAM 24,576 bits 8 x 16 dots 192 fonts Icon Display RAM 512 bits Maximum 512 icons Duty Ratio 1/18, 1/34, 1/50, 1/66, 1/82, 1/98 (Programmable) Bias Ratio 1/4 ~ 1/11 (Programmable) Common and Segment driver Location order Select Function (Programmable) Common Wiring Select Function Useful Instruction Set RE Flag Set, Status Read, Display Clear, Cursor Home, Display Control, Stand-by, Cursor Control, Display / Entry Mode, Scroll Start Line, Scroll Start Row, Display Start Line, Display Duty Ratio, N-line inversion, Driver Output Control, Oscillation Control, Discharge, Boost Level, Bias Ratio, Electrical Volume, Power Control, RAM Address Set, Address Shift, RAM Data Writing / Reading Built-in Voltage Boost 2 to 6-time Built-in Electrical Volume 128-step Oscillation Circuit External Resistor Required Built-in Bleeder Resistor Operating Voltage +2.4 to 3.6V LCD Driving Voltage +4.5 to 17.0V Operation Temperature Range -40 to +85°C C-MOS Technology (P-sub ) Package Outline Bump Chip ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Ver.2009-05-20 -1- NJU6645 ! PAD ALIGNMENT Preliminary 315:DUMMY90 314:DUMMY89 313:DUMMY88 263:DUMMY87 262:DUMMY86 261:DUMMY85 312:COMMK1 265:COM49 264:COM48 311:COM95 ALI_B1 316:DUMMY91 317:DUMMY92 318:DUMMY93 319:SEG255 320:SEG254 ALI_A2 260:DUMMY84 259:DUMMY83 258:DUMMY82 257:C5256:C5- X Y TOP VIEW NJU6645 573:SEG1 574:SEG0 575:DUMMY94 576:DUMMY95 577:DUMMY96 ALI_B2 5:DUMMY4 4:TESTOUT 3:DUMMY3 2:DUMMY2 1:DUMMY1 ALI_A1 630:DUMMY100 631:DUMMY101 Chip Size Chip Thickness Bump Size Bump Material : 14.16mm x 3.16mm (T.B.D.) : 625µm±25µm : 31µm x 130µm : Au Chip Center Pad Pitch Bump Height : X=0µm, Y=0µm : 50µm pitch : 17.5µm(Typ.) 632:DUMMY102 578:DUMMY97 579:DUMMY98 580:DUMMY99 629:COMMK0 581:COM47 582:COM46 628:COM0 -2- Ver.2009-05-20 Preliminary Alignment Mark - Type A NJU6645 70µm - Type B 7 0 µm Center Coordinates : ALI_A1 (X, Y) = (-6682, -1447) : ALI_A2 (X, Y) = (6682, -1447) Center Coordinates : ALI_B1 (X, Y) = (6710, 1427) : ALI_B2 (X, Y) = (-6710, 1427) 70µm Ver.2009-05-20 110µm -3- NJU6645 Preliminary Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DUMMY27 D3 D3 DUMMY28 DUMMY29 D4 D4 DUMMY30 DUMMY31 D5 D5 DUMMY32 DUMMY33 D6/SCL D6/SCL DUMMY34 DUMMY35 D7/SDA D7/SDA DUMMY36 OSC2 OSC2 DUMMY37 VDD VDD VDD VDD VDD VDD DUMMY38 OSC1 OSC1 DUMMY39 VSS VSS VSS VSS VSS VSS DUMMY40 DUMMY41 VLCD VLCD VLCD VLCD VLCD VLCD DUMMY42 DUMMY43 V1 -3975 -3925 -3875 -3825 -3775 -3725 -3675 -3625 -3575 -3525 -3475 -3425 -3375 -3325 -3275 -3225 -3175 -3125 -3075 -3025 -2975 -2925 -2875 -2825 -2775 -2725 -2675 -2625 -2575 -2525 -2475 -2425 -2375 -2325 -2275 -2225 -2175 -2125 -2075 -2025 -1975 -1925 -1875 -1825 -1775 -1725 -1675 -1625 -1575 -1525 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 ! PAD COORDINATES 1 PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PAD name DUMMY1 DUMMY2 DUMMY3 TESTOUT DUMMY4 DUMMY5 SEL68 DUMMY6 VPUP DUMMY7 PS DUMMY8 VPUP DUMMY9 CSEL DUMMY10 DUMMY11 RSTb RSTb DUMMY12 DUMMY13 CSb CSb DUMMY14 DUMMY15 RS RS DUMMY16 VPDN DUMMY17 WRb/RW WRb/RW DUMMY18 DUMMY19 RDb/E RDb/E DUMMY20 VPUP DUMMY21 D0 D0 DUMMY22 DUMMY23 D1 D1 DUMMY24 DUMMY25 D2 D2 DUMMY26 X= µm -6475 -6425 -6375 -6325 -6275 -6225 -6175 -6125 -6075 -6025 -5975 -5925 -5875 -5825 -5775 -5725 -5675 -5625 -5575 -5525 -5475 -5425 -5375 -5325 -5275 -5225 -5175 -5125 -5075 -5025 -4975 -4925 -4875 -4825 -4775 -4725 -4675 -4625 -4575 -4525 -4475 -4425 -4375 -4325 -4275 -4225 -4175 -4125 -4075 -4025 -4- Ver.2009-05-20 Preliminary ! PAD COORDINATES 2 NJU6645 PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PAD name V1 V1 V1 V1 DUMMY44 DUMMY45 V2 V2 V2 V2 V2 DUMMY46 DUMMY47 V3 V3 V3 V3 V3 DUMMY48 DUMMY49 V4 V4 V4 V4 V4 DUMMY50 DUMMY51 VREG VREG VREG VREG VREG DUMMY52 DUMMY53 VREF VREF VREF VREF DUMMY54 DUMMY55 VBA VBA VBA VBA DUMMY56 DUMMY57 VSS VSS VSS VSS X= µm -1475 -1425 -1375 -1325 -1275 -1225 -1175 -1125 -1075 -1025 -975 -925 -875 -825 -775 -725 -675 -625 -575 -525 -475 -425 -375 -325 -275 -225 -175 -125 -75 -25 25 75 125 175 225 275 325 375 425 475 525 575 625 675 725 775 825 875 925 975 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 VSS VSS DUMMY58 DUMMY59 VOUT VOUT VOUT VOUT VOUT VOUT DUMMY103 DUMMY104 VDCOUT VDCOUT VDCOUT VDCOUT VDCOUT VDCOUT VDCOUT DUMMY60 DUMMY61 VEE VEE VEE VEE VEE VEE DUMMY62 DUMMY63 C1+ C1+ C1+ C1+ C1+ C1+ DUMMY64 DUMMY65 C1C1C1C1C1C1DUMMY66 DUMMY67 C2+ C2+ C2+ C2+ C2+ 1025 1075 1125 1175 1225 1275 1325 1375 1425 1475 1525 1575 1625 1675 1725 1775 1825 1875 1925 1975 2025 2075 2125 2175 2225 2275 2325 2375 2425 2475 2525 2575 2625 2675 2725 2775 2825 2875 2925 2975 3025 3075 3125 3175 3225 3275 3325 3375 3425 3475 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 Ver.2009-05-20 -5- NJU6645 Preliminary Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 DUMMY81 C5C5C5C5C5C5DUMMY82 DUMMY83 DUMMY84 DUMMY85 DUMMY86 DUMMY87 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 6025 6075 6125 6175 6225 6275 6325 6375 6425 6475 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1412.5 -1352 -1302 -1252 -1202 -1152 -1102 -1052 -1002 -952 -902 -852 -802 -752 -702 -652 -602 -552 -502 -452 -402 -352 -302 -252 -202 -152 -102 -52 -2 48 98 148 198 248 298 348 398 448 498 548 598 ! PAD COORDINATES 3 PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 PAD name C2+ DUMMY68 DUMMY69 C2C2C2C2C2C2DUMMY70 DUMMY71 C3+ C3+ C3+ C3+ C3+ C3+ DUMMY72 DUMMY73 C3C3C3C3C3C3DUMMY74 DUMMY75 C4+ C4+ C4+ C4+ C4+ C4+ DUMMY76 DUMMY77 C4C4C4C4C4C4DUMMY78 DUMMY79 C5+ C5+ C5+ C5+ C5+ C5+ DUMMY80 X= µm 3525 3575 3625 3675 3725 3775 3825 3875 3925 3975 4025 4075 4125 4175 4225 4275 4325 4375 4425 4475 4525 4575 4625 4675 4725 4775 4825 4875 4925 4975 5025 5075 5125 5175 5225 5275 5325 5375 5425 5475 5525 5575 5625 5675 5725 5775 5825 5875 5925 5975 -6- Ver.2009-05-20 Preliminary ! PAD COORDINATES 4 NJU6645 PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 PAD name COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COMMK1 DUMMY88 DUMMY89 DUMMY90 DUMMY91 DUMMY92 DUMMY93 SEG255 SEG254 SEG253 SEG252 SEG251 SEG250 SEG249 SEG248 SEG247 SEG246 SEG245 SEG244 SEG243 SEG242 SEG241 SEG240 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 SEG231 SEG230 SEG229 SEG228 SEG227 SEG226 SEG225 SEG224 X= µm 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6918.5 6525 6475 6425 6375 6325 6275 6225 6175 6125 6075 6025 5975 5925 5875 5825 5775 5725 5675 5625 5575 5525 5475 5425 5375 5325 5275 5225 5175 5125 5075 5025 4975 4925 4875 4825 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 648 698 748 798 848 898 948 998 1048 1098 1148 1198 1248 1298 1348 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 SEG199 SEG198 SEG197 SEG196 SEG195 SEG194 SEG193 SEG192 SEG191 SEG190 SEG189 SEG188 SEG187 SEG186 SEG185 SEG184 SEG183 SEG182 SEG181 SEG180 SEG179 SEG178 SEG177 SEG176 SEG175 SEG174 4775 4725 4675 4625 4575 4525 4475 4425 4375 4325 4275 4225 4175 4125 4075 4025 3975 3925 3875 3825 3775 3725 3675 3625 3575 3525 3475 3425 3375 3325 3275 3225 3175 3125 3075 3025 2975 2925 2875 2825 2775 2725 2675 2625 2575 2525 2475 2425 2375 2325 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 Ver.2009-05-20 -7- NJU6645 Preliminary Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 -225 -275 -325 -375 -425 -475 -525 -575 -625 -675 -725 -775 -825 -875 -925 -975 -1025 -1075 -1125 -1175 -1225 -1275 -1325 -1375 -1425 -1475 -1525 -1575 -1625 -1675 -1725 -1775 -1825 -1875 -1925 -1975 -2025 -2075 -2125 -2175 -2225 -2275 -2325 -2375 -2425 -2475 -2525 -2575 -2625 -2675 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 ! PAD COORDINATES 5 PAD No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 PAD name SEG173 SEG172 SEG171 SEG170 SEG169 SEG168 SEG167 SEG166 SEG165 SEG164 SEG163 SEG162 SEG161 SEG160 SEG159 SEG158 SEG157 SEG156 SEG155 SEG154 SEG153 SEG152 SEG151 SEG150 SEG149 SEG148 SEG147 SEG146 SEG145 SEG144 SEG143 SEG142 SEG141 SEG140 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 X= µm 2275 2225 2175 2125 2075 2025 1975 1925 1875 1825 1775 1725 1675 1625 1575 1525 1475 1425 1375 1325 1275 1225 1175 1125 1075 1025 975 925 875 825 775 725 675 625 575 525 475 425 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -8- Ver.2009-05-20 Preliminary ! PAD COORDINATES 6 NJU6645 PAD No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 PAD name SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 X= µm -2725 -2775 -2825 -2875 -2925 -2975 -3025 -3075 -3125 -3175 -3225 -3275 -3325 -3375 -3425 -3475 -3525 -3575 -3625 -3675 -3725 -3775 -3825 -3875 -3925 -3975 -4025 -4075 -4125 -4175 -4225 -4275 -4325 -4375 -4425 -4475 -4525 -4575 -4625 -4675 -4725 -4775 -4825 -4875 -4925 -4975 -5025 -5075 -5125 -5175 Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 DUMMY94 DUMMY95 DUMMY96 DUMMY97 DUMMY98 DUMMY99 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 -5225 -5275 -5325 -5375 -5425 -5475 -5525 -5575 -5625 -5675 -5725 -5775 -5825 -5875 -5925 -5975 -6025 -6075 -6125 -6175 -6225 -6275 -6325 -6375 -6425 -6475 -6525 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1412.5 1348 1298 1248 1198 1148 1098 1048 998 948 898 848 798 748 698 648 598 548 498 448 398 348 298 248 Ver.2009-05-20 -9- NJU6645 Preliminary Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm) Y= µm PAD No. PAD name X= µm Y= µm 198 148 98 48 -2 -52 -102 -152 -202 -252 -302 -352 -402 -452 -502 -552 -602 -652 -702 -752 -802 -852 -902 -952 -1002 -1052 -1102 -1152 -1202 -1252 -1302 -1352 ! PAD COORDINATES 7 PAD No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 PAD name COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMMK0 DUMMY100 DUMMY101 DUMMY102 X= µm -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 -6918.5 - 10 - Ver.2009-05-20 Preliminary ! LCD DISPLAY EXAMPLE - Mix display (Full-size / Half-size / Graphics) NJU6645 Ver.2009-05-20 - 11 - NJU6645 ! BLOCK DIAGRAM PS SEL68 CSb RS WRb/RW RDb/E D7/SDA D6/SCL D5~D0 CSEL TESTOUT Preliminary Address Counter Instruction Decoder Instruction Register Display Counter N-line Inversion Full/Half/ODD/EVEN Discrimination Circuit Data Register RSTb OSC1 OSC2 VDD VSS VPUP VPDN VBA VOUT VREG VREF Reset Circuit Oscillator Circuit Timing Generator Character Generator ROM (Full-size FCGROM) 2M-bit (Half-size HCGROM) 32k-bit Segment Driver Data Register Character Generator RAM(CGRAM) 24,576-bit Icon Display RAM (MKRAM) 512-bit Common Driver Display Data RAM(DD RAM) 1,536-bit Graphics Counter 98-bit Shift Register COM0~ COM95, COMM0, COMM1 Interface SEG0~ SEG255 Attribute, Cursor, Inversion Reference Voltage + Gain Control + - + + - VLCD V1 V2 V3 V4 E.V.R. + + + - C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VEE VDCOUT Boost Level Register Voltage Booster E.V.R. Register - 12 - Ver.2009-05-20 256-bit Shift Register Preliminary ! TERMINAL DESCRIPTION No. 74 to 79 84 to 89, 147 to 152 141 to 144 135 to 138 128 to 132 172 to 177 155 to 160 163 to 169 92 to 97 100 to 104 107 to 111 114 to 118 121 to 125 SYMBOL VDD VSS VBA VREF VREG VEE VOUT VDCOUT VLCD V1 V2 V3 V4 I/O Power Power Output Input Output Power Power Output NJU6645 Power/ Output 9,13,38 VPUP Power/ Output Power/ Output 29 180 to 185 188 to 193 196 to 201 204 to 209 212 to 217 220 to 225 228 to 233 236 to 241 244 to 249 252 to 257 81,82 71,72 18,19 15 VPDN C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5OSC1 OSC2 RSTb CSEL FUNCTION Power Supply (Logic, I/F) VDD=2.4 to 3.6V GND (Logic, I/F, High voltage) VSS=0V Reference-Voltage Generator Output Voltage Regulator Input Voltage Regulator Output Voltage Booster Input VEE is normally connected to VDD. High Voltage Power Supply Input (External supply) Input of LCD power supply circuit. Voltage Booster Output Output of voltage booster circuit. LCD Bias Voltages When the internal LCD power supply is used, internal LCD bias voltages (VLCD and V1~V4) are activated by the “Power Control” instruction. Stabilizing capacitors are required between each bias voltage and VSS. When the external LCD power supply is used, LCD bias voltages are externally supplied on VLCD, V1, V2, V3 and V4 individually, with the following relation maintained : VSS (a) RAM Data Write The "RAM Data Write" instruction writes display data on a specified address. The address is incremented automatically by "Display / Entry Mode” instruction. RE * RS 1 RW 0 D7 D6 D5 D4 D3 WRITE DATA D2 D1 D0 (b) RAM Data Read The "RAM Data Read" instruction reads out display data from a specified address. The address is incremented automatically by "Display / Entry Mode” instruction. RE * RS 1 RW 1 D7 D6 D5 D4 D3 READ DATA D2 D1 D0 - 78 - Ver.2009-05-20 Preliminary (c) Status Read NJU6645 The "Status Read" instruction reads out the busy flag (BF) that indicates the internal operation and the line / row that displayed at present. The BF="1" indicates that internal operation is in progress. When the BF="1", the next instruction is disabled. Check the busy flag status (BF="0") before the next write operation. RE * RS 0 RW 1 D7 BF D6 NF2 D5 NF1 D4 NF0 D3 LF3 D2 LF2 D1 LF1 D0 LF0 - Busy Flag Read BF 0 1 - Display Line Read NF 000 001 010 011 100 101 110 111 - Display Row Read LF 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Internal Operation Instruction is enable Operating (Instruction is disabled) Display Line 1st line 2nd line 3rd line 4th lint 5th line 6th line - Display Row 1st row 2nd row 3rd row 4th row 5th row 6th row 7th row 8th row 9th row 10th row 11th row 12th row 13th row 14th row 15th row 16th row Ver.2009-05-20 - 79 - NJU6645 (d) Display Clear Preliminary When the "Display Clear" instruction is executed, the Half-size space code "0020h" is written into every DD RAM address, the DD RAM address "000h" is set into the address counter. The MK RAM / CG RAM data is unchanged. RE 0 (e) Cursor Home When the "Cursor Home" instruction is executed, the DD RAM address "000h" is set into the address counter. The Scroll Start Line and the Scroll Start Row are set to default. The DD RAM contents are unchanged. RE 0 (f) Display Control The "Display Control" instruction controls the Dot Matrix Display ON/OFF, the Icon Display ON/OFF, the Full Screen Reverse Display ON/OFF and All Pixels ON/OFF. The Icon Display ON/OFF and the Dot Matrix Display ON/OFF are controlled separately. When the M=”0” and D=”0”, common / segment drivers are turning OFF and output VSS level. RE 0 RS 0 RW 0 D7 0 D6 0 D5 1 D4 0 D3 D2 ALLON REV D1 M D0 D RS 0 RW 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 RS 0 RW 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 - All Pixels ON/OFF ALLON 0 1 Display Normal display All ON display (Both dot matrix and Icon display) - Full Screen Reverse Display ON/OFF REV Display 0 Normal display 1 Full screen reverse display - Icon Display ON/OFF M 0 1 - Dot Matrix Display ON/OFF D 0 1 Icon Display OFF ON Dot Matrix Display OFF ON - 80 - Ver.2009-05-20 Preliminary (g) Standby The "Standby" instruction controls the Standby mode ON/OFF. RE 0 RS 0 RW 0 D7 0 D6 0 D5 1 D4 1 D3 * D2 * NJU6645 D1 * D0 HALT HALT 0 1 Function OFF (Normal mode) ON (Standby mode) During the standby ON, operating current is down to the standby level. The internal state of the LSI in the standby mode is listed below. - Internal oscillator and internal LCD power supply are halted. - All segment and common drivers are fixed at VSS level. - External clock to the OSC2 cannot be accepted. - Voltage booster is halted. - Display data in the DDRAM and data in the instruction registers are being maintained. - VLCD, V1, V2, V3 and V4 are in high impedance. In the standby ON sequence, execute the "Display OFF" prior to the "Standby ON". In the standby OFF sequence, execute the "Standby OFF" prior to the "Display ON". If the "Standby ON/OFF" instruction is executed during the "Display ON", unexpected pixels may be turned on instantly. (h) Cursor Display The "Cursor Display" instruction controls the Cursor ON/OFF, the Line Cursor ON/OFF and display method. RE 0 BW * 0 0 1 1 0 0 1 1 RS 0 B * 0 1 0 1 0 1 0 1 RW 0 D7 0 LC * 0 0 0 0 1 1 1 1 D6 1 C 0 1 1 1 1 1 1 1 1 D5 0 D4 0 D3 BW D2 B D1 LC D0 C Display State Cursor OFF Underline cursor (Character unit) Black blink cursor (Character unit) Reverse blink cursor (Character unit) Inhibited Underline cursor (Line unit) White blink cursor (Line unit) Reverse cursor (Line unit) Inhibited Ver.2009-05-20 - 81 - NJU6645 (i) Preliminary Display Mode / Entry Mode The "Display Mode / Entry Mode" instruction controls the Display Mode and Entry Mode. RE 0 - Display Mode SPR 0 0 1 RS 0 RW 0 D7 0 D6 1 D5 0 D4 1 D3 * D2 SPR D1 GR D0 RDM GR 0 1 * Display state Character Mode Graphics Mode Superimpose Mode - Read Modify Write Mode RDM 0 1 (j) Scroll Start Line Function OFF (Auto increment in writing and reading display data) ON (Auto increment in writing display data only) The "Scroll Start Line" instruction controls the Display Line from COM0 output. RE 0 SSN2 0 0 0 0 1 1 1 RS 0 RW 0 SSN1 0 0 1 1 0 0 1 D7 0 SSN0 0 1 0 1 0 1 * D6 1 D5 1 D4 0 D3 * D2 SSN2 D1 SSN1 D0 SSN0 Scroll Start Line 1st line 2nd line 3rd line 4th line 5th line 6th line Inhibited - 82 - Ver.2009-05-20 Preliminary - Example of Display NJU6645 SSN=”000” (Default) 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 1 2 3 4 5 6 2 3 4 5 6 1 SSN=”001” SSN=”010” 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 SSN=”011” SSN=”100” SSN=”101” Ver.2009-05-20 - 83 - NJU6645 (k) Scroll Start Row Preliminary The "Scroll Start Row" instruction controls number of the Scroll Start Row. RE 0 SSL3 0 0 0 0 RS 0 RW 0 SSL2 0 0 0 0 : : 1 - Example of Display 1 1 1 D7 0 SSL1 0 0 1 1 D6 1 SSL0 0 1 0 1 D5 1 D4 1 D3 SSL3 D2 SSL2 D1 SSL1 D0 SSL0 Scroll Start Row 1st row 2nd row 3rd row 4th row : : 16th row SSL3 to 0=0 SSL3 to 0=1 SSL3 to 0=2 --- SSL3 to 0=14 SSL3 to 0=15 --- (Under Character) (l) Display Start Line The "Display Start Line" instruction controls the Display Start Line. The displayed data of the 1st line shifts to the setting line. RE 0 DST2 0 0 0 0 1 1 1 RS 0 RW 0 DST1 0 0 1 1 0 0 1 D7 1 DST0 0 1 0 1 0 1 * D6 0 D5 0 D4 0 D3 * D2 DST2 D1 DST1 D0 DST0 Display Start Line 1st line 2nd line 3rd line 4th line 5th line 6th line Inhibited - 84 - Ver.2009-05-20 Preliminary - Example of Display NJU6645 DST=”000” (Default) 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 1 2 3 4 5 6 6 1 2 3 4 5 5 6 1 2 3 4 4 5 6 1 2 3 3 4 5 6 1 2 2 3 4 5 6 1 - 85 - DST=”001” DST=”010” DST=”011” DST=”100” DST=”101” Ver.2009-05-20 NJU6645 (m) Display Duty Ratio Preliminary The "Display Duty Ratio" instruction controls the number of display line, and is used to carry out the partial display. RE 0 DN2 0 0 0 0 1 1 1 (n) N-line Inversion The "N-line Inversion" instruction controls the number of inversion line. The setting range are 2 to 98 lines, and is alternated by setting (N+1). RE 0 RE 0 NL6 0 0 0 0 RS 0 RS 0 RW 0 RW 0 NL5 0 0 0 0 D7 1 D7 1 NL4 0 0 0 0 D6 0 D6 0 NL3 0 0 0 0 : 1 1 1 1 0 0 0 0 : 1 1 1 1 1 1 1 0 0 0 0 0 1 D5 1 D5 1 NL2 0 0 0 0 D4 0 D4 1 NL1 0 0 1 1 D3 * D3 NL3 NL0 0 1 0 1 D2 NL6 D2 NL2 D1 NL5 D1 NL1 D0 NL4 D0 NL0 RS 0 RW 0 DN1 0 0 1 1 0 0 1 D7 1 DN0 0 1 0 1 0 1 * D6 0 D5 0 D4 1 D3 * D2 DN2 D1 DN1 D0 DN0 Display Line (Duty) 6-line (1/98 Duty) 5-line (1/82 Duty) 4-line (1/66 Duty) 3-line (1/50 Duty) 2-line (1/34 Duty) 1-line (1/18 Duty) Inhibited Inversion Line Inhibited 2 3 4 : 97 98 Inhibited - 86 - Ver.2009-05-20 Preliminary (o) Driver Output Control The "Driver Output Control" instruction controls the SEG / COM driver output direction. RE 0 SEL1 0 1 SEL2 0 1 (p) Oscillation Control RS 0 RW 0 D7 1 D6 1 D5 0 D4 0 D3 * D2 * NJU6645 D1 SEL1 D0 SEL2 Function COM scan forward direction COM scan backward direction Function SEG output forward direction SEG output backward direction The "Oscillation Control" instruction controls the system clock type and the internal capacitance of internal oscillation circuits. The frame frequency is adjusted by internal capacitance setting. When the frame frequency is set by this instruction, make sure what is the best setting in the particular application. RE 0 RS 0 RW 0 D7 1 D6 1 D5 0 D4 1 D3 INTCK D2 OC2 D1 OC1 D0 OC0 INTCK 0 1 OC2 0 0 0 0 1 1 1 1 (q) RE Flag Set OC1 0 0 1 1 0 0 1 1 OC0 0 1 0 1 0 1 0 1 Function Internal oscillation circuit External oscillation input Internal Capacitance Reference capacitance 0.7 x Reference capacitance 0.8 x Reference capacitance 0.9 x Reference capacitance 1.1 x Reference capacitance 1.2 x Reference capacitance 1.3 x Reference capacitance Inhibited The "RE Flag Set" instruction controls the access to the expanded register. When it accesses each instruction, it is necessary to set the RE flag in advance. RE * RS 0 RW 0 D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 RE Ver.2009-05-20 - 87 - NJU6645 (r) Discharge Preliminary Discharge circuit is used to discharge out of the stabilizing capacitors placed on the VLCD, V1, V2, V3, V4 and VSS. This instruction prevents the unknown display at the power supply off. RE 1 DIS 0 1 (s) Boost Level The "Boost Level" instruction controls the level of Voltage Boost Circuit.. RE 1 VU2 0 0 0 0 1 1 1 1 (t) Bias Ratio The "Bias Ratio" instruction controls the Bias Ratio. RE 1 BS3 0 0 0 0 0 0 0 0 1 1 1 1 RS 0 RW 0 BS2 0 0 0 0 1 1 1 1 0 0 0 : 1 1 1 D7 0 BS1 0 0 1 1 0 0 1 1 0 0 1 D6 0 BS0 0 1 0 1 0 1 0 1 0 1 0 D5 1 D4 0 D3 BS3 Bias Ratio 1/11 1/10 1/9 1/8 1/7 1/6 1/5.5 1/5 1/4.5 1/4 Inhibited D2 BS2 D1 BS1 D0 BS0 RS 0 RW 0 VU1 0 0 1 1 0 0 1 1 D7 0 VU0 0 1 0 1 0 1 0 1 D6 0 D5 0 D4 1 D3 * D2 VU2 D1 VU1 D0 VU0 RS 0 RW 0 D7 0 D6 0 D5 0 D4 0 D3 * D2 * D1 * D0 DIS Function Discharge OFF Discharge ON Boost Level 1 time (No boost) 2 times 3 times 4 times 5 times 6 times Inhibited - 88 - Ver.2009-05-20 Preliminary (u) Electrical Volume NJU6645 The "Electrical Volume" instruction adjusts VLCD to optimize display contrast. The voltage divided into 127 is set. The setting order requires upper byte first. RE 1 RE 1 EV6 0 0 RS 0 RS 0 RW 0 RW 0 EV5 0 0 D7 0 D7 0 EV4 0 0 D6 0 D6 1 EV3 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 0 1 D5 1 D5 0 EV2 0 0 D4 1 D4 0 EV1 0 0 D3 * D3 EV3 EV0 0 1 D2 EV6 D2 EV2 D1 EV5 D1 EV1 D0 EV4 D0 EV0 Output Voltage Low : : High This instruction is finally effective when both upper and lower bytes are transmitted in order to prevent high VLCD. The setting order is upper byte first, then lower byte. Note) When the electrical volume setting is changed to wide range at keeping display on, there is possibility that the unknown display appears. In this case, add waiting time and change the electrical volume value gradually. < Example of the changing from EV=80 to EV=110 at keeping display on > EV=80 → Wait (~ms) → EV=90 → Wait (~ms) → EV=100 → Wait (~ms) → EV=110 * The wait time and electrical volume setting range is different depending on the capacitance value of V1 to V4 and the panel size. Please make sure what is the best setting in the particular application. (v) Power Control RE 1 RS 0 RW 0 D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 D0 AMPON DCON AMPON : This instruction controls ON/OFF of the operational amplifier parts of the internal power supply circuits (Voltage regulator, electrical variable resistor, and voltage converter). AMPON 0 1 DCON Function Internal operational amplifier OFF Internal operational amplifier ON : This instruction controls Internal Voltage Booster ON/OFF, DCON 0 1 Function Voltage booster OFF Voltage booster ON Ver.2009-05-20 - 89 - NJU6645 (w) RAM Address Set Preliminary The "RAM Address Set" instruction specifies the DDRAM, CGRAM, and MKRAM address. The RAM address should set lower 4-bit (AD3 to AD0) at first. This instruction is finally effective when upper 4-bit (AD11 to AD8) are transmitted. RE 1 RE 1 RE 1 (x) Address Shift The "Address Shift" instruction controls increment (+1) or decrement (-1) of the address. The address moves whenever this instruction is executed. RE 1 ARL 0 1 (y) Maker Test This instruction is using for device testing mode. Please do not use this instruction usually. RE 1 RS 0 RW 0 D7 1 D6 0 D5 1 D4 0 D3 * D2 * D1 * D0 * RS 0 RW 0 D7 1 D6 0 D5 0 D4 1 D3 * D2 * D1 * D0 ARL RS 0 RS 0 RS 0 RW 0 RW 0 RW 0 D7 0 D7 0 D7 1 D6 1 D6 1 D6 0 D5 1 D5 1 D5 0 D4 0 D4 1 D4 0 D3 AD3 D3 AD7 D3 AD11 D2 AD2 D2 AD6 D2 AD10 D1 AD1 D1 AD5 D1 AD9 D0 AD0 D0 AD4 D0 AD8 Function Address –1 Address +1 RE 1 RS 0 RW 0 D7 1 D6 1 D5 1 D4 0 D3 * D2 * D1 * D0 * - 90 - Ver.2009-05-20 Preliminary (21) TYPICAL INSTRUCTION SEQUENCE (21-1) Initialization Sequence in Using Internal LCD Power Supply Power ON (VDD, VEE) WAIT(*2) Reset (RSTb terminal) WAIT(*3) Refer to (15)RESET FUNCTION -------------------- Instruction Code ------------------D7 0 1 0 0 0 0 0 D6 0 1 0 0 0 1 1 D5 0 1 0 1 1 0 0 D4 0 1 1 0 1 0 1 D3 0 * * 0 * 0 * D2 0 * 1 0 1 0 * D1 0 * 0 0 0 0 0 D0 1 1 1 0 0 0 1 (*1) NJU6645 ----- Setting Example ----- Display Clear RE Flag Boost Level Bias Ratio Electrical Volume (Upper) Electrical Volume (Lower) Power Control WAIT(*4) Power Control WAIT(*5) End *1 *2 *3 *4 *5 Display clear RE=”1” 6 times boost 1/11 bias EV=“1,0,0,0,0,0,0” Voltage booster ”ON” 0 1 0 1 * * 1 1 Internal operational amplifier ”ON” If different power sources are applied to the VDD and the VEE, turn ON the VDD first. Wait until the VDD and VEE are stabilized. Wait 1.5ms or more. Wait until the VDCOUT (VOUT) is stabilized. Wait until the VLCD and V1 to V4 are stabilized. Ver.2009-05-20 - 91 - NJU6645 Preliminary (21-2) Initialization Sequence in Using External LCD Power Supply Power ON (VDD) WAIT(*1) Reset (RSTb terminal) WAIT(*2) External Power Supply ON WAIT(*3) -------------------- Instruction Code ------------------D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 ----- Setting Example ----Refer to (15)RESET FUNCTION Display Clear End *1 *2 *3 Display clear Wait until the VDD is stabilized. Wait 1.5ms or more. Wait until the external LCD power supply (VOUT, VLCD, V1 to V4) are stabilized. - 92 - Ver.2009-05-20 Preliminary (21-3) Display Data Write Sequence Operational Status -------------------- Instruction Code ------------------D7 1 0 0 1 * * D6 1 1 1 0 * * D5 1 1 1 0 * * D4 1 0 1 0 * * D3 * 0 0 0 * * D2 * 0 0 0 * * D1 * 0 0 0 * * D0 1 0 0 0 * * NJU6645 ----- Setting Example ----- RE Flag RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RE=”1” 1st line DDRAM address Set (000h) 1st line writing DDRAM data Repeating 2nd to 5th line RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RE Flag Display Control 0 0 1 * * 0 0 1 * * 0 0 1 * * 1 0 1 1 0 * * 1 1 0 * * 1 1 0 * * 1 0 1 1 0 * * 1 1 0 * * 1 1 0 * * 1 1 0 1 0 * * 0 1 0 * * 0 1 0 * * 1 0 0 1 0 * * 0 0 0 * * 0 0 0 * * * 0 0 0 0 * * 0 0 0 * * 0 0 0 * * * 0 0 1 0 * * 0 0 0 * * 0 0 1 * * * 1 0 0 0 * * 0 0 1 * * 0 0 0 * * 0 1 6th line DDRAM address set (0A0h) 6th line DDRAM data writing MKRAM address set (100h) MKRAM data writing CGRAM address set (200h) CGRAM Data Writing RE=”0” Dot matrix display “ON” Icon display ”ON” Data Display Ver.2009-05-20 - 93 - NJU6645 Preliminary (21-4) Power OFF Sequence in Using Internal LCD Power Supply Operational Status -------------------- Instruction Code ------------------D7 1 0 0 1 0 D6 1 0 0 1 0 D5 1 1 1 1 0 D4 1 0 1 1 0 D3 * 0 * * * D2 * 0 * * * D1 * 0 * * * D0 0 0 1 1 1 ----- Setting Example ----- RE Flag Display Control Standby RE Flag Discharge WAIT(*1) Power OFF (VEE) Power OFF (VDD) *1 RE=”0” Display ”OFF" Standby ”ON” RE=”1” Discharge ”ON” Wait until the discharge is completed. (21-5) Power OFF Sequence in Using External LCD Power Supply Operational Status -------------------- Instruction Code ------------------D7 1 0 0 D6 1 0 0 D5 1 1 1 D4 1 0 1 D3 * 0 * D2 * 0 * D1 * 0 * D0 0 0 1 ----- Setting Example ----- RE Flag Display Control Standby External Power OFF RE Flag Discharge WAIT(*1) Power OFF (VEE) Power OFF (VDD) *1 RE=”0” Display ”OFF" Standby ”ON” 1 0 1 0 1 0 1 0 * * * * * * 1 1 RE=”1” Discharge ”ON” Wait until the discharge is completed. - 94 - Ver.2009-05-20 Preliminary NJU6645 (21-6) Partial Display Sequence [Example : Display Duty Ratio = 2-line (1/34 Duty), Display Start Line = 3rd line] Operational Status -------------------- Instruction Code ------------------D7 1 0 1 0 D6 1 0 1 1 D5 1 1 1 0 D4 1 0 1 1 D3 * 0 * * D2 * 0 * * D1 * 0 * 0 D0 0 0 1 0 ----- Setting Example ----- RE Flag Display Control RE Flag Power Control WAIT(*1) Boost Level Bias Ratio Electrical Volume (Upper) Electrical Volume (Lower) Power Control WAIT(*2) Power Control WAIT(*3) RE Flag Display Start line Display Duty Ratio RE=”0” Display ”OFF" RE=”1” Voltage booster ”OFF” Internal operational amplifier ”OFF” 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 * 0 * 0 * 0 1 1 0 * 1 0 0 0 0 0 1 0 0 1 3 times boost 1/6 bias EV=“1,0,0,0,0,0,0” Voltage booster ”ON” 0 1 0 1 * * 1 1 Internal operational amplifier ”ON” 1 1 1 1 0 0 1 0 0 1 0 1 * * * * 0 1 * 1 0 0 0 0 RE=”0” 3rd line 2-line (1/34Duty) Display Control 0 0 1 0 0 0 1 1 Dot matrix display “ON” Icon display ”ON” Partial Display *1 *2 *3 Wait until the discharge is completed. Wait until the VDCOUT (VOUT) is stabilized. Wait until the external LCD power supply (VOUT, VLCD, V1 to V4) are stabilized. Refer to (10) PARTIAL DISPLAY . Ver.2009-05-20 - 95 - NJU6645 Preliminary (21-7) Smooth Scroll Display Sequence [Example : 5-line display, 4-dot scroll] 5-line display, Display ON -------------------- Instruction Code ------------------D7 1 0 0 0 0 0 D6 1 1 1 1 1 1 D5 1 1 1 1 1 1 D4 1 1 1 1 1 0 D3 * 0 1 1 0 * D2 * 1 0 1 0 0 D1 * 0 0 0 0 0 D0 0 0 0 0 0 1 ----- Setting Example ----- RE Flag Scroll Start Row Scroll Start Row Scroll Start Row Scroll Start Row Scroll Start Line RE=”0” 4-row scroll 8-row scroll 12-row scroll 0-row scroll 1-line scroll RE Flag RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RE Flag Scroll Start Row Scroll Start Row Scroll Start Row Scroll Start Row Scroll Start Line 1 0 0 1 * * 1 0 0 0 0 0 1 1 1 0 * * 1 1 1 1 1 1 1 1 1 0 * * 1 1 1 1 1 1 1 0 1 0 * * 1 1 1 1 1 0 * 0 0 0 * * * 0 1 1 0 * * 0 0 0 * * * 1 0 1 0 0 * 0 0 0 * * * 0 0 0 0 1 1 0 0 0 * * 0 0 0 0 0 0 RE=”1” 1st line DDRAM address set (000h) 1st line writing DDRAM data RE=”0” 4-row scroll 8-row scroll 12-row scroll 0-row scroll 2-line scroll Refer to (11) VERTICAL SMOOTH S SCROLL. - 96 - Ver.2009-05-20 Preliminary (21-8) Superimpose Mode Display Sequence [Example : Character display on 2nd ~ 5th line] Operational Status -------------------- Instruction Code ------------------D7 1 0 1 0 0 1 * * D6 1 1 1 1 1 0 * * D5 1 0 1 1 1 0 * * D4 1 1 1 0 1 0 * * D3 * * * 0 0 0 * * D2 * 1 * 0 0 0 * * D1 * 0 * 0 1 0 * * D0 0 0 1 0 0 0 * * NJU6645 ----- Setting Example ----- RE Flag Display / Entry Mode RE Flag RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RE=”0” Superimpose mode RE=”1” 2nd line DDRAM address set (020h) 2nd line DDRAM data writing Repeating 3rd to 4th line RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RAM Address Set 1 RAM Address Set 2 RAM Address Set 3 RAM Data Write RAM Data Write RE Flag Display Control 0 0 1 * * 0 0 1 * * 1 0 1 1 0 * * 1 1 0 * * 1 0 1 1 0 * * 1 1 0 * * 1 1 0 1 0 * * 0 1 0 * * 1 0 0 1 0 * * 0 0 0 * * * 0 0 0 0 * * 0 0 0 * * * 0 0 0 0 * * 0 0 1 * * * 1 0 0 0 * * 0 0 0 * * 0 1 5th line DDRAM address set (080h) 5th line DDRAM data writing CGRAM address set (200h) CGRAM data writing RE=”0” Dot matrix display “ON” Icon display ”ON” Data Display Refer to (13-3) Superimpose Mode. Ver.2009-05-20 - 97 - NJU6645 PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Supply Voltage (4) Supply Voltage (5) Supply Voltage (6) Input Voltage (1) Operating Temperature Storage Temperature *1 *2 Preliminary SYMBOL VDD VEE VOUT, VDCOUT VREG VLCD V1, V2, V3, V4 VI Topr Tstg Bump Chip CONDITION TERMINAL VDD VEE VOUT, VDCOUT VREG VLCD V1, V2, V3, V4 RATING -0.3 to +4.0 -0.3 to +4.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to VLCD+0.3 -0.3 to VDD+0.3 -40 to +85 -55 to +125 UNIT V V V V V V V °C °C ! ABSOLUTE MAXIMUM RATINGS VSS=0V Common Ta=+25°C If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. The order of turning on the power supply should turn on VDD earlier than other power supplies. When the power supply is turned off, that requires turning off VDD at the last. ! RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage SYMBOL VDD1 VDD2 VEE VLCD VOUT VDCOUT VREG VREF TERMINAL VDD VEE VLCD VOUT VDCOUT VREG VREF MIN 2.4 2.4 2.4 4.5 1.8 TYP MAX UNIT 3.6 V 3.6 V 3.6 V 17.0 V 17.0 V 17.0 V VOUTx0.9 V 3.6 V NOTE *1 *2 *3 *4 Operating Voltage *5 *6 *1 *2 *3 *4 *5 *6 *7 Applied to the condition when the reference voltage generator (VBA) is not used. (VSS common) Applied to the condition when the reference voltage generator (VBA) is used. (VSS common) Applied to the condition when the voltage booster is used. The following relation among the LCD bias voltages must be maintained. VSS