NJW1112V

NJW1112 8-IN 4-OUT STEREO AUDIO SELECTOR GENERAL DESCRIPTION The NJW1112 is an 8-input 4-output stereo audio selector. It includes four independent 8-input-1output stereo audio selectors and 0dB fixed gain buffers. The NJW1112 performs superior audio characteristics such as low distortion, low output noise and low crosstalk. In addition, the NJW1112 is available to expand to 16-input 4-output stereo audio selector without sound quality deterioration, because it is able to connect in parallel by Output switch function. All of internal status and variables are controlled by three-wired serial bus. Selectable two Chip address is available for using two chips on same serial bus line. It is suitable for AV amplifiers, AV receivers, Analog audio switchers, Video conferencing, Security systems and others. FEATURES • Operating Voltage • 8-Input, 4-Output Stereo Audio Selector • Operating Current • Low On Resistance Output Switch • Low Distortion • Low Output Noise • Low Crosstalk • Channel Separation • 3-Wired Serial Control • Bi-CMOS Technology • Package Outline BLOCK DIAGRAM PACKAGE OUTLINE NJW1112V ±4.5 to ±7.5V 14mA typ. On Resistance :15Ω typ. 0.0007% typ. -119dBV typ. 120dB typ. 116dB typ. SSOP32 V- DATA LATCH CLOCK ADR V+ + V- OutA1 OutB1 OutA2 OutB2 OutA3 OutB3 OutA4 OutB4 10µF + + 10 µF 100µF + 10µF + 10µF + 10µF + 10µF + 10µF + 10µF + 10µF + 100µF 32 VDDOUT 31 30 29 28 27 26 GND 25 24 23 22 21 20 19 18 17 Control Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Rin + + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin + Rin InA1 InB1 InA2 InB2 InA3 InB3 InA4 InB4 InA5 InB5 InA6 InB6 InA7 InB7 InA8 InB8 Ver.0.2 –1– NJW1112 PIN CONFIGURATION 32 17 1 16 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol InA1 InB1 InA2 InB2 InA3 InB3 InA4 InB4 InA5 InB5 InA6 InB6 InA7 InB7 InA8 InB8 Function Ach Input 1 Bch Input 1 Ach Input 2 Bch Input 2 Ach Input 3 Bch Input 3 Ach Input 4 Bch Input 4 Ach Input 5 Bch Input 5 Ach Input 6 Bch Input 6 Ach Input 7 Bch Input 7 Ach Input 8 Bch Input 8 No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol OutB4 OutA4 OutB3 OutA3 OutB2 OutA2 OutB1 OutA1 VGND V+ ADR CLOCK LATCH DATA VDDOUT Function Bch Output 4 Ach Output 4 Bch Output 3 Ach Output 3 Bch Output 2 Ach Output 2 Bch Output 1 Ach Output 1 V- Power Supply Terminal Ground Terminal V+ Power Supply Terminal Chip address setting terminal CLOCK LATCH DATA Internal Digital Power Supply Output –2– Ver.0.2 NJW1112 ABSOLUTE MAXIMUM RATING (Ta=25°C) PARAMETER SYMBOL Power Supply Voltage Maximum Input Voltage Power Dissipation Operating Temperature Range Storage Temperature Range V + RATING +8/-8 V /V 800 + - UNIT V V mW °C °C VIM PD Topr Tstg NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting -40 to +85 -40 to +125 RECOMMENDED OPERATING CONDITIONS (Ta=25°C) PARAMETER Operating Voltage SYMBOL V+/VTEST CONDITION MIN. TYP. MAX. UNIT V - ±4.5 ±7.0 ±7.5 ELECTRICAL CHARACTERISTICS ♦Power Supply (Ta=25°C, V+/V-=±7V) PARAMETER Supply Current 1 Supply Current 2 SYMBOL ICC IEE TEST CONDITION V+, No Signal V-, No Signal MIN. 7.0 7.0 TYP. 14.0 14.0 MAX. 21.0 21.0 UNIT mA mA ♦AC CHARACTERISTICS (Ta=25°C, V+/V-=±7V, VIN=2Vrms,f=1kHz,RL=47kΩ) PARAMETER Maximum Output Voltage Voltage Gain Total Harmonic Distortion 1 Total Harmonic Distortion 2 Total Harmonic Distortion 3 Mute Level Output Noise Cross Talk 1 Cross Talk 2 Channel Separation 1 Channel Separation 2 Output impedance SYMBOL VOM GV THD1 THD2 THD3 ATT VNO CT1 CT2 CS1 CS2 ROUT TEST CONDITION THD=1% BW=400Hz-30kHz Vin=1Vrms, BW=400Hz-30kHz f=10kHz, BW=400Hz-30kHz Selector=Mute, A-weighted Rg=0Ω, A-Weighted Rg=0Ω, A-Weighted Rg=0Ω, f=20kHz Rg=0Ω, A-Weighted Rg=0Ω, f=20kHz Output Switch = ON MIN. 11.1 (3.6) TYP. 12.9 (4.4) MAX. 1.0 0.02 -110 (3.2) UNIT dBV (Vrms) -1.0 - 0 0.001 0.0007 0.002 -120 -119 (1.1) dB % dB dBV (µVrms) -120 -100 -116 -96 15 -90 30 dB dB Ω BW: Band Width ♦Logic Control Characteristics (Ta=25°C, V+/V-=±7V) PARAMETER High Level Input Voltage Low Level Input Voltage SYMBOL VH VL TEST CONDITION ADR, LATCH, DATA, CLOCK Terminal ADR, LATCH, DATA, CLOCK Terminal MIN. 2.5 0 TYP. MAX. V + UNIT V 1.5 Ver.0.2 –3– NJW1112 TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE V+ 1 to 16 InA1 to 8 InB1 to 8 Ach Input 1 to 8 Bch Input 1 to 8 200Ω 0V V-(sub) V+ 50Ω V+ 17 to 24 OutA1 to 4 OutB1 to 4 Ach Output 1 to 4 Bch Output 1 to 4 50Ω V-(sub) 0V 27 V+ V+ Power Supply Terminal V+ V-(sub) V+ 26 GND Ground Terminal 0V V-(sub) V+ 28 29 30 31 ADR CLOCK LATCH DATA Chip address setting terminal CLOCK LATCH DATA 4kΩ 0V 8kΩ V-(sub) –4– Ver.0.2 NJW1112 TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE V+ 70kΩ 32 VDDOUT Internal Digital Power Supply Output 25kΩ 20kΩ 200Ω V-(sub)+5V V-(sub) V-(sub) Ver.0.2 –5– NJW1112 CONTROL DATA FORMAT t7 t1 t2 t3 t4 t8 LATCH CLOCK MSB LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA D15 () MSB First t5 t6 Note.) Set CLOCK in High to prevent incorrect operation during a standby period. SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER CLOCK Clock Width CLOCK Pulse Width (High) CLOCK Pulse Width (Low) LATCH Rise Hold Time DATA Setup Time DATA Hold Time CLOCK Setup Time LATCH High Pulse Width MIN 4 2 2 4 1.6 1.6 1.6 1.6 TYP - MAX - UNIT µsec µsec µsec µsec µsec µsec µsec µsec CONTROL DATA NJW1112 control data is constructed with 16bits. MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Setting DATA Select Address D10 D9 D8 D7 0 0 0 0 D6 0 0 0 0 D5 0 0 1 1 D4 0 1 0 1 D3 * * * * Chip Address D2 * * * * D1 * * * * D0 * * * * LSB D0 MSB D15 D14 Don’t Care Don’t Care Don’t Care Don’t Care D13 D12 OutSW1 OutSW2 OutSW3 OutSW4 D11 Selector1 Selector2 Selector3 Selector4 LSB * Chip address is set by chip address select terminal (ADR) status. Chip address ADR Low High D3 1 1 D2 0 0 D1 1 1 D0 0 1 –6– Ver.0.2 NJW1112 INITIAL CONDITION MSB D15 0 0 0 0 D14 0 0 0 0 D13 0 0 0 0 D12 0 0 0 0 D11 0 0 0 0 D10 0 0 0 0 D9 0 0 0 0 D8 0 0 0 0 D7 0 0 0 0 D6 0 0 0 0 D5 0 0 1 1 D4 0 1 0 1 D3 * * * * D2 * * * * D1 * * * * D0 * * * * LSB Note.) This product starts up by MUTE setting in power “ON”. Use it after removing MUTE of each setting. If any audio signal is inputted in input signal terminal before power “ON”, it may cause initial condition abnormality. In conditions of use such as the above, it prevents that abnormality by setting MUTE before power “OFF" CONTROL DATA Selector OutSW D15 D14 Don’t Care Don’t Care Don’t Care Don’t Care D13 D12 OutSW1 OutSW2 OutSW3 OutSW4 D11 : Selector for the stereo inputs from InA1/B1 to InA8/B8 : Output ON/OFF setting D10 D9 D8 D7 0 0 0 0 D6 0 0 0 0 D5 0 0 1 1 D4 0 1 0 1 D3 * * * * D2 * * * * D1 * * * * D0 * * * * Selector1 Selector2 Selector3 Selector4 a) Selector Data D11 0 0 0 0 0 0 0 0 1 D10 0 0 0 0 1 1 1 1 0 D9 0 0 1 1 0 0 1 1 0 D8 0 1 0 1 0 1 0 1 0 Setting Mute () InA1/B1 InA2/B2 InA3/B3 InA4/B4 InA5/B5 InA6/B6 InA7/B7 InA8/B8 () Initial Setting b) OutSW Data D12 0 1 Setting Output ON () () Output OFF Initial Setting Ver.0.2 –7– NJW1112 APPLICATION CIRCUIT 1 InA1 10 µF + 1 Rin VDDOUT 32 + V- 10µF 10 µF InB1 + 2 31 DATA Control Logic InA2 10 µF Rin + 3 Rin 30 LATCH 10 µF InB2 + 4 Rin 29 CLOCK InA3 10 µF + 5 Rin 28 ADR 10 µF InB3 + 6 Rin 27 + V+ 100µF InA4 10 µF + 7 Rin GND 26 100µF + 10 µF InB4 + 8 Rin 50kΩ 25 V- InA5 10 µF + 9 Rin 50kΩ 24 + OutA1 10µF 10 µF InB5 + 10 Rin 23 + OutB1 10µF InA6 10 µF + 11 Rin 50kΩ 22 + OutA2 10µF 10 µF InB6 + 12 Rin 50kΩ 21 + OutB2 10µF InA7 10 µF 50kΩ + 13 Rin 50kΩ 20 + OutA3 10µF 10 µF InB7 + 14 Rin 50kΩ 19 + OutB3 10µF InA8 10 µF + 15 Rin 18 + OutA4 10µF 10 µF InB8 + 16 Rin 50kΩ 17 + OutB4 10µF NOTES () Separate the 3-wired serial control bus line from the input terminals (1pin to 16pin) for avoiding digital noise problem and cross talk. ( ) Cross talk performance may be effected by PCB patterning and Input resistor “Rin” in relation to input impedance. Widen intervals of input lines (1pin to 16pin) and put guard patterns (ground patterns) among input lines for avoiding cross talk problem. Further, cross talk performance may be effected by input resistor “Rin”. In consideration of an actual operating condition, please decide Rin values after evaluating. ( ) The output terminals of this device are designed as a line driver. Use them by load resistances more than 2kΩ because output waveforms may be in an unstable condition. –8– Ver.0.2 NJW1112 APPLICATION CIRCUIT 2 The NJW1112 is available to expand to 16-input 4-output stereo audio selector without sound quality deterioration, because it is able to connect in parallel by Output switch function. InA1 10µF + 1 Rin VDDOUT 32 + V- In1 InB1 10 µF 10µF + 2 31 DATA Control Logic InA2 10µF Rin + 3 Rin 30 LATCH In2 InB2 10µF + 4 Rin 29 CLOCK InA3 10µF + 5 Rin 28 ADR=V+ In3 InB3 10µF + 6 Rin 27 + V+ 100 µF InA4 10µF + 7 Rin GND 26 100 µF + In4 InB4 10µF + 8 Rin 50kΩ 25 V- InA5 10µF + 9 Rin 50kΩ 24 + OutA1 10 µF In5 10µF InB5 + Out1 23 + 10 Rin 50kΩ OutB1 10 µF InA6 10µF + 11 Rin 22 + OutA2 10 µF In6 10µF InB6 + 12 Rin 50kΩ Out2 21 + OutB2 10 µF InA7 10µF 50kΩ + 13 Rin 50kΩ 20 + OutA3 10 µF In7 10µF InB7 + Out3 19 + 14 Rin 50kΩ OutB3 10 µF InA8 10µF + 15 Rin 50kΩ 18 + OutA4 10 µF In8 10µF InB8 + Out4 17 + 16 Rin OutB4 10 µF InA1 10µF + 1 Rin VDDOUT 32 + V- In9 InB1 10 µF 10µF + 2 31 Control Logic InA2 10µF Rin + 3 Rin 30 In10 InB2 10µF + 4 Rin 29 InA3 10µF + 5 Rin 28 ADR=GND In11 InB3 10µF + 6 Rin 27 + V+ 100µF InA4 10µF + 7 Rin GND 26 100µF + In12 InB4 10µF + 8 Rin 50kΩ 25 V- InA5 10µF + 9 Rin 50kΩ 24 + In13 10µF InB5 + 10 µF 10 Rin 23 + 10 µF InA6 10µF + 11 Rin 50kΩ 22 + In14 10µF InB6 + 10 µF 12 Rin 50kΩ 21 + 10 µF InA7 10µF 50kΩ + 13 Rin 50kΩ 20 + In15 10µF InB7 + 10 µF 14 Rin 50kΩ 19 + 10 µF InA8 10µF + 15 Rin 18 + In16 10µF InB8 + 10 µF 16 Rin 50kΩ 17 + 10 µF Ver.0.2 –9– NJW1112 APPLICATION CIRCUIT 3 The NJW1112 is available to expand to 8-input 8-output stereo audio selector. 10 µF InA1 + 1 Rin VDDOUT 32 + V- In1 InB1 10 µF 10 µF + 2 31 DATA Control Logic 10 µF InA2 Rin + 3 Rin 30 LATCH In2 InB2 10 µF + 4 Rin 29 CLOCK 10 µF InA3 + 5 Rin 28 ADR=V+ In3 InB3 10 µF + 6 Rin 27 + V+ 100 µF 10 µF InA4 + 7 Rin GND 26 100 µF + In4 InB4 10 µF + 8 Rin 50kΩ 25 V- 10 µF InA5 + 9 Rin 50kΩ 24 + OutA1 10 µF In5 10 µF InB5 10 µF InA6 + Out1 23 + 10 Rin 50kΩ OutB1 10 µF + 11 Rin 22 + OutA2 10 µF In6 10 µF InB6 10 µF InA7 + 12 Rin 50kΩ Out2 21 + OutB2 10 µF 50kΩ + 13 Rin 50kΩ 20 + OutA3 10 µF In7 10 µF InB7 10 µF InA8 + Out3 19 + 14 Rin 50kΩ OutB3 10 µF + 15 Rin 50kΩ 18 + OutA4 10 µF In8 10 µF InB8 + Out4 17 + 16 Rin OutB4 10 µF 1 VDDOUT 32 + V- 10 µF 2 31 Control Logic 3 30 4 29 5 28 ADR=GND 6 27 + V+ 100 µF 7 GND 26 100 µF + 8 50kΩ 25 V- 9 50kΩ 24 + OutA1 10 µF Out5 OutB1 10 50kΩ 23 + 10 µF 11 22 + OutA2 10 µF Out6 OutB2 12 50kΩ 21 + 10 µF 50kΩ 13 50kΩ 20 + OutA3 10 µF Out7 19 + 14 50kΩ OutB3 10 µF 15 50kΩ 18 + OutA4 10 µF Out8 OutB4 16 17 + 10 µF – 10 – Ver.0.2 NJW1112 TYPICAL CHARACTERISTICS ICC vs Supply Voltage No signal , Ta=-40,25,85oC IEE vs Supply Voltage No signal , Ta=-40,25,85oC 20 20 15 25oC, 85oC -40oC 25oC, 85oC 15 -40oC ICC [mA] 10 IEE [mA] 4 5 6 V+/V- [V] Maxim um Output Voltage vs Frequency 7 8 10 5 5 0 0 4 5 6 V+/V- [V] Maxim um Output Voltage vs Supply Voltage 6.0 V+/V- =±7V,THD=1%, I/O: INA1-1Aout , Ta=-40,25,85oC 7 8 5.0 V+/V- =±7V, THD=1%, I/O: INA1-1Aout , Ta= -40,25,85oC 85oC Maximum Output Voltage [Vrms ] 4.5 25oC Maximum Output Voltage [Vrms ] -40oC 5.0 85oC 4.0 4.0 3.0 25oC, -40oC 2.0 3.5 1.0 3.0 10 100 1000 Frequency [Hz] 10000 100000 0.0 4 5 6 V+/V- [V] 7 8 Maxium Output Voltage vs Load Resistance V+/V- =±7V, f=1kHz , I/O: INA1-1Aout , Ta=-40,25,85oC Gain vs Frequency V+/V- =±7V, Vin=2Vrms , I/O: INA1-1Aout , Ta=-40,25,85oC 5 2 85 C Maximum Output Voltage [Vrms ] o 25oC -40oC 1 4 Gain [dB] 3 0 2 -1 1 1000 -2 RL[Ω] 10000 10 100 1000 Frequency [Hz] 10000 100000 Ver.0.2 – 11 – NJW1112 TYPICAL CHARACTERISTICS THD+N vs Input Voltage V+/V- =±7V, I/O: INA1-1Aout , BW:10-22kHz ( f=100Hz ) 400-30kHz ( f = 1,10kHz ) , Ta=25oC THD+N vs Frequency V+/V- =±7V, I/O: INA1-1Aout, BW:10-80kHz, Vin=2Vrms , Ta=-40,25,85oC 1 1 0.1 10kHz 100Hz 1kHz THD+N [%] 0.1 o 85oC 25 C THD+N [%] 0.01 0.01 -40oC 0.001 0.001 0.0001 0.01 0.0001 0.1 1 Input Voltage [Vrms] 10 10 100 1000 Frequency [Hz] 10000 100000 THD+N vs Am bient Tem perature V+/V- =±7V, I/O: INA1-1Aout , BW:400-30kHz ( f = 1 kHz ) 1 0.1 THD+N [%] 2Vrms 0.01 1Vrms 0.001 0.0001 -40 -20 0 25 50 85 100 Ambient Temperature [oC] 125 Cross Talk vs Frequency V+/V- =±7V, Vin=2Vrms, BW:10Hz-80kHz, I/O: INA1,3,4,5,6,7,8 / OutA1,Select channel:INA2, Ta=25o C Channel Separation vs Frequency V+/V- =±7V, Vin=2Vrms , BW:10Hz-80kHz, I/O: INB1,2,3,4,5,6,7,8 / OutA1, Select channel:INA2 Ta=25o C -40 -40 Rg=5.1k Ω Rg=3.3k Ω Rg=5.1k Ω -60 Channel Separation[dB] Rg=3.3k Ω Rg=620Ω Cross Talk[dB] -60 Rg=620Ω -80 -80 Rg=0Ω Rg=0Ω -100 -100 -120 10 100 1000 Frequency [Hz] 10000 100000 -120 10 100 1000 Frequency [Hz] 10000 100000 – 12 – Ver.0.2 NJW1112 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.0.2 – 13 –