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NJW1154V

NJW1154V

  • 厂商:

    NJRC

  • 封装:

  • 描述:

    NJW1154V - 2-CHANNEL ELECTRONIC VOLUME WITH INPUT SELECTOR - New Japan Radio

  • 数据手册
  • 价格&库存
NJW1154V 数据手册
NJW1154 2-CHANNEL ELECTRONIC VOLUME WITH INPUT SELECTOR s GENERAL DESCRIPTION NJW1154 is a two channel electronic volume with 6 in 1 out selector IC. It’s suitable for Input signal trimmer of audio equipments such as DVD recorder 2 and VCR. These functions are controlled by I C Bus. s PACKAGE OUTLINE s FEATURES q Operating Voltage 2 q I C Bus control q 6in 1out Input Selector q Volume q Bi-CMOS Technology q Package Outline s BLOCK DIAGRAM NJW1154V 8 to 13V +12 to -12dB/3dBstep, MUTE SSOP32 1uF 47KΩ 100uF 47KΩ C28 C27 R5 R4 ALCCNT ALCOUT LOUT ROUT SCL V+ 12V 10uF 22KΩ 10uF 10uF 10uF C22 10uF 10uF C17 SDA C16 22uF C15 17 Vref ALC Control 16 18KΩ ALCVTH 1uF ALCINT R2 10uF 10uF VREFOUT C21 62KΩ 1uF 100uF L1IN R1IN C24 C23 R3 C20 C25 C19 C18 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC 18 GND I2C Bus Interface Internal Power Supply Vref Vref 1 10uF C2 C1 2 10uF C3 3 10uF C4 4 100uF C5 5 10uF C6 6 10uF C7 7 10uF C8 8 100uF C9 9 10uF C10 10 10uF C11 11 10uF C12 12 10uF C13 13 10uF C14 14 10uF R7IN 15 DCCAP_R1 DCCAP_L1 R5IN L6IN L5IN R3IN R2IN R4IN R6IN L2IN L3IN L4IN L7IN R1 C26 VDDOUT ALC2IN ALC1IN VREFIN V+ –1– NJW1154 s ABSOLUTE MAXIMUM RATING (Ta=25°C) PARAMETER SYMBOL Power Supply Voltage Power Dissipation Operating Temperature Range Storage Temperature Range V+ PD Topr Tstg RATING 15 800 NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting UNIT V mW °C °C -20 to +75 -40 to +125 s ELECTRICAL CHARACTERISTICS (Ta=25°C,V+=+12V, RL=47kΩ) PARAMETER x Power Supply Operating Voltage Reference Voltage Supply Current V+ Vref ICC No signal 8 5.5 12 6 7 13 6.5 9 V V mA SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT x Input/Output Characteristics (Output) Maximum Output Voltage Voltage Gain 1 Voltage Gain 2 Voltage Gain 3 Voltage Gain Error 1 Voltage Gain Error 2 Maximum Attenuation Output Noise Total Harmonic Distortion Cross Talk Channel Separation VOM GV1 GV2 GV3 ∆GV1 ∆GV2 ATT VNO T.H.D CT CS f=1KHz,THD=1% Volume=0dB VIN=1Vrms, f=1kHz Volume=0dB VIN=0.25Vrms, f=1kHz Volume=+12dB VIN=2.5Vrms, f=1kHz Volume=-12dB VIN=0.25Vrms, f=1kHz Volume=+12dB , Ach - Bch VIN=2.5Vrms, f=1kHz Volume=-12dB , Ach - Bch f=1KHz, VIN=1Vrms Volume=Mute, A-weighted Volume=0dB, Rg=0,A-weighted f=1KHz,Vo=1Vrms, Volume=0dB, BW:400 – 30kHz Selected Input : No signal Rg=0Ω Unselected Input : Input signal A-weighted 3.2 -0.5 +11 -13 -0.5 -0.5 - 3.7 0 +12 -12 0 0 -110 -114 (2µ) 0.001 -100 -100 0.5 +13 -11 0.5 0.5 -100 (10µ) 0.05 -90 Vrms dB dB dB dB dB dB dBV (Vrms) % dB dB f=1KHz,Vo=1Vrms,A-weighted Volume=0dB x ALC Flat Level ALC Cut Level ALCFLT ALCCUT Vin = 300mVrms Vin = 2Vrms - 0 -12 - dB dB –2– NJW1154 s I C BUS BLOCK CHARACTERISTICS (SDA,SCL) I C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND) 2 2 PARAMETER Low Level Input Voltage High Level Input Voltage Hysteresis of Schmitt trigger inputs LOW level output voltage (3mA at SDA pin) Output fall time from VIHmin to VILmax with a bus capacitance from 10pF to 400pF Pulse width of spikes which must be suppressed by the input filter SYMBOL VIL VIH Vhys VOL tof tSP Ii Ci fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF Cb VnL VnH MIN. 0.0 3.0 0.25 0 20+0.1Cb TYP. - MAX. 1.5 5.0 0.4 250 50 10 10 400 0.9 300 300 400 - UNIT V V V V ns ns µA pF kHz µs µs µs µs µs ns ns ns µs µs pF V V 0 -10 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0.5 1 Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax Capacitance for each I/O pin SCL clock frequency Hold time (repeated) START condition. LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level Noise margin at the HIGH level Cb ; total capacitance of one bus line in pF. SDA tBUF tR tF tHD:STA SCL tHD:STA tLOW P S tHD:DAT tHIGH tSU:DAT Sr tSU:STA tSU:STO P –3– NJW1154 s APPLICATION CIRCUIT –4– C1 1 L2IN 32 L1IN 10uF C24 2 R1IN 10uF V+ 12V 3 30 V+ C28 100uF LOUT 10uF C22 28 ROUT 10uF R3 6 27 ALCCNT 22KΩ C20 7 26 10uF C19 8 25 10uF C18 24 10uF C17 23 10uF GND 11 22 10 VREFIN 9 ALC1IN ALC2IN C27 1uF R4 47KΩ R5 47KΩ ALCOUT C23 29 31 10uF C2 L3IN 10uF C3 R3IN 10uF C4 4 Vref DCCAP_R1 100uF C5 Vref 5 R2IN 10uF C6 L4IN 10uF C7 R4IN 10uF C8 DCCAP_L1 100uF C9 L5IN 10uF C10 R5IN 10uF C11 L6IN 10uF C12 R6IN 12 10uF C13 13 L7IN 10uF C14 14 19 R7IN 10uF R1 15 C26 18KΩ ALCINT R2 62KΩ 16 1uF C21 1uF ALCVTH C16 18 VDDOUT Vref ALC Control 22uF C15 17 VREFOUT 100uF Internal Power Supply NC I2C Bus Interface C25 SCL 21 20 SDA NJW1154 s DEFINITION OF I C REGISTER 2 ♦I C BUS FORMAT MSB LSB MSB LSB MSB LSB 2 S 1bit Slave Address 8bit A 1bit Select Address 8bit A 1bit Data 8bit A 1bit P 1bit S: Starting Term A: Acknowledge Bit P: Ending Term ♦SLAVE ADDRESS MSB LSB 1 0 0 0 0 0 1 R/W R/W=0: Receive Only R/W=1: No Output Data ♦CONTROL REGISTER TABLE The select address sets each function (Volume, Selector). The auto increment function cycles the select address as follows. 00H¡01H¡02H¡00H Select Address 00H 01H 02H BIT D7 D6 Don’t Care Don’t Care Don’t Care D5 D4 D3 D2 VOLa VOLb D1 D0 Selector ♦CONTROL REGISTER DEFAULT VALUE Control register default values are as follows : Select Address 00H 01H 02H BIT D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 –5– NJW1154 s CONTROL COMMAND TABLE a) Master Volume Select Address 00H 01H BIT D7 D6 D5 Don’t Care Don’t Care D4 D3 D2 VOLa VOLb D1 D0 •VOLa / VOLb : Ach and Bch volume level setting from +12dB to -12dB with 3dB step. VOLa / VOLb D2 D1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 Gain (dB) +12 +9 +6 +3 0 -3 -6 -9 -12 Mute D3 0 0 0 0 0 0 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 b)Input Selector Select Address 02H BIT D7 D6 D5 Don’t Care D4 D3 D2 D1 Selector D0 •Selector : Input signal selecting Selector Input L1IN / R1IN L2IN / R2IN L3IN, L4IN / R3IN, R4IN L5IN / R5IN L6IN / R6IN L7IN / R7IN D2 0 0 0 0 1 1 D1 0 0 1 1 0 0 D0 0 1 0 1 0 1 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. –6–
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