NJW4161
MOSFET Drive Switching Regulator IC for Buck Converter
GENERAL DESCRIPTION
■ PACKAGE OUTLINE
The NJW4161 is a MOSFET Drive switching regulator IC for
Buck Converter that operates wide input range from 3.1V to 40V.
It can provide large current application because of built-in highly
effective Pch MOSFET 10V drive circuit.
There are two types, Hiccup type and Latch type, of over
current protection version.
It is suitable for logic voltage generation from high voltage that
Car Accessory, Office Automation Equipment, Industrial
Instrument and so on.
NJW4161R
(MSOP8(VSP8))
NJW4161D
(DIP8)
FEATURES
Pch MOSFET Driving
Driving Voltage V+-10V(typ.)
Wide Operating Voltage Range
3.1V to 40V
PWM Control
Automatic PWM/PFM Control improves power efficiency at light load. (C ver.)
Wide Oscillating Frequency
50kHz to 1MHz
Soft Start Function
15ms (typ.)
Over Current Protection
Hiccup type (A, C ver.)
Latch type (B ver.)
Thermal Shutdown Protection
UVLO (Under Voltage Lockout)
Standby Function
Package Outline
NJW4161R: MSOP8(VSP8) *MEETJEDEC MO-187-DA
NJW4161D: DIP8
PRODUCT CLASSFICATION
Part Number
Version
Controller
Over Current
Protection
Package
NJW4161R-A
A
PWM control
Hiccup type
MSOP8
(VSP8)
NJW4161D-A
A
PWM control
Hiccup type
DIP8
NJW4161R-B
B
PWM control
Latch type
NJW4161R-C
C
PWM/PFM
control
Hiccup type
Ver.2016-03-22
MSOP8
(VSP8)
MSOP8
(VSP8)
Operating
Temperature
Range
General Spec.
-40 C to +125 C
General Spec.
-40 C to +125 C
General Spec.
-40 C to +125 C
General Spec.
-40 C to +125 C
-1-
NJW4161
PIN CONFIGURATION
REGH 1
8
GND
SI 2
7
RT
OUT 3
6
FB
+
5
IN-
V
4
NJW4161R-A
NJW4161R-B
NJW4161R-C
NJW4161D-A
PIN DESCRIPTIONS
PIN NAME
PIN
NUMBER
REGH
1
SI
2
OUT
3
V+
4
IN-
5
FB
6
RT
7
GND
8
-2-
FUNCTION
Output pin of the high side regulator.
Connect a bypass capacitor to stabilize a driver circuit.
Current Sensing pin
When difference voltage between the V+ pin and the SI pin exceeds 120mV(typ.),
over current protection operates.
Output pin for Power MOSFET Driving
The OUT pin Voltage is clamped with V+ -10V(typ.) at the time of Low level, in
order to protect a gate of Pch MOSFET.
Power Supply pin
Output Voltage Detecting pin
Connects output voltage through the resistor divider tap to this pin in order to
voltage of the IN- pin become 0.8V.
Feedback Setting pin
The feedback resistor and capacitor are connected between the FB pin and the
IN- pin.
Oscillating Frequency Setting pin by Timing Resistor.
Oscillating Frequency should set between 50kHz and 1MHz.
NJW4161 becomes the standby mode when make RT pin open.
GND pin
Ver.2016-03-22
NJW4161
BLOCK DIAGRAM
V+
Enable
Control
VREG
SI
UVLO
VIPK
Soft Start
Pulse by
Pulse
10V
Regulator
500k
PWM
Comparator
OSC
Error AMP
0.8V
VREF
Driver
OUT
REGH
PWM/PFM
Control
TSD
*C version only
IN-
RT
FB
GND
RT State
ON: Connect timing resistor to GND
OFF (Stand-by): RT terminal open
Ver.2016-03-22
-3-
NJW4161
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage
V+
OUT pin Voltage
VOUT
SI pin Voltage
VSI
REGH pin Voltage
VREGH
IN- pin Voltage
VINRT pin Voltage
VRT
IO_PEAK+
OUT pin Peak Current
IO_PEAKPower Dissipation
Operating Temperature Range
Storage Temperature Range
PD
MAXIMUM RATINGS
-0.3 to +45
V+-11 to V+ (*1)
V+-5 to V+ (*2)
V+-11 to V+ (*1)
-0.3 to +6
-0.3 to +6 (*3)
1,700 (Source)
1,100 (Sink)
MSOP8
(VSP8)
595 (*4)
805 (*5)
DIP8
700 (Device itself)
Topr
Tstg
-40 to +125
-50 to +150
(Ta=25°C)
UNIT
V
V
V
V
V
V
mA
mW
C
C
(*1): When Supply voltage is less than +11V, the absolute maximum rating is -0.3 to V+.
(*2): When Supply voltage is less than +5V, the absolute maximum rating is -0.3 to V+.
(*3): When Supply voltage is less than +6V, the absolute maximum voltage is equal to the Supply voltage.
(*4): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 2Layers)
(*5): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 4Layers),
internal Cu area: 74.2×74.2mm
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
+
Supply Voltage
V
3.1
Timing Resistor
RT
1.5
Oscillating Frequency
fOSC
50
REGH Capacitor
CREGH
0.01
-4-
TYP.
–
–
–
0.1
MAX.
40
43
1,000
1
UNIT
V
k
kHz
F
Ver.2016-03-22
NJW4161
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V+=12V, RT=10k , CREGH=0.1 F, Ta=25 C)
PARAMETER
Oscillator Block
Oscillating Frequency 1
Oscillating Frequency 2
SYMBOL
fOSC1
fOSC2
TEST CONDITION
RT=3.6k
RT=10k
MIN.
TYP.
MAX.
UNIT
450
180
500
200
550
220
kHz
kHz
-1.0%
-0.1
0.8
–
+1.0%
0.1
V
A
Error Amplifier Block
Reference Voltage
Input Bias Current
VB
IB
Output Source Current
IOM+
VFB=1V, VIN-=0.7V
50
90
140
A
Output Sink Current
IOM-
VFB=1V, VIN-=0.9V
6
13
20
mA
Soft Start Block
Soft Start Time
tSS
VB=0.75V
7.5
15
24
ms
VT_0
VT_50
MAXDUTY
Duty=0%, VIN-=0.6V
Duty=50%, VIN-=0.6V
VFB=1.2V
0.32
0.63
100
0.4
0.7
–
0.48
0.77
–
V
V
%
PFMDUTY
C version
5
10
15
%
PWM Comparate Block
Input Threshold Voltage
(FB pin)
Maximum Duty Cycle
PWM/PFM Change
Duty Cycle
Current Limit Detection Block
Current Limit Detection
Voltage
Delay Time
VIPK
110
120
130
mV
tDELAY
–
80
–
ns
Over Current Protection Block
Cool Down Time
Timer Latch Time
tCOOL
tLATCH
A, C version
B version
–
–
60
10
–
–
ms
ms
ROH
IO= -50mA
–
3.5
7
ROL
IO= +50mA
–
3.5
7
50
V+-11
–
150
V+-10
500
250
V+-9
–
mA
V
k
2.9
2.6
3.0
2.7
3.1
2.8
V
V
Output Block
Output High Level
ON Resistance
Output Low Level
ON Resistance
REGH Output Current
OUT pin Limiting Voltage
OUT pin Pull-Up Resistance
IO_REGH
VOLIM
ROUT
REGH pin=V+-8V
Under Voltage Lockout Block
ON Threshold Voltage
OFF Threshold Voltage
VT_ON
VT_OFF
V+= L → H
V+= H → L
Ver.2016-03-22
-5-
NJW4161
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
RT pin Enable Control Block
RT pin Current at Standby
IRT_STB
(Unless otherwise noted, V+=12V, RT=10k , CREGH=0.1 F, Ta=25 C)
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
5.0
–
–
A
–
1.5
3
mA
–
2
10
A
General Characteristics
Quiescent Current
IDD
Standby Current
IDD_STB
RL=no load,
VIN-=0.7V, VFB=0.7V
VRT=OPEN
POWER DISSIPATION vs. AMBIENT TEMPERATURE
NJW4161R (VSP8 Package)
Power Dissipation vs. Ambient Temperature
(Tj=~150°C)
NJW4161D (DIP8 Package)
Power Dissipation vs. Ambient Temperature
(Tj=~150°C)
1000
At on 4 layer PC Board (*7)
At on 2 layer PC Board (*6)
800
Power Dissipation PD (mW)
Power Dissipation PD (mW)
1000
600
400
200
0
800
Device itself
600
400
200
0
-50
-25
0
25
50
75
100
Ambient Temperature Ta (°C)
125
150
-50
-25
0
25
50
75
100
125
150
Ambient Temperature Ta (°C)
(*6): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 2Layers)
(*7): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 4Layers),
internal Cu area: 74.2×74.2mm
-6-
Ver.2016-03-22
NJW4161
TYPICAL APPLICATIONS
Non-isolated Buck Converter
VIN
RSENSE
Q1
CIN1
4
3
2
1
V+
OUT
SI
REGH
VOUT
L
CREGH
CIN2
SBD
COUT
CFB
R2
RFB
NJW4161
IN-
FB
RT
GND
5
6
7
8
R1
RT
RNF
CNF
Q2
Ver.2016-03-22
Enable Control
-7-
NJW4161
TYPICAL CHARACTERISTICS
520
Oscillating Frequency 1 fOSC1 (kHz)
100
1
10
Timing Registor RT (kW)
510
505
500
495
490
485
0
100
Oscillating Frequency 2 vs. Supply Voltage
(RT=10kW, Ta=25ºC)
10
20
30
Supply Voltage V+ (V)
40
Reference Voltage vs. Supply Voltage
(Ta=25ºC)
0.81
208
Reference Voltage VB (V)
Oscillating Frequency 2 fOSC2 (kHz)
515
480
10
210
Oscillating Frequency 1 vs. Supply Voltage
(RT=3.6kW, Ta=25ºC)
206
204
202
200
198
196
194
0.805
0.8
0.795
192
190
0.79
0
40
Quiescent Current vs. Supply Voltage
(RT=10kW, RL=no load, VIN-=VFB=0.7V, Ta=25ºC)
10
20
30
Supply Voltage V+ (V)
Error Amplifier Block
Voltage Gain, Phase vs. Frequency
(V+=12V, Gain=40dB, Ta=25ºC)
60
40
180
Phase
2.5
2
1.5
1
45
135
Gain
30
90
15
45
0.5
0
0
0
-8-
0
Voltage Gain AV (dB)
Quiescent Current IDD (mA)
3
10
20
30
Supply Voltage V+ (V)
Phase F (deg)
Oscillating Frequency fOSC (kHz)
1000
Oscillating Frequency vs. Timing Registor
(V+=12V, Ta=25ºC)
10
20
30
Supply Voltage V+ (V)
40
100
1k
10k
100k
Frequency f (Hz)
1M
0
10M
Ver.2016-03-22
NJW4161
TYPICAL CHARACTERISTICS
220
Oscillating Frequency 2 fOSC2 (kHz)
Oscillating Frequency 1 fOSC1 (kHz)
550
Oscillating Frequency 1 vs. Temperature
(V+=12V, RT=3.6kW)
540
530
520
510
500
490
480
470
460
450
210
205
200
195
190
185
0.805
0.8
0.795
0.79
-50
-50
Current Limit Detection Voltage VIPK (mV)
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Reference Voltage vs. Temperature
(V+=12V)
0.81
Reference Voltage VB (V)
215
180
-50
135
130
125
120
115
110
105
100
-50
11
OUT pin Limited Voltage VOLIM (V)
22
20
18
16
14
12
10
8
6
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Current Limit Detection Votage vs.Temperature
(V+=12V)
140
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Soft Start Time vs. Temperature
(V+=12V, VB=0.75V)
24
Soft Start Time tSS (ms)
Oscillating Frequency 2 vs. Temperature
(V+=12V, RT=10kW)
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
OUT pin Limiting Voltage vs.Temperature
(V+=12V)
10.5
10
9.5
9
-50
Ver.2016-03-22
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
-50
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
-9-
NJW4161
TYPICAL CHARACTERISTICS
10
8
V+=3.1V
6
4
V+=12V, 40V
2
Output Low Level ON Resistance vs.Temperature
(Io=+50mA)
30
Output Low Level ON Resistance
ROL (W)
Output High Level ON Resistance
ROH (W)
Output High Level ON Resistance vs.Temperature
(Io=-50mA)
12
0
10
V+=40V
5
V+=12V
3
VT_ON
2.9
2.8
VT_OFF
2.7
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Quiescent Current vs. Temperature
(RT=10kW, RL=no load, VIN-=VFB=0.7V)
3
Quiescent Current IDD (mA)
Threshold Voltage (V)
15
-50
2.6
2.5
2
V+=40V
1.5
V+=12V
V+=3.1V
1
0.5
0
-50
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
-50
RT pin Current at Standby vs. Temperature
(V+=12V)
9
8
7
6
5
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Standby Current vs. Temperature
(VRT=Open)
10
Standby Current IDD_STB (μA)
RT pin Current at Standby IRT_STB (μA)
V+=3.1V
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Under Voltage Lockout Voltage vs. Temperature
3.1
9
8
7
6
V+=40V
5
4
V+=12V
V+=3.1V
3
2
1
4
0
-50
- 10 -
20
0
-50
10
25
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
-50
-25
0
25 50 75 100 125 150
Ambient Temperature Ta (ºC)
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Description of Block Features
1. Basic Functions / Features
Error Amplifier Section (Error AMP)
0.8V±1% precise reference voltage is connected to the non-inverted input of this section.
To set the output voltage, connects converter's output to inverted input of this section (IN- pin). If requires output
voltage over 0.8V, inserts resistor divider.
This AMP section has high gain and external feedback pin (FB pin). It is easy to insert a feedback resistor and a
capacitor between the FB pin and the IN- pin, making possible to set optimum loop compensation for each type of
application.
Oscillating Circuit Section (OSC)
Oscillating frequency can be set by inserting resistor between the RT pin and GND. Referring to the sample
characteristics in "Timing Resistor and Oscillating Frequency", set oscillation between 50kHz and 1MHz.
NJW4161 becomes the standby mode when make RT pin open. Refer to the description of the standby function
PWM Comparator Section (PWM)
PWM comparator receives the signal of the error amplifier and the triangular wave, and controls the duty ratio
between 0% and 100%. The timing chart is shown in Fig.1.
FB pin Voltage
OSC
Waveform
(IC internal)
High
OUT pin
Low
GND
Fig. 1. Timing Chart PWM Comparator and SW pin
PWM/PFM Control Feature (PWM/PFM Control: Only C version)
NJW4161 C version features automatic PWM/PFM control, improving power efficiency at light load.
Most of the application circuit loss occurs when the switching element performs, and therefore, the switching pulse is
skipped to minimize unnecessary switching loss at times of low load.
When PWM comparator duty is no greater than 10% typ., switching output is stopped and switching is skipped to
next period. In the case of high step-down ratio applications, a duty of steady operation may fall to 10% or less. Under
such conditions, the PWM/PFM switch feature always operates. Therefore for high step-down ratio applications, use
the PWM control type (A version or B version).
Power Supply, GND pin (V+ and GND)
In line with MOSFET drive, current flows into the IC according to frequency. If the power supply impedance
provided to the power supply circuit is high, it will not be possible to take advantage of IC performance due to input
voltage fluctuation. Therefore insert a bypass capacitor more than 0.1 F close to the V+ pin – the GND pin
connection in order to lower high frequency impedance.
Ver.2016-03-22
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NJW4161
NJW4161Application Manual
Technical Information
Description of Block Features (Continued)
Driver Section , 10V Regulator Section (Driver, 10V Regulator)
The output driver circuit is configured a totem pole type, it can efficiently drive a Pch MOSFET switching device.
When the output is low level, the OUT pin voltage is clamped with V+ -10V (typ.) by the internal regulator to protect
gate of Pch MOSFET. (Ref. Fig.2. OUT pin)
V+
V+
VIN
CREGH
10V
Regulator
CIN2
500kW
VGS
From PWM
Comparator
OUT
Driver
RG
REGH
To turn off Pch MOSFET
High Level Output
V+
V+-10V
GND
To turn on Pch MOSFET
Low Level Output
OFF
ON
OFF
ON
Fig. 2. Driver Circuit and the OUT pin Voltage
OUT pin Differential Voltage V+-VOUT (V)
When supply voltage is decreasing, gate drive voltage output from the OUT pin is also decreasing. Fig.3. shows
the example of the “OUT pin Differential Voltage vs. supply voltage” characteristic
The optimum drive ability of MOSFET depends on the oscillating frequency and the gate capacitance of MOSFET.
OUT pin Differential Voltage vs. Supply Voltage
(IO=0mA, Ta=25ºC)
12
10
8
6
4
2
0
0
2
4
6
8
10
Supply Voltage V+ (V)
12
14
Fig. 3. OUT pin Differential Voltage vs. Supply Voltage Characteristic
- 12 -
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Description of Block Features (Continued)
2. Additional and Protection Functions / Features
Under Voltage Lockout (UVLO)
The UVLO circuit operating is released above V+=3.0V(typ.) and IC operation starts. When power supply voltage
is low, IC does not operate because the UVLO circuit operates. There is 300mV width hysteresis voltage at rise and
decay of power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing.
Soft Start Function (Soft Start)
The output voltage of the converter gradually rises to a set value by the soft start function. The soft start time is
15ms (typ.). It is defined with the time of the error amplifier reference voltage becoming from 0V to 0.75V. The soft
start circuit operates after the release UVLO and/or recovery from thermal shutdown.
0.8V
Vref,
IN- pin Voltage
OSC Waveform
(IC internal)
High
OUT pin
Low
GND
UVLO(3.0V typ.) Release,
Standby,
Recover from Thermal
Shutdown
Soft Start time: tSS=15ms(typ.) to VB=0.75V
Steady
Operaton
Soft Start effective period to VB=0.8V
Fig. 4. Startup Timing Chart
Ver.2016-03-22
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NJW4161
NJW4161Application Manual
Technical Information
Description of Block Features (Continued)
Over Current Protection Circuit
At when the potential difference between the V+ pin and the SI pin becomes 120mV or more, the over current
protection circuit is stopped the switch output. The switching current is detected by inserted current sensing resistor
(RSENSE) between the V+ pin and the SI pin.
There are Hiccup type of the automatic return and Latch type of the switching stop in NJW4161.
Hiccup Type: A version, C version
Latch Type: B version
Hiccup Type (A version, C version)
The NJW4161-A and -C output returns automatically along with release from the over current condition.
Fig.5. shows the timing chart of the Hiccup type over current protection detection.
When the IN- pin voltage is 0.5V or lower(less), the switching operation stops after the overcurrent detection
continued 8 pulses.
After NJW4161 switching operation was stopped, it restarts by soft start function after the cool down time of
approx. 60ms (typ.).
IN- pin
Voltage
0.8V
0.5V
0V
Oscillating Frequency
fosc
High
OUT pin
Low
GND
RSENSE
Voltage
VIPK
0
Pulse Count :8 pulse
Cool Down time tCOOL=60ms typ.
Pulse by Pulse
Static Status
Detect Overcurrent
Soft Start
After cool-down time,
NJW4161 restarts automatically.
Fig. 5. Hiccup Type Timing Chart at Over Current Detection
(A version, C version)
- 14 -
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Description of Block Features (Continued)
Latch Type (B version)
When an overcurrent continues, NJW4161-B stops and maintains a stop state.
Fig.6. shows the timing chart of the Latch type over current protection detection.
When the IN- pin voltage is 0.5V or lower(less), the switching operation stops after the overcurrent detection
continued 10ms.
After NJW4161 stopped, it restarts with a soft start by UVLO or standby input.
It does not latch, when it operation stops by thermal shutdown.
IN- pin
Voltage
0.8V
0.5V
0V
Oscillating Frequency
fosc
High
OUT pin
Low
GND
RSENSE
Voltage
VIPK
0
Timer Latch time tLATCH=10ms typ.
Stop Switching (Latch Mode)
Pulse by Pulse
Static Status
Detect Overcurrent
Soft Start
Restart by
UVLO and Stanby.
Fig. 6. Latch Type Timing Chart at Over Current Detection
(B version)
The current waveform contains high frequency superimposed noises due to the parasitic elements of MOSFET,
the inductor and the others. Depending on the application, inserting RC low-pass filter between current sensing
resistor (RSENSE) and the SI pin to prevent the malfunction due to such noise. The time constant of RC low-pass filter
should be equivalent to the spike width (t RLF CLF) as a rough guide (Fig. 7). Or the insertion is effective with a
bypass capacitor near the source pin of the MOSFET, too.
Spike Noise
Filter
V+
Current Limit
Detection
VIPK
CLF
VIN
RSENSE
SI
RLF
t
Pulse by Pulse
Current Waveform example
CIN3
Bypass
Capacitorr
OUT
RG
Fig. 7. Current Waveform and Filter Circuit
Ver.2016-03-22
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NJW4161
NJW4161Application Manual
Technical Information
Description of Block Features (Continued)
Thermal Shutdown Function (TSD)
When Junction temperature of the NJW4161 exceeds the 160°C*, internal thermal shutdown circuit function stops
SW function. When junction temperature decreases to 145°C* or less, SW operation returns with soft start operation.
The purpose of this function is to prevent malfunctioning of IC at the high junction temperature. Therefore it is not
something that urges positive use. You should make sure to operate within the junction temperature range rated
(150 C). (* Design value)
Standby Function
To set the NJW4161 to standby status, insert MOSFET or others between the timing resistor RT and GND in order
to set high impedance. (Fig. 8.)
It is necessary to make RT pin current less than IRT_STB=5 A to a standby mode, therefore choose MOSFET of the
small leak current.
If large capacitor is connected to RT pin when using a standby function, it becomes impossible to shift to an
operating state from standby. When connect a bypass capacitor to RT pin, use capacitor of 100 pF or less.
Moreover, when changing from operation to a standby state, ON time may occur about 2 s by circuit delay.
Enable
Control
OSC
RT
RT
Enable
Control
Signal
RT State
ON: Connect timing resistor to GND
OFF (Stand-by): RT pin open
RONOFF
Fig. 8. When using a standby function
- 16 -
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Application Information
Inductors
Current
Peak Current Ipk
Large currents flow into inductor, therefore you
must provide current capacity that does not
Inductor
(1) Continuous
saturate.
Current IL
Conduction Mode
Reducing L, the size of the inductor can be
smaller. However, peak current increases and
(2) Critical Mode
adversely affecting efficiency.
(3) Discontinuous
0
On the other hand, increasing L, peak current
Conduction Mode
can be reduced at switching time. Therefore
Frequency
tON
tOFF
fOSC
conversion efficiency improves, and output ripple
voltage reduces. Above a certain level, increasing
inductance windings increases loss (copper loss)
Fig. 9. Inductor Current State Transition
due to the resistor element.
Ideally, the value of L is set so that inductance current is in continuous conduction mode. However, as the load
current decreases, the current waveform changes from (1) CCM: Continuous Conduction Mode (2) Critical Mode
(3) DCM: Discontinuous Conduction Mode (Fig. 9.).
In discontinuous mode, peak current increases with respect to output current, and conversion efficiency tend to
decrease. Depending on the situation, increase L to widen the load current area to maintain continuous mode.
Catch Diode
When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output
capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's
forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a
low forward saturation voltage, is ideal.
An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when
the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such
factors as noise generation.
Switching Element
You should use a switching element (Pch MOSFET) that is specified for use as a switch. And select sufficiently low
RON MOSFET at less than VGS=10V because the NJW4161 OUT pin voltage is clamped V+-10V (typ.).
However, when the supply voltage of the NJW4161 is low, the OUT pin voltage becomes low. You should select a
suitable MOSFET according to the supply voltage specification. (Ref. Driver section)
Large gate capacitance is a source of decreased efficiency. That is charge and discharge from gate capacitance
delays switching rise and fall time, generating switching loss.
The spike noise might occur at the time of charge/discharge of gate by the parasitic inductance element. You
should insert resistance between the OUT pin and the gate and limit the current for gate protection when gate
capacitance is small. However, it should be noted that the efficiency might decrease because the shape of waves
may become duller when resistance is too large. The last fine-tuning should be done on the actual device and
equipment.
Ver.2016-03-22
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NJW4161
NJW4161Application Manual
Technical Information
Application Information (Continued)
Input Capacitor
Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply
impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW4161
performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as
possible.
Output Capacitor
An output capacitor stores power from the inductor, and stabilizes voltage provided to the output.
When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple
current, and breakdown voltage.
Also, the ambient temperature affects capacitors, decreasing capacitance and increasing ESR (at low
temperature), and decreasing lifetime (at high temperature). Concerning capacitor rating, it is advisable to allow
sufficient margin.
Output capacitor ESR characteristics have a major influence on output ripple noise. A capacitor with low ESR can
further reduce ripple voltage. Be sure to note the following points; when ceramic capacitor is used, the capacitance
value decreases with DC voltage applied to the capacitor.
- 18 -
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Application Information (Continued)
Board Layout
In the switching regulator application, because the current flow corresponds to the oscillating frequency, the
substrate (PCB) layout becomes an important.
You should attempt the transition voltage decrease by making a current loop area minimize as much as possible.
Therefore, you should make a current flowing line thick and short as much as possible. Fig. 10. shows a current loop
at step-down converter.
SW
VIN
CIN
L
SW
COUT
SBD
VIN
CIN
L
COUT
SBD
NJW4161
NJW4161
(a) Buck Converter SW ON
(b) Buck Converter SW OFF
Fig. 10. Current Loop at Buck Converter
Concerning the GND line, it is preferred to separate the power system and the signal system, and use single
ground point.
The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has
high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance.
Fig. 11. shows example of wiring at buck converter. Fig. 12 shows the PCB layout example.
SW
VIN
CIN
L
VOUT
SBD
COUT
RL
OUT
(Bypass Capacitor)
V+
RFB
CFB
NJW4161
INRT
RT
R2
GND
Separate Digital(Signal)
GND from Power GND
R1
To avoid the influence of the voltage
drop, the output voltage should be
detected near the load.
Because IN- pin is high impedance, the
voltage detection resistance: R1/R2 is
put as much as possible near IC(IN-).
Fig. 11. Board Layout at Buck Converter
Ver.2016-03-22
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NJW4161
NJW4161Application Manual
Technical Information
Application Information (Continued)
Feed back signal
CFB
RFB
R2
RNF
CNF
RT
R1
Signal GND Area
CREGH
CIN2
IC
CLF
RG
RLF
VIN
RSENSE
FET
L
VOUT
CSENSE
CIN1
SBD
GND IN
COUT
GNDOUT
Power GND Area
Connect Signal GND line and Power GND line on backside pattern
Fig. 12. Layout Example (top view)
- 20 -
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Calculation of Package Power
You should consider derating power consumption under using high ambient temperature.
Moreover, you should consider the power consumption that occurs in order to drive the switching element.
Supply Voltage:
Quiescent Current:
Oscillating Frequency:
Gate charge amount:
V+
IDD
fOSC
Qg
The gate of MOSFET has the character of high impedance. The power consumption increases by quickening the
switching frequency due to charge and discharge the gate capacitance. Power consumption: PD is calculated as
follows.
PD = (V+ IDD) + (V+ Qg fOSC) [W]
You should consider temperature derating to the calculated power consumption: PD.
You should design power consumption in rated range referring to the power dissipation vs. ambient temperature
characteristics.
Ver.2016-03-22
- 21 -
NJW4161
NJW4161Application Manual
Technical Information
Application Design Examples
Step-Down Application Circuit
Input Voltage:
VIN=12V
Output Voltage:
VOUT=5V
Output Current:
IOUT=3A
Oscillation frequency: fosc=345kHz
VIN=12V
RSENSE1 30mW
CIN1
10mF/50V,
2pcs.
CSENSE
1mF/50V
RLF1
22W
CLF1
2,200pF
RG 0W
CREGH
0.1mF
CIN2
0.1mF/50V
4
3
2
1
V+
OUT
SI
REGH
NJW4161
IN-
FB
RT
GND
5
6
7
8
Q1
VOUT=5V
L1 10mH/6.7A
CFB
180pF
SBD
COUT
47mF/16V
RFB
1kW
R2
68kW
R1
13kW
RT 5.6kW
RNF
6.8kW
Reference
IC1
1
NJW4161R
Q1
L1
SBD
CIN1
CIN2
COUT
CREGH
CNF1
CFB
CLF1
CSENSE
R1
R2
RNF
RFB
RG
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
FDD4243
CLF12555T-100M
DE5SC4M
UMK325BJ106MM-P
0.1 F
GRM32EB31C476KE15L
0.1 F
6,800pF
180pF
2,200pF
UMK212BJ105KG-T
13k
68k
6.8k
1k
0 (Short)
Description
MOSFET Drive Switching Regulator
for Buck Converter IC
Pch MOSFET 40V, 14A
Inductor 10 H, 6.7A
Schottky Diode 40V, 5A
Ceramic Capacitor 3225 10 F, 50V, X5R
Ceramic Capacitor 1608 0.1 F, 50V, B
Ceramic Capacitor 3225 47 F, 16V, B
Ceramic Capacitor 1608 0.1 F, 25V, B
Ceramic Capacitor 1608 6,800pF, 50V, B
Ceramic Capacitor 1608 180pF, 50V, CH
Ceramic Capacitor 1608 2,200pF, 50V, B
Ceramic Capacitor 2012 1 F, 50V, B
Resistor 1608 13k , 1%, 0.1W
Resistor 1608 68k , 1%, 0.1W
Resistor 1608 6.8k , 5%, 0.1W
Resistor 1608 1k , 5%, 0.1W
Resistor 1608 0 , 0.1W
RSENSE1
1
LPS1R030FE
Current Sense Resistor 30m , ±1%, 1W
RLF1
RT
1
1
22
5.6k
Resistor 1608 22 , ±5%, 0.1W
Resistor 1608 5.6k , 1%, 0.1W
- 22 -
Qty.
CNF1
6,800pF
Part Number
Manufacturer
New JRC
Fairchild
TDK
Shindengen
Taiyo yuden
Std.
Murata
Std.
Std.
Std.
Std.
Taiyo yuden
Std.
Std.
Std.
Std.
Std.
Hokuriku
Electric
Industry
Std.
Std.
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Application Design Examples (Continued)
Setting Oscillation Frequency
From the Oscillation frequency vs. Timing Resistor
Characteristic, RT=5.6 [k ], t=2.9 [ s] at fosc=345kHz.
Peak Current: Ipk
Inductance
Current: IL
Step-down converter duty ratio is shown with the following
equation:
Duty
VOUT VF
VIN
100
5 0.4
100
12
Output Current: IOUT
45 %
0
Period: t
Frequency: fOSC=1/t
Therefore, tON=1.31 [ s], tOFF=1.59 [ s]
tON
tOFF
Fig. 13. Inductor Current Waveform
Selecting Inductance
IL is Inductance ripple current. When to IL= output current 30%:
IL = 0.3 IOUT = 0.3 3 = 0.9 [A]
This obtains inductance L. VDS_RON is drop voltage by MOSFET on resistance.
L
VIN
VDS
RON
VOUT
IL
t ON
12 0.2 5
1.31
0.9
10 [ H]
Inductance L is a theoretical value. The optimum value varies according such factors as application specifications
and components. Fine-tuning should be done on the actual device.
This obtains the peak current Ipk at switching time.
IL
0 .9
Ipk I OUT
0 .3
3.45 [ A ]
2
2
The current that flows into the inductance provides sufficient margin for peak current at switching time.
In this application circuit example, use L=10 H/6.7A.
Setting Over Current Detection
In this application circuit example, current limitation value: ILIMIT is set to Ipk=4A.
ILIMIT = VIPK / RSC = 120mV / 30m =4 [A]
The limit value increases slightly according to the response time between the overcurrent detection with the SI pin
and the OUT pin outputs stop signal.
ILIMIT _ DELAY
Ver.2016-03-22
ILIMIT
VIN
L
t DELAY
4.0
12
10
80n
4.1 [ A ]
- 23 -
NJW4161
NJW4161Application Manual
Technical Information
Application Design Examples (Continued)
Selecting the Input Capacitor
The input capacitor is an important component to decrease power line impedance. The input capacitor selection
should be determined by the input ripple current and the maximum input voltage of the capacitor rather than its
capacitance value.
The effective input current can be expressed by the following formula:
IRMS
IOUT
VOUT
VIN
VOUT
[A]
VIN
In the above formula, the maximum current is estimated when VIN = 2 VOUT, and the result in this case is:
IRMS = IOUT (MAX) 2.
When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has
adequate margin.
Selecting the Output Capacitor
The output capacitor is an important component that determines output ripple noise. Equivalent Series Resistance
(ESR), ripple current and capacitor breakdown voltage are important in determining the output capacitor.
The output ripple noise can be expressed by the following formula:
Vripple (p
IL
p)
ESR
1
8 f OSC
C OUT
[V]
When selecting output capacitance, select a capacitor that allows for sufficient ripple current.
The effective ripple current that flows in a capacitor (Irms) is calculated by the following equation:
Irms
IL
0.9
2 3
2 3
260 [mArms ]
Considering sufficient margin, use a capacitor that fulfills the above spec.
In this application circuit example, use COUT=47 F/16V.
Setting Output Voltage
The output voltage VOUT is determined by the relative resistances of R1, R2. The current that flows in R1, R2 must
be a value that can ignore the bias current that flows in ER AMP.
VOUT
- 24 -
R2
1
R1
VB
68k
13k
1
0.8
4.98 [ V ]
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
Compensation design example
A switching regulator requires a feedback circuit for stable output. Because
the frequency characteristics of the application change according to an
inductance, an output capacitor and so on, the ideal compensation constant
is to keep the necessary phase for stable operation and to obtain the
maximum band.
The tuning with an actual application is important to determine the
compensation constants. Therefore, to finally select the constants with
measurement in consideration of the application specifications.
Pole
Gain
-20dB/dec
Phase
0
-45
-90
fP/10
fP
10fP
Frequency
Pole
Feedback and Stability
Basically, the feedback loop should be designed as the open loop phase
shift at the point where the loop gain is 0 dB is less than -180 . Furthermore,
the loop characteristics should have margin in consideration of ringing and
oscillation tolerance caused by load fluctuations. The feedback circuit of the
NJW4161 can be arbitrarily be designed. Therefore to enable optimizing the
poles and zeros which are important parameters for loop compensation.
+20dB/dec
Gain
Zero
Phase
+90
+45
0
fZ/10
The characteristics of the poles and zeros are shown in Fig. 14.
Poles: The gain has a slope of -20 dB/dec, and the phase shifts -90 .
Zeros: The gain has a slope of +20 dB/dec, and the phase shift +90 .
fZ
10fZ
Frequency
Zero
Fig. 14. Characteristics of Pole and Zero
If the number of factors constituting poles is defined as “n”, the change in the gain and phase will be “n”-fold. This
also applies to zeros as well. The poles and zeros are in a reciprocal relationship, so if there is one factor for each
pole and zero, they will cancel each other.
Configuration of the compensation circuit
VIN
+
PV
LC Gain
Buffer
SW
L
VOUT
RESR
CFB
R2
COUT
ER AMP
PWM
CFB
Vref
=0.8V
RFB
IN-
FB
R1
CNF
RNF
C1(option)
Fig. 15. Compensation Circuit Configuration
Ver.2016-03-22
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NJW4161
NJW4161Application Manual
Technical Information
Compensation Design (Continued)
Poles and zeros due to the inductance and output capacitor
Double poles fP(LC) are generated by the inductance and output capacitor. Simultaneously, single zeros fZ(ESR) are
generated by the output capacitor and ESR. Each pole and zero is expressed by the following formula:
f Z(ESR )
1
fP(LC)
2 C OUTR ESR
1
2
LC OUT
If the ESR of the output capacitor is high, fZ(ESR) will be located in the vicinity of fP(LC). In such application, the zero
fZ(ESR) compensates the double poles fP(LC) and it has tendency for stability accordingly.
However, if the ESR of the output capacitor is low, fZ(ESR) shifts to the high frequency and the phase is shifted -180
by fP(LC). The NJW4161 compensation circuit can compensate by using zeros of fZ1 and fZ2.
Gain (dB)
Poles and zeros due to error amplifier
The single poles and zeros generated by the error amplifier
LC Gain
are obtained using the following formula.
Zero
Pole
1
fP1
1
f Z1
R1 R2
Loop
2 CNF A V
2 CNFRNF
Gain
R1 R2
(Av: Amplifier Open Loop Gain=80dB)
fZ 2
1
2 CFBR2
Double
pole
-40dB/dec
0dB frequency
* Gain increase
due to Zero
1
fP 2
2 C FB R FB
fP 3
R1 R2
R1 R2
1
2 C1 R NF
-20dB/dec
Compensation
Gain
(Option)
fZ1 and fZ2 are located on both sides of fP(LC).
Because the inductance and the output capacitor vary, they are
each set using the following as a rough guide:
fP(LC) 0.5-fold to 0.9-fold
fP(LC) 1.1-fold to 2.0-fold
fP1
fZ1 or fZ2
fP(LC)
fP2 fP3 fZ(ESR)
Fig16. Loop Gain examples
There is also a method in which fZ1 and fZ2 are located at positions lower than fP(LC). Because there is a tendency to
increase the phase shift and the gain becomes high, it can be expected that the response will improve.
However, there is a tendency for the phase margin to become insufficient, so care is necessary.
The fP1 creates poles in the low frequency band due to the Miller effect of the error amplifier. The stability becomes
better as fP1 becomes lower. On the other hand, the frequency characteristics do not improve, so the response is
adversely affected. The fP1 is set a frequency gain of fP(LC) is 20dB as a rough guide.
If the open loop gain of the error amplifier is made 80 dB, design is carried out using fP1 < fP(LC) 103 (= 60 dB) as a
rough guide.
Above several 100 kHz, various poles are generated, so the upper limit of the frequency range where the loop
gain is 0 dB is set to fifth (1/5) to tenth (1/10) of oscillation frequency. The fZ(ESR) in the high frequency region
sometimes causes a loop gain to be generated (See Fig.16 Loop Gain “). Using fP2 and fP3, perform adjustment with
the NJW4161 in an actual application, so as to adequately reduce the loop gain in the high frequency region.
- 26 -
Ver.2016-03-22
NJW4161 ApplicationNJW4161
Manual
Technical Information
■Application Characteristics
● PWM control : A version, B version
Efficiency vs. Output Current
(PWM ver., VOUT=5V, Ta=25ºC)
100
5.2
fOSC=345kHz
L=10 H
90
Output Voltage VOUT (V)
(%)
VIN=6V
VIN=18V
Efficiency
60
50
fOSC=345kHz
L=10 H
5.15
80
70
Output Voltage vs. Output Current
(PWM ver., Ta=25ºC)
VIN=12V
40
30
20
5.1
VIN=6V, 12V, 18V
5.05
5
4.95
4.9
4.85
10
0
4.8
1
10
100
1000
Output Current IOUT (mA)
10000
1
10
100
1000
Output Current IOUT (mA)
10000
● PWM/PFM Control : C version
Efficiency vs. Output Curent
(PWM/PFM ver., VOUT=5V, Ta=25ºC)
100
5.2
fOSC=345kHz
L=10 H
90
Output Voltage VOUT (V)
(%)
VIN=6V
VIN=18V
Efficiency
60
50
fOSC=345kHz
L=10 H
5.15
80
70
Output Voltage vs. Output Current
(PWM/PFM ver., Ta=25ºC)
VIN=12V
40
30
20
5.1
5.05
VIN=6V, 12V, 18V
5
4.95
4.9
4.85
10
0
4.8
1
Ver.2016-03-22
10
100
1000
Output Current IOUT (mA)
10000
1
10
100
1000
Output Current IOUT (mA)
10000
- 27 -
NJW4161
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 28 -
Ver.2016-03-22
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