CF5072BA 155MHz VCXO Module IC
OVERVIEW
The CF5072BA is 155MHz VCXO IC. It incorporates a 155.52MHz fundamental frequency oscillator circuit and a differential LVPECL output circuit on a single chip. The oscillator circuit features characteristics optimized for VCXO operation, and includes a varicap connection pin. The CF5072BA can be configured with few external components, making them ideal as miniature VCXO modules.
FEATURES
I I I I
3.0 to 3.6V operating supply voltage range 70MHz to 200MHz oscillator frequency range Differential LVPECL output 50 ± 5% output duty (measured at the output crossing point)
I
I I
Output enable function High impedance output when OE = LOW (oscillator continues running) −40 to 85°C operating temperature range Chip form (CF5072BA)
BLOCK DIAGRAM
VDD2
VDD1
RP LS
X'tal
XIN XC 100pF Differential Converter C2 RS VC C1 Pre-buffer ECL
OUTN
CVC XR RVC
OUT
Oscillator block equivalent circuit VSS1
OE VSS2
ESD sensitive device: The XR pin is not equipped with a protection circuit. Accordingly, its electrostatic withstand voltage is significantly lower than that of the other pins. ESD breakdown prevention handling precautions are strongly recommended.
ORDERING INFORMATION
Device CF5072BA−1 Package Chip form
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CF5072BA
FUNCTIONAL DESCRIPTION
Oscillator Equivalent Circuit
The oscillator can be represented by the equivalent circuit shown below. The crystal unit is connected to XIN, and the other terminal is connected to the LS and RP network. A varicap is added with cathode connected to XR, and anode connected to XC. The control voltage is applied to the VC pin, with high-resistance element connected between VC and XR built-in.
RP LS
X'tal
XIN XC 100pF To differential converter C2 RS VC C1
CVC XR RVC
VC input
VSS1
Note. RP is a damping resistor to prevent parasitic oscillation due the combined effects of the external inductor (expander coil) and varicap capacitance/internal capacitance. It is recommended that RP be connected in parallel with LS.
Oscillator internal capacitors (design value)
Internal capacitance [pF] (design value) Version C1 CF5072BA 11.2 C2 14.4
Selecting external constants The LS and RP values should be selected such that both (a) the resonance point in the loop formed by LS and C0, CL, CVC is higher than the crystal oscillator frequency, and (b) the resonance point does not satisfy the oscillation condition. (C0 is the crystal shunt capacitance, CL is the oscillator equivalent circuit capacitance, and CVC is the varicap capacitance.) In the oscillator circuit, if the crystal capacitance C0 is 2.85pF, the varicap (CVC) is a HVC350B (Renesas), and the oscillator frequency is 155.52MHz, then values in the order LS = 220nH, RP = 2.2kΩ or LS = 180nH, RP = 1.8kΩ will satisfy the conditions above. The optimal values for LS and RP will vary with crystal characteristics, oscillator frequency, and varicap diode, thus the values selected should be thoroughly evaluated.
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CF5072BA
Output Circuit
The output is enabled/disabled using the OE pin. Outputs are high impedance when disabled. The OE pin logic is shown in the following table.
OE HIGH or open LOW OUT CLK output High impedance OUTN CLK output High impedance
OE = HIGH: ON OE = LOW: OFF From pre-buffer
VDD1
OUTN OE = HIGH: OFF OE = LOW: ON OUT
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CF5072BA
PAD LAYOUT
(Unit: µm)
VDD2 XIN XC Y NC XR VC VSS1 (0,0) X 9 10 11 12 13 1 8 7 6 DB5072BA 5 4 2 TEST 3 (1820,1000) VDD1 OUTN OUT VSS2 OE
Chip size: 1.82 × 1.00mm Chip thickness: 300 ± 30µm Pad size: 110 × 100µm (TEST pin only = 90 × 90µm) Chip base: VSS potential
PAD DESCRIPTION AND DIMENSIONS
Pad dimensions [µm] Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Name VSS1 TEST OE VSS2 OUT OUTN VDD1 VDD2 XIN XC NC XR1 VC I/O – I I – O O – – I I – I I Oscillator ground IC test pin (leave open circuit for normal operation) Output enable, with pull-up resistor built-in Ground Differential PECL non-inverting output (true) Differential PECL inverting output (complementary) ECL buffer supply Supply Crystal unit connection Varicap anode connection No connection Varicap cathode connection and inductor connection Control voltage pin Function X 125 1283 1695 1695 1695 1695 1695 643 125 125 125 125 125 Y 135 160 135 268 460 673 865 865 828 708 495 375 255 X 110 90 110 110 110 110 110 100 110 110 110 110 110 Y 100 90 100 100 100 100 100 110 100 100 100 100 100 Pad size [µm]
1. The XR pin electrostatic withstand voltage is weaker than the other pins. The electrostatic withstand voltage of pins, excluding XR, is the same as that for existing NPC devices.
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CF5072BA
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage range Input voltage range Storage temperature range Symbol VDD VIN TSTG Conditions Rating VSS − 0.5 to VSS + 7.0 VSS − 0.5 to VDD + 0.5 −65 to 150 Unit V V °C
RECOMMENDED OPERATING CONDITIONS
Rating Parameter Supply voltage Operating temperature Output load Output frequency Symbol VDD TOPR RL fOUT Terminated to VDD − 2V Conditions Min 3.0 −40 – 70 Typ – – 50 – Max 3.6 85 – 200 V °C Ω MHz Unit
ELECTRICAL CHARACTERISTICS
DC Characteristics
Recommended operating conditions apply unless otherwise noted
Rating Parameter Symbol Conditions Min Current consumption IDD VOH Measurement circuit 2, VDD = 3.3V, OE = OPEN OUT/OUTN LOW-level output voltage OE HIGH-level input voltage OE LOW-level input voltage OE LOW-level input current Input impedance VC resistance Pull-down resistance VOL VIH VIL IIL ZIN RVC RS Measurement circuit 3 Measurement circuit 3 Measurement circuit 4, VIL = 0V Measurement circuit 5, measured between supply and VC Measurement circuit 6, measured between VC and XR Measurement circuit 7, measured between VSS and XC Measurement circuit 1, output terminated to VDD − 2V, OE = OPEN Ta = 0 to 85°C Ta = −40°C Ta = 0 to 85°C Ta = −40°C – 2.275 2.215 1.490 1.470 0.7VCC – – 10 100 10 Typ 50 2.350 2.295 1.600 1.605 – – – – 150 20 Max 88 2.420 2.420 1.680 1.745 – 0.3VCC −20 – 200 40 mA V V V V V V µA MΩ kΩ kΩ Unit
OUT/OUTN HIGH-level output voltage
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CF5072BA
AC Characteristics
Recommended operating conditions apply unless otherwise noted
Rating Parameter Symbol Conditions Min Output duty cycle 1 Output duty cycle 2 Output swing Output rise time Output fall time Output enable delay time Output disable delay time Duty1 Duty2 VOpp tr tf tOE tOD Measurement circuit 1, measured at output crossing point, Ta = 25°C, VDD = 3.3V Measurement circuit 1, measured at 50% output swing, Ta = 25°C, VDD = 3.3V Measurement circuit 1, peak-to-peak of output waveform Measurement circuit 1, output swing 20% to 80% Measurement circuit 1, output swing 80% to 20% Measurement circuit 3, Ta = 25°C Measurement circuit 3, Ta = 25°C 45 45 0.4 – – – – Typ 50 50 – 0.5 0.5 – – Max 55 55 – 1 1 200 200 % % V ns ns ns ns Unit
VDD
tr
OUTN OUT
tf
80% 20%
tW tPER
DUTY1 = (tW/tPER)
VDD – 2V
VSS
100
Figure 1. PECL output waveform
tOD
OE VDD/2
tOE
VDD
GND VDD OUT OUTN
LOW-level (High impedance)
GND
Figure 2. OE timing waveform (Differential LVPECL)
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CF5072BA
MEASUREMENT CIRCUITS
Measurement Circuit 1
Parameters: IDD, Duty1, Duty2, VOpp, tr, tf
Measurement Circuit 4
Parameter: IIL
A IDD
VDD1 RP VDD1 XIN LS XC XR VC VSS1 VSS2 OUTN IIL OUT 50Ω VDD−2V VDD2 50Ω OE VDD2
A
VSS1 VSS2
Measurement Circuit 5 Measurement Circuit 2
Parameters: VOH, VOL
VDD1 I1 1kΩ VDD1 XIN OUTN TEST OUT VSS1 VSS2 50Ω VDD−2V VDD2 50Ω ZIN = VDD/I1 VSS1 VSS2 VDD2
Parameter: ZIN
A
VC
VV
VOH,VOL
Measurement Circuit 6
Parameter: RVC
OUT is tied LOW (VOL) OUTN is tied HIGH (VOH) When XOUT = LOW: OUT is tied HIGH (VOH) OUTN is tied LOW (VOL)
When XIN = HIGH:
I2
VDD1 VC
VDD2
Measurement Circuit 3
Parameters: VIH, VIL, tOE, tOD
A
XR V2 V VSS1 RVC = V2/I2 VSS2
RP
VDD1 XIN
VDD2 50Ω OUTN
LS
XC XR OE
Measurement Circuit 7
50Ω
OUT VDD−2V
Parameter: RS
V
VIH,VIL
VSS1
VSS2
VDD1 I3
VDD2
VIH: output state changes VSS → VDD VIL: output state changes VDD → VSS OE: disable function
A
V3 V
XC
VSS1 RS = V3/I3
VSS2
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CF5072BA
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15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC0212CE 2006.04
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