CF5762AB0

CF5762AB0 Analog Chime Clock CMOS IC OVERVIEW The CF5762AB0 is an analog chime clock CMOS IC that uses a 4.194304MHz crystal oscillator source. It can play a melody and hour chime when triggered by an hourly signal. It generates output sound using dual pitch synthesis (DPS) to produce high-tone quality melodies and chime signals. FEATURES I I I I I I I 4.2MHz fundamental oscillator frequency 1.5V and 3.0V supply voltages (VDD − VSS) 8Hz sweep Melody switching function (SEL1 and SEL2) • choice of 4 melodies played hourly Chime output using time detection circuit Dual pitch synthesis (DPS) sound generator BTL-configuration melody output circuit PAD LAYOUT (Unit: mm) lim RESET N.C. XTN XT N.C. N.C. N.C. VSS NPC MT S4 pre (0,0) SP VOL SPN MSBN ina ry I I I I I I 2 simultaneous output pitches Busy (play) signal control output (ATN) Melody stop when dark (CDS and CO4N) • melody stop using an external CdS element Melody stop at night (AMI and PMI) Reset function Chattering elimination function N.C. S3 N.C. S2 S1 N.C. O1 O2 (3.44, 2.58) VDD PMI AMI SEL2 HA5762 SEL1 WSEL MSB ATN CO4N CDS Chip size: 3.44 × 2.58mm Chip thickness: 300 ± 30µm NIPPON PRECISION CIRCUITS INC.—1 CF5762AB0 PAD DESCRIPTION/DIMENSIONS Dimensions (µm) Name RESET NC XTN XT NC NC NC VSS VOL SP SPN MSBN MSB ATN CO4N CDS WSEL SEL1 SEL2 AMI PMI VDD O2 O1 NC S1 S2 Reset input No connection (leave open circuit) Oscillator output Oscillator input No connection (leave open circuit) No connection (leave open circuit) No connection (leave open circuit) 0V supply Volume adjust input Audio output (9-bit current output D/A) Audio output (9-bit current output D/A) Audio output (sign bit) Audio output (sign bit) Control signal output Melody stop when dark (CdS) output Melody stop when dark (CdS) input Waveform select input Melody select input 1 Melody select input 2 Description Input/output X Input with pull-down 235 234 235 Y 2283 2049 1786 1553 lim Melody stop at night input Melody stop at night input 1.5V supply (IC substrate) Clock movement motor drive output 2 Clock movement motor drive output 1 No connection (leave open circuit) Time detect input 1 Time detect input 2 pre NC S3 No connection (leave open circuit) Time detect input 3 NC S4 No connection (leave open circuit) Time detect input 4 MT Hourly signal input ina ry 235 234 235 235 235 Resistance connection input 235 P-channel output 381 P-channel output CMOS output 908 1260 CMOS output 1780 CMOS output 2172 CMOS output 2488 Input with pull-up when inactive Input with pull-down 2808 3205 Input with pull-down Input with pull-down 3205 3205 3205 3205 3205 3211 3020 2768 2409 2174 1815 Input with pull-down 1540 1181 Input with pull-down Input with pull-down 906 548 Input with pull-down Input with pull-down CMOS output CMOS output Input with pull-down Input with pull-down 1289 1017 829 618 430 185 185 185 185 185 185 185 331 565 923 1156 1514 1725 2395 2395 2395 2395 2395 2395 2395 2395 2395 2395 NIPPON PRECISION CIRCUITS INC.—2 CF5762AB0 SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage range Input voltage range Storage temperature range Operating temperature range Symbol VDD − VSS VIN Tstg Topr Condition Rating −0.3 to 5.0 VSS to VDD −65 to 150 −30 to 80 Unit V V °C °C Electrical Characteristics VDD = 1.5V, VSS = 0V, Ta = 25°C, f0 = 4.194304MHz, CI = 150Ω, CG = CD = 15pF unless otherwise noted Rating typ – Parameter Minimum operating voltage1 Maximum operating voltage1 Operating current consumption (non-play mode)1 Operating current consumption (play mode)1 Oscillator start-up time1 Frequency-voltage characteristic2 Output saturation resistance3 Input current 1 (MT, RESET, WSEL, SEL1, SEL2, AMI, PMI)4 Input current 2 (S1 to S4)4 Input current 3 (CDS)4 Symbol Condition Unit V V VDD (min) VDD (max) IDD1 IDD2 t1 ina ry min – max 1.2 – fOSC ≈ f0 fOSC ≈ f0 3.6 – – – fOSC ≈ f0, outputs open fOSC ≈ f0, outputs open fOSC ≈ f0, VDD = 1.2V fOSC (1.5V) 20 60 – 50 150 5.0 – – – 2.0 Rout IIH1 IIH2 IIL1 VDD = 1.2V, RL = 400Ω VDD = 1.5V, VIH = 1.5V VDD = 1.5V, VIH = 1.5V VDD = 1.5V, VIL = 0V VDD = 1.2V, VOL = 0.2V VDD = 1.2V, VOH = 0.2V VDD = 1.2V, VOL = 0.2V VDD = 1.2V, VOH = 1.0V VDD = 1.2V, VOL = 0.6V – 70 100 2.0 4.0 4.0 1000 1000 1000 200 – – 1.3 50 36 36 0.4 1.0 1.0 200 200 200 50 1.5 1.5 0.7 40 5 5 1.0 2.0 2.0 500 500 500 100 – – 1.0 45 15 15 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOH4 VDD = 1.2V, VOH = 0.6V VDD = 1.2V, VOH = 0.6V VDD = 1.5V CG CD µA µA s ε1, ε2 ppm Ω lim RVOL0 µA µA µA µA µA µA µA mA mA mA kΩ pF pF Output current 1 (CO4N)5 Output current 2 (ATN)5 Output current 3 (MSB, MSBN)5 Output current 4 (SP, SPN)5 Volume 0 resistance6 pre External capacitance (XT) External capacitance (XTN) 1. Measured using “Measurement Circuit” with fOSC ≈ f0 ± 30ppm, functions auto-start normally. 2. ε1 = ε (1.2V) = |[f (1.2V) − f (1.5V)] / f (1.5V)| ε2 = ε (1.7V) = |[f (1.7V) − f (1.5V)] / f (1.5V)| 3. Load resistor RL connected between outputs O1 and O2. If VOUT is the voltage wave maximum value across the resistor, then Rout is given by: Rout = (VDD / VOUT − 1) × RL = (1.2(V) / VOUT − 1) × 400(Ω) 4. The IIH and IIL ratings are for each input when short circuited to VDD or VSS. IIL1 is the current when CDS is inactive (when CO4N output is HIGH). NIPPON PRECISION CIRCUITS INC.—3 CF5762AB0 5. Output current (IOL, IOH) measured using the following circuit. IOH4 is measured with a 10kΩ resistor connected to VOL. VDD VDD Measurement pin IOL A IOH 6. Volume 0 resistance is the resistance connected between VOL and VSS for which the SP and SPN output current is less than 100nA. Measurement Circuit RL S1 S2 WSEL SEL2 SEL1 VDD AMI PMI O1 O2 Parallel 1.5V lim S3 S4 XTN MT RESET Oscillator CD XT CG VOL VSS pre f0 = 4.194304MHz, CG = 15pF, CD = 15pF, RL = 400Ω, VOL = 50kΩ ina ry VSS 10kΩ VOH VOL CDS CO4N ATN MSB MSBN SPN SP VOL VOL NIPPON PRECISION CIRCUITS INC.—4 CF5762AB0 FUNCTIONAL DESCRIPTION Motor Output Sweep movement frequency: 8Hz The pulse cycle (Tcy) and the pulsewidth (Tpw) correspond to 1/16 Sec (= 62.5ms). Tpw O1 Tcy O2 Figure 1. Motor pulse output Reset Clock movement reset For step clock movement, the seconds are stopped. When reset is released, the next pulse is output on the opposing output pin to that immediately before the reset was applied. The time delay until the pulse output after reset is released is 1 + 0.0625 seconds. –0 For sweep clock movement, both outputs O1 and O2 are held HIGH during reset. pre NIPPON PRECISION CIRCUITS INC.—5 lim All functions are reset when RESET goes HIGH. The reset is released when RESET goes LOW or open circuit (RESET has a built-in pull-down resistor). ina ry VDD VSS Tcy VDD VSS Tpw Melody reset If a reset occurs during melody or chime output, the output stops immediately. During reset, the MT is valid when it is input. When the MT pin is HIGH, the reset signal is valid if input. Time reset During the timing between reset and the hourly signal input when the melody select pins (SEL1, SEL2) are used to monitor, chime monitoring is inactive while melody monitoring is active. CF5762AB0 Chattering Elimination Input S1 to S4, CDS, WSEL MT, RESET AMI, PMI SEL1, SEL2 No chattering elimination function If the input goes HIGH and continues for 2 or more 16Hz cycles, then the input is recognized, otherwise it is ignored. If the input goes LOW, it is sampled at 16Hz. If the input changes state and continues for 2 or more 16Hz cycles, then the input is recognized, otherwise it is ignored. The inputs are sampled periodically at 16Hz. If either SEL1 or SEL2 changes state, the state is held for 62.5ms and then the state of both SEL1 and SEL2 are read. If either SEL1 or SEL2 changes state during this interval, a further interval of 62.5ms is added before reading the input states (see figure 2). Description 16Hz SEL1 SEL2 Read hold pulse Status read clock 62.5ms 62.5ms Power-ON Initialization When power is applied, the following reset functions take place. I I pre I Clock movement motor outputs (O1, O2) After the oscillator starts, each output is activated with O1 being LOW and O2 being HIGH. Reset (RESET) After power is applied, a 62.5ms reset pulse is output. If, however, RESET is HIGH when power is applied, the corresponding reset state is recognized as-is. Melody trigger (MT) If MT is HIGH when power is applied, melody output stops. Melody output starts when MT goes LOW and then goes HIGH again. lim I I I Figure 2. SEL1, SEL2 read timing ina ry 62.5ms 62.5ms 62.5ms Time information (S1 to S4) The time data is reset to a zero state not representing any hour in the range 1 to 12 o’clock, and the inputs are not read until the next hourly signal input. Melody switching function (SEL1, SEL2) When power is applied, the input states are reset and then immediately read in. Melody stop at night (AMI, PMI) When power is applied, the PM flag is set to LOW (AM setting) and then, immediately, the input states are read in. If at this time both AMI and PMI are HIGH, then the PM flag stays set to LOW. NIPPON PRECISION CIRCUITS INC.—6 CF5762AB0 MELODY FUNCTION DESCRIPTION Melodies There are 4 melodies stored, and which can be played hourly. Time Function The number of chimes played are determined by time detection in 12-hour mode. Melody Select Switching The melody to be played is selected by the state of SEL1 and SEL2. SEL1 and SEL2 have built-in pulldown resistors. lim Time Detection pre The time information inputs are only read when the hourly signal is input on MT. At all other times the internal data does not change, even if the time information inputs change state. The hours 1 through 12 are represented in 12-hour mode with an internal PM flag. The PM flag reverses state when the hour switches from 11 to 12, or from 12 to 11 if the time setting is being reversed to adjust to the correct time. When the S1 to S4 inputs are all HIGH, the melody output plays without chimes. These inputs determine the time detection and are read into internal registers when the hourly signal is input on MT. Other input combinations not shown are invalid. S1 to S4 have built-in pull-down resistors. ina ry SEL1 LOW SEL2 LOW HIGH LOW HIGH LOW HIGH HIGH S4 S3 LOW LOW LOW HIGH HIGH HIGH HIGH LOW LOW LOW LOW HIGH LOW HIGH S2 LOW HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH S1 HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW LOW HIGH LOW LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH LOW HIGH If the following conditions are satisfied when a HIGH-level hourly signal is input on MT, then hourly melody output occurs. The hourly melody is a combination of melody output and subsequent chime signals. MT has a built-in pull-down resistor. 1. The hourly signal turns OFF once before turning ON 2. Melody stop at night function is not set for current time interval (see “Melody Stop at Night”) 3. Melody stop when dark function is not active (see “Melody Stop when Dark”) If S1 to S4 are all HIGH (no chime), then condition number 2 is ignored. If the time information inputs change state and an hourly signal on MT is input during melody output, the output stops and then starts again under the new conditions. Melody (hourly signal) Melody 1 + chime Melody 2 + chime Melody 3 + chime Melody 4 + chime Time 1 o’clock 2 o’clock 3 o’clock 4 o’clock 5 o’clock 6 o’clock 7 o’clock 8 o’clock 9 o’clock 10 o’clock 11 o’clock 12 o’clock No change No chime NIPPON PRECISION CIRCUITS INC.—7 CF5762AB0 Melody Stop at Night The melody output can be disabled at night by the state of AMI and PMI. This function disables the melody output from 11:00PM to 5:45AM, inclusive. AMI and PMI have built-in pull-down resistors. AMI LOW LOW HIGH HIGH PMI LOW HIGH LOW HIGH Melody output Always enabled Disabled during PM hours (PM flag is HIGH) Disabled during AM hours (PM flag is LOW) Always disabled Melody Stop when Dark When a CdS element and resistor is connected between CO4N and VDD with the mid-point potential connected to CDS, the CDS input can be used to detect the brightness and to stop melody output when the surroundings become dark. CDS LOW HIGH Melody output Disabled due to darkness Enabled lim The CDS input has a built-in pull-up resistor when inactive. This pull-up is switched off when CO4N output is LOW. CO4N goes LOW in response to the hourly signal input on MT signal. The melody play output is then disable/enabled depending on the state of the CDS input. If this function is not used, the CDS input must be tied HIGH. Note that when used together with the melody stop at night function, melody output can be disabled by either function. pre Melody Play Mode The melody output plays in complete one-shot mode only. A complete one-shot melody plays through to the end of a whole melody and does not start again as long as the current melody play conditions do not ina ry CdS element VDD CDS CO4N Note that when used together with the melody stop when dark function, melody output can be disabled by either function. Figure 3. Darkness detection circuit MT etc CO4N Read clock (on rising edge) 11.719ms 15.625ms Pull-up Open Pull-down HIGH:play mode (light) CDS LOW:non-play mode (dark) Figure 4. Darkness detection timing change, even if the hourly signal is input again. However, if during melody play the melody output stops or other melody start conditions change, the current melody output may stop. NIPPON PRECISION CIRCUITS INC.—8 CF5762AB0 Dual Pitch Synthesis (DPS) Separate A and B pitches are processed by reading a single set of waveform data at slightly varying frequencies to create a chorus effect, to which an envelope functions are added, and then the resulting pitches are mixed (added) to generate output pitches. NORMAL waveform data Shift CHORUS waveform data Pitch A Pitch B Figure 5. Dual pitch synthesis block diagram Number of Simultaneous Pitches There are a maximum of 2 pitches with 2 pitch colors that can be generated simultaneously. These are Dynamic Range The range of pitches stored in Note-ROM is C3 to C6. Waveform Data pre There are 2 waveform data sets that are stored in Wave-ROM: Wave data 0 and Wave data 1. When WSEL is LOW or open circuit, pitch synthesis uses the preassigned waveform data sets. When WSEL is HIGH, all pitch synthesis uses the wave data 1 set. lim ina ry Envelope Envelope Mixer output the A and B normal melody (normal waveform) and chorus (chorus waveform) pitches. If the waveform data assignment is changed mid melody, subsequent pitch sounds generated will change because the data waveform used for pitch synthesis changes immediately in response to WSEL, even during pitch synthesis. NIPPON PRECISION CIRCUITS INC.—9 CF5762AB0 Melody Output Circuit The D/A converter is a 2-pin (SP and SPN) 9-bit Pchannel current adder which, together with MSB and MSBN outputs, is used to drive 4 external transistors VDD lim SP VOL VSS Control Signal Output A LOW-level active busy signal is output from ATN whenever a melody output is playing. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: sales@npc.co.jp NP0014AE 2000.10 pre ina ry VDD MSB MSBN SPN VOL VSS The melody output circuit employs a BTL configuration. (PNP × 2, NPN × 2) which are used to drive a speaker. In addition, the volume adjust pin (VOL) can be used to adjust the volume by connecting an external 10kΩ resistor between VOL and VSS. Figure 6. BTL output NIPPON PRECISION CIRCUITS INC.—10