NR8576BB

NR8576 Series NIPPON PRECISION CIRCUITS INC. Real-time Clock Modules OVERVIEW The NR8576 Series devices are serial-interface type real-time clock module ICs with built-in crystal oscillator elements. They feature timer counter circuits that keep track of time from the current second to the current year, automatic leap-year adjustment, and a supply voltage detect function. Also, a 32.768 kHz/1 Hz select output function is incorporated for independent hardware control. They are available in compact 14-pin SOPs (NR8576A×) and miniature 18-pin SOPs (NR8576B×). PINOUTS 14-pin SOP VSS N.C CE FSEL WR FOE N.C 1 2 3 4 5 6 7 14 13 12 11 10 9 8 FOUT N.C N.C DATA CLK VDD N.C NR8576A FEATURES s s s s s s s s Crystal oscillator element built-in for adjustmentfree use Timer counters for second, minute, hour, day, day of the week, month, and year 2.5 to 5.5 V operating voltage range 1.7 ± 0.3 V supply voltage detection threshold 1.0 µA at 3.0 V (typ) current consumption Automatic leap-year calendar adjustment 32.768 kHz and 1 Hz output selectable Package • 14-pin SOP (NR8576A×) • 18-pin SOP (NR8576B×) 18-pin SOP N.C N.C N.C N.C FOE WR FSEL CE VSS 1 18 N.C N.C N.C N.C VDD N.C CLK DATA FOUT NR8576B 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 10 SERIES CONFIGURATION D evice NR8576AA NR8576AB NR8576BA NR8576BB Package 14-pin SOP 14-pin SOP 18-pin SOP 18-pin SOP Frequency deviation 5 ± 12 ppm 5 ± 23 ppm 5 ± 12 ppm 5 ± 23 ppm NIPPON PRECISION CIRCUITS—1 NR8576 Series PACKAGE DIMENSIONS Unit: mm 14-pin SOP 18-pin SOP 10.1 0.2 0 10 11.4 0.2 0 10 7.4 0.2 7.8 0.2 5.0 5.4 0.6 0.2 1.8 0.1 3.2 0.1 0.10 0.05 1.27 0.35 0.1 1.27 0.4 0.1 BLOCK DIAGRAM VDD 32.768kHz VSS OSC FOUT FSEL FOE DATA CLK WR CE Divider Timer Counter Output Controller Voltage Detect I/O Controller Shift Register Control Circuit NIPPON PRECISION CIRCUITS—2 0.05 0.05 0.15 0.15 0.6 0.2 NR8576 Series PIN DESCRIPTION N ame V SS CE I/O – I Ground Chip enable. HIGH: Enable LOW: DATA goes high impedance; input on WR, CLK, and DATA stops; and the TM bit is cleared. FOUT output frequency select. HIGH: 1 Hz LOW: 32.768 kHz DATA input/output control switch. HIGH: Data input mode (RTC write) LOW: Data output mode (RTC read) FOUT output enable control. HIGH: The frequency selected by FSEL is output on FOUT. LOW: FOUT goes high impedance. Supply voltage. Connect a ≥ 0.1 µF capacitor between VDD and VSS. System clock input. Data is input (RTC write mode) and output (RTC read mode) on the rising edge of CLK. Data read and write input/output Frequency output (output controlled by FOE and frequency selected by FSEL). In 1 Hz output mode, the 1 Hz signal is synchronized to the internal 1 second signal. FOUT output is not affected by the CE signal. No connection. Leave open for normal use. Description FSEL I WR I FOE I VDD CLK DATA FOUT N. C – I I/O O – SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage range Input voltage range Output voltage range Storage temperature range Soldering temperature Soldering time Symbol VDD V IN VO UT Tstg Tsld tsld Condition Ta = 25 °C Ta = 25 °C Ta = 25 °C Rating −0.3 to 7.0 V S S − 0.3 to V D D + 0.3 V S S − 0.3 to V D D + 0.3 −55 to 125 260 10 Unit V V V °C °C s Recommended Operating Conditions VSS = 0 V Parameter Supply voltage range Clock supply voltage range Operating temperature range Symbol VDD V C LK Topr Condition Rating 2.5 to 5.5 1.4 to 5.5 −40 to 85 Unit V V °C NIPPON PRECISION CIRCUITS—3 NR8576 Series Oscillator Characteristics Parameter Frequency deviation Symbol ∆f/fO Top f/V tSTA fA Condition Ta = 25 °C, V D D = 5.0 V NR8576×A NR8576×B Rating 5 ± 12 5 ± 23 +10/−120 ±2 3 ±5 Unit ppm ppm ppm ppm/V s ppm Frequency temperature characteristic Frequency voltage characteristic Oscillator start time Aging Ta = −10 to 70 °C, V D D = 5.0 V, 25 °C std Ta = 25 °C, V D D = 2.0 to 5.5 V Ta = 25 °C, V D D = 2.5 V Ta = 25 °C, V D D = 5.0 V, first year DC Electrical Characteristics VSS = 0 V, VDD = 5.0 V ± 10%, Ta = −40 to 85 °C unless otherwise noted Rating Parameter Symbol ID D1 ID D2 Current consumption ID D3 ID D4 ID D5 ID D6 HIGH-level input voltage LOW-level input voltage Input OFF leakage current V IH V IL IO FF VO H1 VO H2 LOW-level output voltage Output load fanout Output leakage current Supply voltage detect threshold voltage VOL1 VOL2 N/CL IO ZH IO ZL VDT V D D = 5.0 V V D D = 3.0 V V D D = 2.0 V V D D = 5.0 V V D D = 3.0 V V D D = 2.0 V Condition min CE = V S S, FOE = V S S, FSEL = V D D, FOUT: floating – – – – – – 0.8VD D – – 4.5 2.0 – – typ 1.5 1.0 0.5 4.0 2.5 1.5 – – – – – – – 2 LSTTL/30 pF max. −1.0 −1.0 1.4 – – 1.7 1.0 1.0 2.0 µA µA V max 3.0 2.0 1.0 10.0 6.5 4.0 – 0.2VD D 0.5 – – 0.5 0.8 µA µA µA µA µA µA V V µA V V V V Unit CE = V S S, FOE = V D D, FSEL = V S S, FOUT: 32 kHz output CE, FSEL, WR, FOE, CLK, DATA CE, FSEL, WR, FOE, CLK, DATA CE, FSEL, WR, FOE, CLK; V IN = V D D or V S S V D D = 5.0 V V D D = 3.0 V V D D = 5.0 V V D D = 3.0 V F OUT VO UT = 5.5 V; DATA, FOUT VO UT = 0 V; DATA, FOUT IO H = −1.0 mA; DATA, FOUT IO L = 1.0 mA; DATA, FOUT HIGH-level output voltage NIPPON PRECISION CIRCUITS—4 NR8576 Series AC Characteristics VDD = 3.0 V, VSS = 0 V, Ta = 25 °C unless otherwise noted Rating Parameter Symbol V D D = 5 V ± 10% min CLK clock period CLK LOW-level pulsewidth CLK HIGH-level pulsewidth CE setup time CE hold time CE enable time Write data setup time Write data hold time WR setup time WR hold time DATA output delay time DATA output floating time Clock rise time Clock fall time FOUT rise time (CL = 30 pF) FOUT fall time (CL = 30 pF) Disable time (CL = 30 pF) tC LK tCLKL tC LKH tC ES tC EH tC E tS D tH D tW RS tW RH tDATD tD Z tr1 tf1 tr2 tf2 tH Z tLZ tZ H tZL Duty tR CV 0.75 0.375 0.375 0.375 0.375 – 0.1 0.1 100 100 – – – – – – – – – – 40 0.95 max 7800 3900 3900 3900 – 0.9 – – – – 0.2 0.1 50 50 100 100 100 100 100 100 60 – V D D = 3 V ± 10% min 1.5 0.75 0.75 0.75 0.75 – 0.2 0.1 100 100 – – – – – – – – – – 40 1.9 max 7800 3900 3900 3900 – 0.9 – – – – 0.4 0.2 100 100 200 200 200 200 200 200 60 – µs µs µs µs µs s µs µs ns ns µs µs ns ns ns ns ns ns ns ns % µs Unit Enable time (CL = 30 pF) FOUT duty cycle (CL = 30 pF) Wait time NIPPON PRECISION CIRCUITS—5 NR8576 Series Timing Diagrams Data read tCE WR tWRS tWRH CE tCES CLK tCLKH tCLKL DATA tDATD tf1 tr1 tDZ tCLK tCEH tRCV Data write tCE WR tWRS CE tCES CLK tCLKH tCLKL tSD tHD DATA tf1 tr1 tCLK tCEH tRCV tWRH NIPPON PRECISION CIRCUITS—6 NR8576 Series FOUT tf2 90% tH 50% 10% FOUT tr2 t H Duty= tt X 100(%) Disable/Enable tZH FOE 50% 50% tHZ 90% FOUT 10% tZL FOE 50% 50% tLZ 90% FOUT 10% Note that FOE and FSEL do not have chatter elimination circuits. Consequently, switching either FOE or FSEL during 32 kHz mode operation may generate chatter noise on the FOUT output. Also, note that the 1 Hz and 32 kHz oscillators are not synchronized to each other, so switching intervals shortens the duty cycle. Accordingly, a wait time (≥ chattering time + output frequency period) should be incorporated when switching intervals. NIPPON PRECISION CIRCUITS—7 NR8576 Series FUNCTIONAL DESCRIPTION Timer data configuration s s s s Counter data in BCD code format Automatic long/short month and leap-year adjustment 24-hour time display LSB first write and read data MSB LSB S40 S20 S10 S8 S4 S2 S1 Second ( 0 to 59 ) FDT Minute ( 0 to 59 ) ∗ mi40 mi20 mi10 mi8 mi4 mi2 mi1 Hour ( 0 to 23 ) ∗ ∗ h20 h10 h8 h4 h2 h1 Week ( 1 to 7 ) ∗ w4 w2 w1 Day ( 1 to 31 ) ∗ ∗ d20 d10 d8 d4 d2 d1 Month ( 1 to 12 ) TM ∗ ∗ mo10 mo8 mo4 mo2 mo1 Year ( 0 to 99 ) y80 y40 y20 y10 y8 y4 y2 y1 1. * bit: Optional write bits. 2. FDT bit: Supply voltage detect bit • The FDT bit is set to 1 when the voltage between VDD and VSS falls below 1.7 ± 0.3 V. • The FDT bit is reset to 0 for data reads longer than 48 bits. Note that the FDT bit is not reset to 0 for data reads of 47 bits or less. • The read/write data bits should be should be set to 0. After the supply voltage is applied, the FDT bit should be set to 0. VDD VDET 0.5 second 0.5 second Detected Pulse CE (READ MODE) FDT 3. TM bit: Factory test bit. Should be set to 0 for normal use. NIPPON PRECISION CIRCUITS—8 NR8576 Series Data Read 1 2 3 52 53 54 54+n CLK CE WR DATA OUTPUT MODE S1 S2 S4 S8 S10 S20 S40 FDT y8 y10 y20 y40 y80 second year NON CHANGE OUTPUT DATA Data is output when WR is LOW and CE is HIGH. Time and calendar data is loaded into shift registers on the first rising edge of the clock CLK, and the seconds’ digit LSB is output on DATA. The data is then loaded and shifted in the sequence second, minute, hour, week, day, and month on the rising edge of CLK, and output on DATA. The output data is valid after 52 rising edges of the clock; data input after 52 cycles does not alter the first 52 bits of valid data. Within the 52 cycles of valid data, data already input can be output if there is a falling edge of CE after the corresponding number of cycles. For example, the data comprising the second-to-week is output is CE goes LOW after 28 clock cycles. For continuous data reads, a wait time (tRCV) is required before the next data cycle if CE has gone LOW. Note that if an update operation (a 1 s carry) occurs during a data read, an error of −1 s in the read data is generated. The data read time should be completed after tCE ≤ 0.9 s. NIPPON PRECISION CIRCUITS—9 NR8576 Series Data Write 1 2 3 52 53 54 54+n CLK CE WR DATA INPUT MODE S1 S2 S4 S8 S10 S20 S40 FDT y8 y10 y20 y40 y80 second year Data is input when WR is HIGH and CE is HIGH. The seconds’ digit signal to the timer counter stops on the first falling edge of CLK and the counter remains stopped until the next rising edge of CE. The 1 Hz to 128 Hz frequency divider step counters are reset during the interval between the first and second rising edges of CLK. The data is then input on DATA into the shift register, starting with seconds’ digit LSB synchronized with the rising edge of CLK. After the final data is input into the shift register following 52 cycles, the shift register contents are trans- ferred to the timer counters. Note that a data write must contain 52 bits of input data. If CE goes LOW before 52 bits are input, the input data is invalid. If the input data exceeds 52 bits, data from the 53rd bit is ignored (the first 52 bits remain valid). The data write time should be completed after tCE ≤ 0.9 s. If a data read occurs immediately after a data write, a wait time (tRCV) is required if CE has gone LOW. Note that writing null data will cause incorrect operation. All bits must be valid data bits. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9603CE 1997.06 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—10