SM5168XXV

SM5168 series PLL Synthesizer IC OVERVIEW The SM5168 series are PLL synthesizer ICs fabricated using NPC’s Molybdenum-gate CMOS process. They provide several combinations of reference and comparator frequency divider ratios, set in master-slice, making them ideal for frequency synthesizers in IF stages of mobile communications devices. They also feature a lock detect signal output (LD). FEATURES I I PACKAGE DIMENSIONS (Unit: mm) I I I I I I 0.10 0.22 ± 0.1 0.1 ± 0.05 2.7 to 3.6V operating supply voltage range Maximum operating frequency • SM5168A× series: 200MHz, VDD = 2.7V • SM5168C× series: 340MHz, VDD = 2.7V Operating current consumption • SM5168A× series: 3.3mA (typ, 200MHz at 0.3Vp-p, VDD = 3.0 V) • SM5168C× series: 4mA (typ, 340MHz at 0.3Vp-p, VDD = 3.0 V) SM5168A× (built-in standby function) and SM168C× (dual frequency divider ratios) series available, as set by master-slice Charge pump output with output polarity for connection to passive filter Lock detect function output −30 to 85°C operating temperature range 8-pin plastic VSOP 4.4 ± 0.2 6.4 ± 0.3 0.575 typ 3.1 ± 0.3 1.15 ± 0.05 0.15 −0.05 +0.1 0.65 0.12 M APPLICATIONS I I I Mobile communications Portable telephones Related applications SERIES CONFIGURATION Version SM5168A× series SM5168C× series Maximum operating frequency 200MHz 340MHz Reference/comparator frequency dividers 1 2 Frequency divider ratio range1 Standby function N counter 272 to 65535 272 to 65535 R counter 5 to 65535 5 to 65535 Yes No 1. SM5168C× series: Dual frequency divider ratios are set within the ratio ranges. ORDERING INFORMATION Device SM5168××V Package 8-pin VSOP SEIKO NPC CORPORATION —1 0.5 ± 0.2 SM5168 series PINOUT (Top view) SM5168A× series SM5168C× series VDD 1 DO 2 VSS 3 FIN 4 8 7 6 5 XIN LD TEST VDD 1 DO 2 VSS 3 FIN 4 8 7 6 5 XIN LD TEST OPR TR PIN DESCRIPTION Number 1 2 3 4 Name VDD DO VSS FIN OPR (SM5168A× series) TR (SM5168C× series) 6 7 8 TEST LD XIN I O I I/O – O – I 2.7 to 3.6V supply Phase comparator error signal three-state output pin. Built-in charge pump means that this output can be connected to a low-pass filter. The output polarity is preset for connection to a passive filter. Ground pin Phase comparator frequency divider (N-counter) signal input pin. Feedback resistor built-in, so input can be AC-coupled. Power-save control pin. Start when HIGH, standby mode when LOW. I Frequency divider switching control. Switches between 2 sets of reference and comparator frequency dividers. Test pin. Leave open or connect to VSS for normal operation. Unlock signal output pin. (Unlocked when LOW) Reference frequency divider (R-counter) external clock input pin. Feedback resistor built-in, so input can be AC-coupled. Description 5 SEIKO NPC CORPORATION —2 SM5168 series BLOCK DIAGRAMS SM5168A× series XIN R-counter (64) FR OPR TEST FIN Control Circuit Phase Detector Charge Pump DO N-counter (890) FV Lock Detector LD SM5168C× series XIN R-counter FR TR TEST FIN Decoder Phase Detector Charge Pump DO N-counter FV Lock Detector LD SEIKO NPC CORPORATION —3 SM5168 series SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Supply voltage Input voltage range Storage temperature range Power dissipation Symbol VDD VIN TSTG PD Rating −0.3 to 6.0 VSS − 0.3 to VDD + 0.3 −55 to 125 100 Unit V V °C mW Recommended Operating Conditions VSS = 0V Parameter Supply voltage Operating temperature range Symbol VDD TOPR Rating 2.7 to 3.6 −30 to 85 Unit V °C SEIKO NPC CORPORATION —4 SM5168 series Electrical Characteristics VSS = 0V, VDD = 2.7 to 3.6V, Ta = −30 to 85°C unless otherwise noted. Rating Parameter Supply voltage VDD operating current consumption 1 (SM5168A× series) VDD operating current consumption 2 (SM5168C× series) FIN maximum operating frequency 1 (SM5168A× series) XIN maximum operating frequency 1 (SM5168A× series) FIN maximum operating frequency 2 (SM5168C× series) XIN maximum operating frequency 2 (SM5168C× series) FIN minimum operating input frequency FIN AC-coupled input voltage range XIN AC-coupled input voltage range OPR, TR LOW-level input voltage OPR, TR HIGH-level input voltage XIN LOW-level input current FIN LOW-level input current XIN HIGH-level input current FIN HIGH-level input current OPR, TR LOW-level input leakage current OPR, TR HIGH-level input leakage current DO, LD LOW-level output voltage DO, LD HIGH-level output voltage DO, LD LOW-level output current DO, LD HIGH-level output current DO three-state output high-impedance leakage current Note 1. Note 2. Note 3. Symbol VDD IDD1 Note 1. VDD = 3.0V VDD = 3.3V Note 2. 300mVp-p sine wave. Note 3. 300mVp-p sine wave Note 3. 300mVp-p sine wave Note 3. 300mVp-p sine wave Note 3. 300mVp-p sine wave Note 3. 340MHz 20MHz VDD = 3.0V VDD = 3.6V VDD = 2.7V VDD = 2.7V VDD = 2.7V VDD = 2.7V VDD = 3.6V VDD = 2.7V VDD = 2.7V VDD = 2.7V VDD = 2.7V VIN = 0V VIN = 0V VIN = VDD VIN = VDD VIN = 0V VIN = VDD IOL = 0.25mA IOH = 0.25mA VOL = 0.4V VOH = VDD − 0.4V VOL = 0V VOH = VDD VDD = 3.6V VDD = 3.6V VDD = 3.6V VDD = 3.6V VDD = 3.6V VDD = 3.6V VDD = 2.7V VDD = 2.7V VDD = 2.7V VDD = 2.7V VDD = 3.6V VDD = 3.6V Condition min 2.7 – – – – 200 20 340 20 – 0.3 0.3 – VDD − 0.3 – – – – – – – VDD − 0.4 0.25 0.25 – – typ – 3.3 – 4 – – – – – – – – – – – – – – – – – – – – – – max 3.6 – mA 5.2 – mA 8 – – – – 10 – – 0.3 – 50 50 50 50 100 100 0.4 – – – 100 100 MHz MHz MHz MHz MHz Vp-p Vp-p V V µA µA µA µA nA nA V V mA mA nA nA V Unit IDD2 fmax1 fmax2 fmax1 fmax2 fmin VAC1 VAC2 VIL VIH IIL1 IIL2 IIH1 IIH2 ILL ILH VOL VOH IOL IOH IOZL IOZH fFIN = 200MHz (300mVp-p sine wave), fXIN = 20MHz (300mVp-p sine wave), TR = HIGH fFIN = 340MHz (300mVp-p sine wave), fXIN = 20MHz (300mVp-p sine wave), TR = HIGH Signal generator AC-coupled input with 50Ω termination. SEIKO NPC CORPORATION —5 SM5168 series FUNCTIONAL DESCRIPTION SM5168A× series Frequency dividers The comparator frequency divider (N-counter) and reference frequency divider (R-counter), one of each, are set in master-slice to the following values. I I Comparator frequency divider (N-counter) = 272 to 65535 Reference frequency divider (R-counter) = 5 to 65535 Standby mode When OPR goes from HIGH to LOW, the PLL is in standby mode with the following input/output conditions. Block Input FIN Comparator frequency divider (N-counter) Input XIN Reference frequency divider (R-counter) Phase comparator Output DO Output LD State LOW level Stopped LOW level Stopped Reset Floating LOW-level When OPR goes from LOW to HIGH, standby mode is released and the PLL is in operating mode, and the following start-up sequence is executed. Internal feedback resistance is connected to XIN to activate the reference frequency divider (R-counter). Internal feedback resistance is connected to FIN. The comparator frequency divider (N-counter) and the phase comparator are reset. DO is floating and LD is LOW. ↓ Reference frequency divider (R-counter) starts to perform frequency division. An internal signal (FR signal) is output on the 2nd clock cycle. ↓ Phase comparator starts and comparator frequency divider (N-counter) starts to perform frequency division. DO floating condition is released and LD goes HIGH. SEIKO NPC CORPORATION —6 SM5168 series SM5168C× series Frequency Dividers The comparator frequency divider (N-counter) and reference frequency divider (R-counter), with 2 sets of comparator frequency divider and reference frequency divider ratios, are set in master-slice. The frequency divider set selected is determined by the state of TR (pin 5). The ratio ranges are the same when TR is HIGH or LOW, and are: I I Comparator frequency divider (N-counter) = 272 to 65535 Reference frequency divider (R-counter) = 5 to 65535 Frequency Divider Switching When switching the frequency dividers using TR, the dividers switch in sync with the R-counter divider signal (FR) and the N-counter divider signal (FV) to minimize any disturbance in the PLL loop. TR = HIGH divider operation starts t1 FV or FR t2 t2 t3 TR Decoder output TR = LOW frequency divider TR = HIGH frequency divider Counter set signal TR = LOW frequency divider counter set TR = HIGH frequency divider counter set If tF represents the FIN cycle time: t1 = 48tF t2 = (divider ratio when TR = LOW) × tF t3 = (divider ratio when TR = HIGH) × tF If tX represents the XIN cycle time: t1 = 3tX t2 = (divider ratio when TR = LOW) × tX t3 = (divider ratio when TR = HIGH) × tX Both the R-counter and N-counter are configured with presettable counters. The divider outputs (FR and FV) are then input to the phase comparator which performs phase comparison on the falling edge of each signal. The FR/FV signals also function as the R/N-counter preset strobe signals, respectively. Consequently, when the TR signal level switches, the decoder output changes on the first FR/FV (R/N-counter preset strobe) signal and the counters are set in the new frequency dividers on the second FR/FV (R/N-counter preset strobe) signal. Frequency division with the new frequency dividers starts on the falling edge of the second FR/FV (R/N-counter preset strobe) signal. The timing in the diagram shows an example when TR goes from LOW to HIGH only, but the timing operation is identical under the reverse transition. The R/N-counters operate with the same timing, although the Ncounter has a dual modulus prescaler in the initial-stage which means the HIGH-level pulsewidth of the FV and FR signals is different. SEIKO NPC CORPORATION —7 SM5168 series DO Output Timing The phase comparator error signal charge pump signal is output on DO with polarity for connection to an external passive filter. The signals compared are FV and FR, which are the internal comparator frequency divider output signal and reference frequency divider output signal, respectively. The timing is shown in the following figure. FR FV DO LD INPUT/OUTPUT EQUIVALENT CIRCUITS DO FIN TYP100kΩ Lagging correction signal DO Leading correction signal FIN To internal counter From internal circuit TR TEST TR To internal circuit TEST To internal circuit LD XIN TYP100kΩ From internal circuit LD XIN To internal counter From internal circuit SEIKO NPC CORPORATION —8 SM5168 series Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp NC0008BE 2006.04 SEIKO NPC CORPORATION —9