SM5816AF

SM5816AF 6-channel DSD-PCM Converter OVERVIEW The SM5816AF is a 6-channel DSD data to 6-channel 8fs or 2fs PCM data converter IC. During conversion, decimation filtering is performed using a filter with selectable fixed coefficients (4 sets) or optional filter coefficients that are written to the built-in RAM. Also, DSD input/outputs and PCM outputs are available for use in master/slave clock mode operation, in a wide range of system configurations, making it easy to construct a multi-channel DSD/PCM reproduction system. FEATURES I I PINOUT (Top view) I 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS6 EXIMCK EXID1 EXID2 EXILRCK EXIBCK TEST3 TEST2 MCK VDD5 VSS5 CKOUT TEST1 F2FLREX1 F2CSWEX2 F2SLR F2LRCK F2BCK FMT2FS VDD4 I I I I I I I I I I I I 512fs master clock (22.5792MHz, fs = 44.1kHz) DSD inputs connected directly to outputs in through mode Clock master/slave switching for DSD input/outputs and PCM outputs 2-system external data inputs (3-wire), with 2fs output data BCK and LRCK pins switchable between external inputs and internal filter outputs Decimation filter characteristics • Fixed coefficients: 4 sets (8fs), 1 set (2fs) • Rewritable coefficients: 1 set (29 bit × 240 word) Dither rounding function in 8fs/24-bit output mode, with switchable ON/OFF and summing position PCM/DSD output independent muting operation 8fs output format: [MSB-first left-justified 32-bit] or [MSB-first right-justified 24-bit] 2fs output format: [MSB-first left-justified 32-bit] or [IIS 32-bit] +6dB DSD gain switching function System clock output switchable between external system clock and internal system clock 3.3V ± 10% supply voltage 5V tolerant inputs for direct connection to 5V logic outputs −20 to 70°C operating temperature range 80-pin QFP package VDD6 DSBCKF DSIFL DSIFR DSICT DSISW DSISL DSISR DIRDSCK1 DIRDSCK2 SELRAM SELFIR1 SELFIR2 XMTPCM XMTDSD SEL8FS SELEXT SYNC INIT VSS7 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS4 DIR2CK SELDH1 SELDH2 F8FL F8FR F8CT F8SW F8SBL VDD3 VSS3 F8SBR F8SL F8SR F8WCK F8BCK FMT8WCK FMT8FS DIR8CK VDD2 PACKAGE DIMENSIONS (Unit: mm) 14 ± 0.4 12 ± 0.1 APPLICATIONS I I Multi-channel SA-CD players SA-CD-compatible AV amplifiers 0.5 1.7max 0.1 0.18 0.05 1.4 ± 0.1 ORDERING INFORMATION Device SM5816AF Package 80-pin QFP 14 ± 0.4 12 ± 0.1 VDD1 MSHIFT MLATCH MDATA DSGAIN SELSBSW SELSBR SELMCU MONTOR VSS1 DSBCKB DSOSR DSOSL DSOSBR DSOSBL DSOSW DSOCT DSOFR DSOFL VSS2 0.05 0.125 0.025 0 to 10 0.1 0.5 ± 0.2 SEIKO NPC CORPORATION —1 SM5816AF PIN DESCRIPTION No. 1 2 3 4 5 Name VDD1 MSHIFT MLATCH MDATA DSGAIN I/O – I I I I Property1 – S S S PD Output current – – – – – Input voltage – 3.3/5 3.3/5 3.3/5 3.3/5 Supply pin 1 Serial control: shift clock Serial control: latch clock Serial control: command data DSD signal gain setting L: 100% modulation = 0dB, H: 50% modulation = 0dB DSD-SW input to SW/(SBL, SBR) output select L: SW input to SW output, H: SW input to (SBL, SBR) output Note. It effects both of DSD and 8fs outputs. DSD 8fs-(SBL, SBR) output select L: SBL output only, H: both SBL, SBR output Note: Valid only when SELSBSW is HIGH. Control method select L: pin control, H: serial interface data control Parameter change monitor output Ground pin 1 DSD through-mode data output: bit clock, controlled by DIRDSCK1, 2 DSD through-mode data output: surround right-channel DSD through-mode data output: surround left-channel DSD through-mode data output: surround back right-channel DSD through-mode data output: surround back left-channel DSD through-mode data output: subwoofer channel DSD through-mode data output: center channel DSD through-mode data output: front right-channel DSD through-mode data output: front left-channel Ground pin 2 Supply pin 2 8fs output F8BCK, F8WCK input/output select L: output (master mode), H: Input (slave mode) 8fs PCM format (MSB-first) L: MSB-first left-justified 32-bit, H: MSB-first right-justified 24-bit Note: In 8fs right-justified 24-bit format, there are a fixed 32 bit clock (F8BCK) cycles per word clock (F8WCK) cycle. Note: In 8fs right-justified 24-bit format, the upper empty bits are for sign extension. 8fs PCMWCK format L: “H” → “L” (rising-edge word boundary) H: “L” → “H” (falling edge word boundary) 8fs PCM BCK (bit clock) 8fs PCM WCK (word clock) 8fs PCM data output: surround right-channel 8fs PCM data output: surround left-channel 8fs PCM data output: surround back right-channel Ground pin 3 Supply pin 3 8fs PCM data output: surround back left-channel 8fs PCM data output: subwoofer channel 8fs PCM data output: center channel Description 6 SELSBSW I PD – 3.3/5 7 SELSBR I PD – 3.3/5 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SELMCU MONTOR VSS1 DSBCKB DSOSR DSOSL DSOSBR DSOSBL DSOSW DSOCT DSOFR DSOFL VSS2 VDD2 DIR8CK I O – I/O O O O O O O O O – – I PD – – S – – – – – – – – – – PD – 2mA – 6mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA – – – 3.3/5 – – 3.3/5 – – – – – – – – – – 3.3/5 23 FMT8FS I PD – 3.3/5 24 25 26 27 28 29 30 31 32 33 34 FMT8WCK F8BCK F8WCK F8SR F8SL F8SBR VSS3 VDD3 F8SBL F8SW F8CT I I/O I/O O O O – – O O O PD S S – – – – – – – – – 6mA 6mA 2mA 2mA 2mA – – 2mA 2mA 2mA 3.3/5 3.3/5 3.3/5 – – – – – – – – SEIKO NPC CORPORATION —2 SM5816AF Output current 2mA 2mA – – Input voltage – – 3.3/5 3.3/5 No. 35 36 37 38 Name F8FR F8FL SELDH2 SELDH1 I/O O O I I Property1 – – PD PD Description 8fs PCM data output: front right-channel 8fs PCM data output: front left-channel Output dither rounding ON/OFF and summing position select SELDH (2, 1) Dither (L, L) OFF (L, H) 1LSB (H, L) 2LSB (H, H) 4LSB 39 DIR2CK I PD – 3.3/5 2fs output F2BCK, F2LRCK input/output select L: output (master mode), H: input (slave mode) Note: In 2fs-PCM output, when external inputs (EXID1, EXID2) are selected for output (SELEXT = “H”), the DIR2CK setting is inactive, and EXILRCK and EXIBCK are output as-is on F2LRCK and F2BCK, respectively. Ground pin 4 Supply pin 4 2fs PCM format L: MSB-first left-justified 32-bit, H: IIS 32-bit Note: In 2fs IIS 32-bit format, there are 64 F2BCK clock cycles per F2LRCK clock cycle. 2fs or external data BCK 2fs or external data LRCK 2fs PCM data output: surround left/right-channel 2fs PCM data output: center/subwoofer channel or external data 2 output 2fs PCM data output: front left/right-channel or external data 1 output Test pin 1 (must be open or tie LOW for normal operation) System clock output. Clock output selected by SELEXT. Ground pin 5 Supply pin 5 Master clock input: 512fs (22.5792MHz, fs = 44.1kHz) Test pin 2 (must be open or tie LOW for normal operation) Test pin 3 (must be open or tie LOW for normal operation) External PCM data BCK input External PCM data LRCK input External PCM data input 2 External PCM data input 1 External system clock input Ground pin 6 Supply pin 6 DSD data input bit clock. Controlled by DIRDSCK1, 2 DSD data input: front left-channel DSD data input: front right-channel DSD data input: center channel DSD data input: subwoofer channel DSD data input: surround left-channel DSD data input: surround right-channel DSBCKF I/O select L: input (slave), H: output (master) DSBCKB I/O select L: output (master), H: input (slave) 40 41 VSS4 VDD4 – – – – – – – – 42 FMT2FS I PD – 3.3/5 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 F2BCK F2LRCK F2SLR F2CSWEX2 F2FLREX1 TEST1 CKOUT VSS5 VDD5 MCK TEST2 TEST3 EXIBCK EXILRCK EXID2 EXID1 EXIMCK VSS6 VDD6 DSBCKF DSIFL DSIFR DSICT DSISW DSISL DSISR DIRDSCK1 DIRDSCK2 I/O I/O O O O I O – – I I I I I I I I – – I/O I I I I I I I I S S – – – PD, S – – – – PD PD S S – – – – – S – – – – – – PD PD 6mA 6mA 2mA 2mA 2mA – 12mA – – – – – – – – – – – – 6mA – – – – – – – – 3.3/5 3.3/5 – – – 3.3/5 – – – 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 – – 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 SEIKO NPC CORPORATION —3 SM5816AF Output current – – – Input voltage 3.3/5 3.3/5 3.3/5 No. 71 72 73 Name SELRAM SELFIR1 SELFIR2 I/O I I I Property1 PD PD PD Description FIR coefficient ROM/RAM select L: ROM, H: RAM FIR coefficient (ROM) select SELFIR (2, 1) FIR coeff (L, L) coeff 1 (L, H) coeff 2 (H, L) coeff 3 (H, H) coeff 4 74 75 76 77 78 79 80 XMTPCM XMTDSD SEL8FS2, 3 SELEXT2, 3 SYNC4 INIT4, 5 VSS7 I I I I I I – PD PD PD PD S S – – – – – – – – 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 – PCM output mute control input L: mute-ON, H: mute-OFF DSD output mute control input L: mute-ON, H: mute-OFF PCM output rate select L: 2fs, H: 8fs 2fs output/external data output select L: 2fs data, H: external data (EXID1, EXID2) Forced sync control. Sync on rising edge Initialization control. Active-LOW. Resync on “L” → “H” Ground pin 7 1. S = Schmitt, PD = pull-down resistor 2. The SEL8FS setting takes precedence over the SELEXT setting. In other words, 8fs PCM output is selected when SEL8FS is HIGH, and the SELEXT settings are not effective. The SELEXT also selects relevant clock pins (F2LRCK, F2BCK, CKOUT). 3. Outputs not selected by SEL8FS and SELEXT are treated as described below: • Data signals are tied LOW. • When I/O pins F8WCK, F8BCK, F2LRCK, F2WCK are set as outputs, they function as outputs. When they are set as inputs, they are ignored in input mode. 4. The output data is synchronized each time by event-driven operation despite the clock input/output. The resynchronization operation occurs to avoid reading DSD input data at the falling edge of DSBCKF. 5. The internal flip-flops are all initialized in response to an active level on INIT, and outputs are tied HIGH or LOW during INIT active level input. SEIKO NPC CORPORATION —4 SM5816AF BLOCK DIAGRAM DSIFL DSIFR DSICT DSISL DSISR DSISW XMTDSD XMTPCM DSGAIN SELDH1 SELDH2 DSD MUTE DSD SW/SB SELECT DSOFL DSOFR DSOCT DSOSL DSOSR DSOSW DSOSBL DSOSBR SEL8FS SELFIR1 SELFIR2 FIR FILTER and DOWN SAMPLING UNIT PCM MUTE 8fs SW/SB SELECT 8fs I/F F8FL F8FR F8CT F8SL F8SR F8SW F8SBL F8SBR FMT8FS FMT8WCK SELRAM COEF. SELECT RAM 29bit 240word ROM 24bit 720word SELSBSW SELSBR MDATA MSHIFT MLATCH SELMCU EXID1 EXID2 EXILRCK EXIBCK EXIMCK SYNC INIT DIRDSCK1 DIRDSCK2 DSBCKF MCK TEST1 TEST2 TEST3 CPU I/F CONTROL (Internal Control) 2fs EXT. DATA SELECT 2fs I/F F2SLR F2FLREX1 F2CSWEX2 FMT2FS SELEXT DIR2CK 2fs EXT. CLOCK SELECT CLOCK GENERATOR and TIMING CONTROL (Internal Clocks) F2LRCK F2BCK CKOUT DIR8CK F8WCK F8BCK DSBCKB TEST/MONTOR CONTROL MONTOR SEIKO NPC CORPORATION —5 SM5816AF SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Supply voltage Input voltage 1 (3.3V) Input voltage 2 (3.3V/5V)1 Power dissipation Storage temperature Symbol VDD VIN1 VIN2 PW TSTG Rating – 0.3 to 4.0 – 0.3 to VDD + 0.5 – 0.3 to 7.0 300 – 55 to 125 Unit V V V mW °C 1. Input voltage 2 applies to pins with 5V input rating. Recommended Operating Conditions VSS = 0V Parameter Supply voltage Operating temperature Symbol VDD TOPR Rating 3.0 to 3.6 – 20 to 70 Unit V °C DC Electrical Characteristics VDD = 3.0 to 3.6V, VSS = 0V, TOPR = – 20 to 70°C unless otherwise noted. Rating Parameter Current consumption “H" level Input voltage “L" level Positive Schmitt-trigger voltage Negative Hysteresis voltage "H" level Output voltage "L" level Input leakage current Pull-down resistance (*3) (*1, 2) (*4) VOL ILI RPD VI = VDD (*2) (*2) (*3) (*1) (*2) Pin VDD (*1) Symbol IDD VIH VIL VT+ VT– VH VOH IOH = – 2mA (Type1) IOH = – 6mA (Type2) IOH = – 12mA (Type3) IOL = 2mA (Type1) IOL = 6mA (Type2) IOL = 12mA (Type3) Condition min All pins no load VDD = 3.6V VDD = 3.0V – 2.0 – 1.1 0.6 0.1 VDD – 0.4 typ – – – – – – – max 80 – 0.8 2.4 1.8 – – mA V V V V V V Unit – –1 40 – – 100 0.4 1 240 V µA kΩ Pin summary (*1) (*2) Input pins and bidirectional (input/output) pins in input mode Inputs with Schmitt characteristic and bidirectional (input/output) pins in input mode Output pins and bidirectional (input/output) pins in output mode Type 3: CKOUT Type 2: DSBCKB, DSBCKF, F8BCK, F8WCK, F2BCK, F2LRCK Type 1: Outputs excluding those above Inputs with pull-down resistor (*3) (*4) SEIKO NPC CORPORATION —6 SM5816AF AC Electrical Characteristics VDD = 3.0 to 3.6V, VSS = 0V, TOPR = – 20 to 70°C, fs = 44.1kHz unless otherwise noted. If DSBCKF, DSBCKB, F8WCK, F2LRCK clocks are input externally, by frequency division the clock input on MCK has the following relationships. (DSBCKF, DSBCKB) cycle = 8 × MCK cycle (64fs) (F8WCK) cycle = 64 × MCK cycle (8fs) (F2LRCK) cycle = 256 × MCK cycle (2fs) System clock I MCK pin Rating Parameter Symbol min typ – – 44.29 (1/512fs) – max – – – 10 ns ns ns ns tMCWH tMCWL tMCY t r , tf 13 13 40 – Unit "H"-level pulsewidth "L"-level pulsewidth Pulse cycle Rise/fall time tMCY tMCWH MCK tr tf tMCWL 0.9VDD 0.5VDD 0.1VDD External system clock I EXIMCK pin Rating Parameter Symbol min typ – – – – max – – – 10 ns ns ns ns tECWH tECWL tECY ter , tef 13 13 40 – Unit "H"-level pulsewidth "L"-level pulsewidth Pulse cycle Rise/fall time tECY tECWH EXIMCK tECWL 0.9VDD 0.5VDD 0.1VDD ter tef SEIKO NPC CORPORATION —7 SM5816AF DSD input/output I I I DSBCKF, DSBCKB pins DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins DSOFL, DSOFR, DSOSL, DSOSR, DSOCT, DSOSW, DSOSBL, DSOSBR pins Rating Parameter Symbol min typ 177.16 354.31 (1/64fs) – – – max – – – – 15 ns ns ns ns ns tDSCW tDSCY tDSS tDSH tDSDLY 150 300 50 50 0 Unit DSD clock pulsewidth DSD clock pulse cycle DSD data setup time DSD data hold time DSD data delay time tDSCY tDSCW DSBCKF tDSCW tDSS DSI** tDSH tDSCY tDSCW DSBCKB tDSCW tDSDLY DSO** DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins DSO**: DSOFL, DSOFR, DSOSL, DSOSR, DSOCT, DSOSW, DSOSBL, DSOSBR pins Note. The DSD clock pulsewidth and clock pulse cycle are with both DSBCKF and DSBCKB in input mode. Note. Data is read internally using the falling edge of MCK, using the DSBCKF timing above as the base. When the timing changes, resynchronization must be performed using INIT or SYNC. SEIKO NPC CORPORATION —8 SM5816AF PCM output I I F8WCK, F8BCK, F8FL, F8FR, F8SL, F8SR, F8CT, F8SW, F8SBL, F8SBR pins F2LRCK, F2BCK, F2SLR, F2FLREX1, F2CSWEX2 pins Rating Parameter Symbol min typ 44.29 88.58 (1/256fs) 88.58 177.15 (1/128fs) – – – – max – – – – – – 15 15 ns ns ns ns ns ns ns ns tF8BCW tF8BCY tF2BCW tF2BCY tPLBS tPLBH tPBDLY tPLDLY 40 80 40 80 30 10 0 0 Unit 8fs BCK clock pulsewidth 8fs BCK clock pulse cycle 2fs BCK clock pulsewidth 2fs BCK clock pulse cycle Word CK setup time Word CK hold time Bit CK data delay time Word CK data delay time tF8BCY tF8BCW F8BCK tPLBH F8WCK tPLDLY F8** tPBDLY tPLBS tF8BCW tF2BCY tF2BCW F2BCK tF2BCW tPLBH F2LRCK tPLBS tPLDLY F2** tPBDLY F8**: F8FL, F8FR, F8SL, F8SR, F8CT, F8SW, F8SBL, F8SBR pins F2**: F2SLR, F2FLREX1, F2CSWEX2 pins Note. The 2fs PCM output rating excludes external inputs (EXI**) in through mode. Note. The 2fs/8fs bit clock and word clock relationship applies when F8BCK, F8WCK, F2BCK, F2LRCK pins are in input mode only. SEIKO NPC CORPORATION —9 SM5816AF Clock outputs I CKOUT, DSBCKF, DSBCKB, F8WCK, F8BCK, F2LRCK, F2BCK pins Rating Parameter Symbol min typ – – max 10 10 ns ns tCKODLY tCKDLY 0 0 Unit CKOUT output delay time Clock output delay time MCK tCKODLY CKOUT tCKDLY Word/Bit clock outputs tCKODLY Note. Rating with MCK, in through mode, output on CKOUT. Note. The word/bit clocks in output mode on pins F8BCK, F8WCK, F2BCK, F2LRCK, and DSBCKF, DSBCKB bidirectional pins in output mode. Through-mode output I DSBCKF, DSBCKB, CKOUT, F2BCK, F2LRCK, F2FLREX1, F2CSWEX2 pins Through inputs DSBCKF DSBCKB EXIMCK EXIBCK EXIWCK EXID1 EXID2 Through outputs DSBCKB DSBCKF CKOUT F2BCK F2LRCK F2FLREX1 F2CSWEX2 2fs PCM outputs with external inputs selected Conditions DSBCKF in input mode, DSBCKB in output mode DSBCKF in output mode, DSBCKB in input mode tTHDLY MAX 10 10 10 10 10 15 15 Unit ns ns ns ns ns ns ns Through mode input tTHDLY Through mode output tTHDLY SEIKO NPC CORPORATION —10 SM5816AF CPU serial control interface I MSHIFT, MDATA, MLATCH pins Rating Parameter Symbol min typ – – – – – – – max 1 – – – – – – MHz ns ns ns ns ns ns fMSCK tMSCW tMSDS tMSDH tMLWT tMLPW tMSWT – 480 200 200 200 10 × tMCY 0 Unit MSHIFT clock pulse frequency MSHIFT clock pulsewidth MDATA setup time MDATA hold time MLATCH wait time MLATCH pulsewidth MSHIFT wait time fMSCK tMSCW MSHIFT tMSDS MDATA tMSCW tMSDH Bit 2 Bit 1 tMLWT tMLPW tMSWT MLATCH Initialization and resynchronization I INIT, SYNC pins Rating Parameter Symbol min typ – – max – – ns ns tINTM tSYCW 6 × tMCY 6 × tMCY Unit Initialization time Resynchronization pulsewidth VDD 3.0V tINTM INIT tINTM tSYCW SYNC SEIKO NPC CORPORATION —11 SM5816AF FUNCTIONAL DESCRIPTION Data Input/Output Formats DSD input/output format DSD input data is read on the rising edge of the bit clock, and output data is output on the falling edge. (1/64fs) DSBCKF DSBCKB DSI** DSO** DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins DSO**: DSOFL, DSOFR, DSOSL, DSOSR, DSOCT, DSOSW, DSOSBL, DSOSBR pins 8fs output format There are two 8fs output formats that can be set using FMT8FS. Also, the F8WCK polarity can be inverted using FMT8WCK. (1) MSB-first left-justified 32-bit (FMT8FS = “L”) (1/8fs) F8WCK (FMT8WCK="L") (FMT8WCK="H") F8BCK F8** 31 30 29 28 27 26 25 24 MSB 3 2 1 0 LSB 31 30 F8**: F8FL, F8FR, F8SL, F8SR, F8CT, F8SW, F8SBL, F8SBR pins I I I If more than 32 bit clock cycles are input during each word clock cycle, data following the 32nd bit are output as “0”. When F8WCK and F8BCK are set as outputs, there are 32 fixed bit clock cycles per word clock cycle. Output data is in 32-bit 2s complement format. (2) MSB-first right-justified 24-bit (FMT8FS = “H”) (1/8fs) F8WCK (FMT8WCK="L") (FMT8WCK="H") F8BCK F8** ;;; ;;;; ;;;; ;;; ;;;; ;;;; ;;;; ;;;; ;;; 30;;;; 28 ;;;;26 ;;; 24 23 22 ;;;; 29;;;;27 ;;;;25;;;; 31 ;;; ;;;; ;;;; ;;; ;;;; ;;;; ;;;; ;;;; ;;; ;;;; ;;;; ;;; MSB ;;;; ;;;; ;;;; ;;;; 21 20 3 2 1 ;;;; ;;;; ;;;;30 31 ;;;; ;;;; ;;;; ;;;; ;;;; LSB 0 F8**: F8FL, F8FR, F8SL, F8SR, F8CT, F8SW, F8SBL, F8SBR pins I I I In this format, there are 32 bit clock cycles per word clock cycle regardless of the input/output settings. The code bits are comprised by the 24-bit output data. The output data is output in 32-bit sign extended format (data bits are shown as slash lines) Output data is in 24-bit 2s complement format. SEIKO NPC CORPORATION —12 SM5816AF 2fs output format There are two 2fs output formats that can be set using FMT2FS. The output data is in 32-bit 2s complement format. However, when external inputs (EXID1, EXID2, EXILRCK, EXIBCK) are selected, the signals are output asis in through mode regardless of the format setting. (1) MSB-first left-justified 32-bit (FMT2FS = “L”) (1/2fs) F2LRCK F2BCK F2** 31 30 29 28 MSB 2 1 0 LSB Rch(F2SLR, F2FLREX1) SubWoofer(F2CSWEX2) 31 30 29 28 2 1 0 31 30 Lch(F2SLR, F2FLREX1) Center(F2CSWEX2) F2**: F2SLR, F2FLREX1, F2CSWEX2 pins I I If more than 32 bit clock cycles are input during each word clock cycle HIGH-level or LOW-level interval, data following the 32nd bit are output as “0”. When F2LRCK and F2BCK are set as outputs, there are 32 fixed bit clock cycles per word clock cycle HIGH-level or LOW-level interval. (2) IIS 32-bit (FMT2FS = “H”) (1/2fs) F2LRCK F2BCK F2** 1 0 31 30 29 MSB 4 3 2 1 0 LSB Rch(F2SLR, F2FLREX1) SubWoofer(F2CSWEX2) 31 30 29 4 3 2 1 0 31 Lch(F2SLR, F2FLREX1) Center(F2CSWEX2) F2**: F2SLR, F2FLREX1, F2CSWEX2 pins I In this format, there are 32 bit clock cycles per word clock cycle regardless of the input/output settings. SEIKO NPC CORPORATION —13 SM5816AF Data Output Selection PCM output selection The PCM output and decimation filter processing is set using SEL8FS and SELEXT, as shown in the following table. PCM output system Setting 8fs output SEL8FS L L H SELEXT L H L or H F8** “0” “0” DSI** F8WCK F8BCK invalid invalid 8fs valid F2SLR DSISL DSISR “0” “0” 2fs output F2FLREX1 DSIFL DSIFR EXID1 “0” F2CSWEX2 DSICT DSISW EXID2 “0” F2LRCK F2BCK 2fs valid EXILRCK EXIBCK invalid Clock output CKOUT MCK EXIMCK MCK 2fs 480th-order invalid 8fs 240th-order Filter processing Note. F8**: F8FL, F8FR, F8SL, F8SR, F8CT, F8SW, F8SBL, F8SBR pins DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins I I The 8fs/2fs select setting (SEL8FS) takes precedence over the 2fs output external data setting (SELEXT). The 8fs/2fs word clock (F8WCK, F2LRCK) and bit clock (F8BCK, F2BCK) are output, even when not selected (“invalid”), in output mode when external input is not selected. 8-channel subwoofer/surround back output switching The DSD output and 8fs PCM output are set using SELSBSW and SELSBR, and the subwoofer output can be switched between surround back left and right channels. PCM output system Setting DSD output SELSBSW L H H I 8fs PCM output DSOSBR Mute Pattern Mute Pattern DSOSW F8SW F8SW “0” “0” F8SBL “0” F8SW F8SW F8SBR “0” “0” F8SW SELSBR L or H L H DSOSW DSOSW Mute Pattern Mute Pattern DSOSBL Mute Pattern DSOSW DSOSW The DSD mute output has a 50% duty “55h” continuous mute pattern. SEIKO NPC CORPORATION —14 SM5816AF Clock Input/Output Selection and Synchronization Operation DSD clock input/output switching The DSD input bit clock (DSBCKF) and DSD output bit clock (DSBCKB) are switched using DIRDSCK1, 2 as shown in the following table. Setting DIRDSCK1 L L H H DIRDSCK2 L H L H DSBCKF IN (Slave) IN (Slave) OUT (Master) OUT (Master) I/O state DSBCKB OUT (Master) IN (Slave) OUT (Master) IN (Slave) Reference connection diagram (1) DIRDSCK1, 2 = (L, L) Front-end device DSBCKF SM5816AF DSBCKB Back-end device (2) DIRDSCK1, 2 = (L, H) Front-end device DSBCKF SM5816AF DSBCKB Back-end device (3) DIRDSCK1, 2 = (H, L) Front-end device DSBCKF SM5816AF DSBCKB Back-end device (4) DIRDSCK1, 2 = (H, H) Front-end device DSBCKF SM5816AF DSBCKB Back-end device Note. In mode (1) and (4) in the diagram above, the input clocks are output as-is in through mode. PCM clock input/output switching The 8fs and 2fs word/bit input/output clocks can be switched using DIR8CK and DIR2CK. Note when external data is selected using SEL8FS and SELEXT, F2LRCK and F2BCK become outputs despite the state of DIR2CK, so care must be taken with external connections. The I/O settings for the data output mode selected are shown in the following table. Mode setting Mode SEL8FS 2fs L SELEXT L H L EXT L H H L 8fs H L or H H IN (invalid) H IN (Slave) OUT (EXILRCK, EXIBCK) OUT (clock output) H L IN (invalid) OUT (Master) IN (Slave) OUT (EXILRCK, EXIBCK) H L IN (invalid) OUT (clock output)1 DIR2CK L 2fs clock I/O state F2LRCK F2BCK OUT (Master) DIR8CK L 8fs clock I/O state F8WCK F8BCK OUT (clock output) 1. When external data is output in 2fs mode, MCK stops and the 8fs clock output stays stopped. SEIKO NPC CORPORATION —15 SM5816AF Input clock sync operation and resynchronization The data output internal operation and interface processing occur as event driven operations using the word clock word boundary as the event trigger, hence the output signals are always synchronized regardless of the word clock and bit clock I/O state. As regards DSD input, the data (BUF_A) on the rising edge of bit clock (DSBCKF) and data (BUF_B) one half of the bit clock period later are selected and read in when the DSD output and PCM output event starts, to avoid the transitions in the DSD input signal. At this time, the sync operation that determines which data was read in, after the INIT and SYNC rising edge, occurs when the word clock word boundary is detected after the first DSBCKF falling edge. SNYC/INIT ;;;; ;;;; ;;;; ;;;; DSI** ;;;; ;;;; ;;;; D (n) ;;;;;;;; ;;;;;;;; ;;;;;;;; D (n+1);;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; D (n+2) ;;;;;;;; D (n+3);;;;;;;; D (n+3) ;;;; ;;;;;;;; ;;;;;;;; ;;;; ;;;;;;;; ;;;;;;;; DA (n+2) ;;;;;;;; ;;;;;;;; DA (n+3) ;;;; ;;;; DSBCKF ;;;;;;;; ;;;;;;;;;;;;;; DA (n+1) DA (n) ;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; (BUF_B) ;;;;;;;;;;;;;; DB (n) DB (n-1) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; (IN_PHASE) ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; (DSD_SEL) ;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Select "BUF_B") ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; (BUF_A) DSBCKB DSO** (PCM_SEL) F8WCK /F2LRCK (Filter Input) DB (n+1) DB (n+2) DB (n+2) Select "BUF_A" ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; DB (n) DB (n-2) DB (n-1) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Select "BUF_A") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; DA (n+1) ;;;;;;;;;; DA (n-1) DA (n) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; DA (n+2) DA (n+3) (Word boundary edge) DB (n+1) DB (n+2) DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins DSO**: DSOFL, DSOFR, DSOSL, DSOSR, DSOCT, DSOSW, DSOSBL, DSOSBR pins Figure 1. Input timing sync operation due to INIT, SYNC 1) After the SYNC/INIT rising edge is detected, the phase reference signal (IN_PHASE) for the input data buffer selected is determined on the first DSBCKF falling edge. 2) Then, after the IN_PHASE transition, the subsequent data buffer is determined on the first DSBCKB edge and F8WCK/F2LRCK word boundary edge. (The input data buffer selection for DSD output and PCM output is independent.) Synchronization adjustment due to INIT/SYNC edge may cause 1 DSD data bit to be lost or made redundant due to input/output clock phase difference. If this would be problem, individual outputs should be muted for the following intervals. [DSD output] 4 DSBCKB (64fs) clock cycles [8fs PCM output] 34 F8WCK (8fs) clock cycles [2fs PCM output] 18 F2LRCK (2fs) clock cycles SEIKO NPC CORPORATION —16 SM5816AF 2fs PCM select external input data and external system clock output switching (1) Switching to external input data When SELEXT goes from LOW to HIGH, F2FLREX1 and F2CSWEX2 PCM data outputs are directly switched from EXID1 and EXID2 inputs. Similarly, F2LRCK and F2BCK are directly switched, regardless of the DIR2CK setting, from EXILRCK and EXIBCK inputs. (2) Switching to external system clock The CKOUT output is switched from MCK or EXIMCK inputs, according to the state of SELEXT SELEXT = “L”: MCK output SELEXT = “H”: EXIMCK output However, both MCK and EXIMCK should not be stopped during the switching interval to avoid a momentary pulse from occurring when switching. Also, the switching interval, from initial setting until both clocks have each switched 4 times, has a LOWlevel pulse that continues longer than the clock pulsewidth of each input clock. After the switching operation finishes, the unused clock input may be stopped. MCK ON EXIMCK SELEXT O FF (MCK OFF) CKOUT (Switching time) (EXIMCK ON) Figure 2. MCK → EXIMCK switching MCK EXIMCK F OF SELEXT (EXIMCK OFF) CKOUT (Switching time) ON (MCK ON) Figure 3. EXIMCK → MCK switching SEIKO NPC CORPORATION —17 SM5816AF Decimation Filter Selection The decimation filter coefficient set can be selected from 5 sets of fixed coefficients (8fs: 4 sets, 2fs: 1 set) and 1 set of programmable coefficients (8fs or 2fs). The coefficient set is selected using SELRAM and SELFIR1,2. Fixed coefficient selection The fixed coefficients are selected when SELRAM = “L”. The filter characteristic is 240th-order for 8fs, and 480th-order for 2fs. When 8fs PCM output is selected, 4 sets of characteristic filter coefficients are available for selection using SELFIR1, 2. SELFIR2 L L H H SELFIR1 L H L H coeff1 coeff2 coeff3 coeff4 Filter characteristic NPC standard filter 40kHz cutoff filter 50kHz cutoff filter 70kHz cutoff filter RAM coefficient selection A RAM coefficient set is selected when SELRAM = “H”. Initially, the data in RAM is indeterminate, so coefficient data must first be written to the RAM. While data is being written to RAM, the result of any RAM coefficient operation is not guaranteed, hence a fixed coefficient set should be used before switching to RAM coefficients or the PCM outputs should be muted. The RAM supports 29-bit × 240 words for combined 8fs and 2fs output. The filter characteristic is 240th-order for 8fs, and 480th-order for 2fs. The filter structure uses an even number order of symmetrical coefficients, reducing by half the number of coefficients to write to RAM. The coefficient data for 8fs and 2fs is in 29-bit 2s complement format. Details about writing coefficient data are described in “RAM coefficient write mode”. DSD Gain Switching The DSD signal 50% level can be set to 0dB, in 8fs/2fs output modes, using DSGAIN. DSGAIN = “L” : 100% modulation = 0dB (PCM) DSGAIN = “H” : 50% modulation = 0dB (PCM) *+ 6dB internal amplification 0dB when DSGAIN="L" [7FFFFFFFh] 0dB when DSGAIN="H" +1.0 +0.5 [7FFFFFFFh] 0 [00000000h] [00000000h] -0.5 [80000000h] -1.0 [80000000h] Figure 4. DSD modulation level Note. With DSGAIN = “H” and 50% DSD modulation or greater, a limiter is needed to prevent output signal clipping. SEIKO NPC CORPORATION —18 SM5816AF Dither Rounding Function In 8fs PCM output mode with 24-bit right-justified format only, a dither function (TPDF)* can be added to the output. The dither ON/OFF and rounding bit position are set by SELDH1 and SELDH2. After the initial setting is made, rounded data is output 2 words later. *: Triangular Probability Density Function SELDH2 L L H H SELDH1 L H L H Dither OFF Dither ON: 1 LSB (Bit 0) Dither ON: 2 LSB (Bit 1) Dither ON: 4 LSB (Bit 2) Function Mute Function The DSD outputs and PCM outputs can be muted independently. Muting is applied directly to the outputs. (1) DSD mute The DSD outputs are directly muted by a 50% duty (55h) pattern. XMTDSD = “L” : all DSD outputs with muting ON XMTDSD = “H” : all DSD outputs with muting OFF (2) PCM mute The PCM outputs are directly muted with value “0”. XMTPCM = “L” : all PCM outputs muting ON XMTPCM = “H” : all PCM outputs muting OFF Monitor Function The internal status changes can be monitored using the monitor pin. The MONTOR pin goes HIGH whenever any of the following parameter conditions occur. I I I SEL8FS changes state SELEXT changes state SELRAM, SELFIR1, 2 changes state The MONTOR pin is reset to LOW using the INIT or SYNC inputs. SEIKO NPC CORPORATION —19 SM5816AF CPU Interface Timing diagrams The CPU interface comprises 3-wire serial inputs MDATA, MSHIFT, and MLATCH. I I MDATA bit data is read into an internal interface buffer on the rising edge of MSHIFT. When MLATCH goes LOW, data is latched and processed. At this point, the data read on the previous MSHIFT rising edge is treated as bit 1, and the most recently input data bits are valid bits. I The internal processing mode is determined by the state of bit 1. • Bit 1 = “L”: system set mode (16 valid bits) • Bit 1 = “H”: RAM coefficient write mode (40 valid bits) bit40 MDATA MSHIFT MLATCH 40 39 38 37 36 10 9 8 7 6 5 4 3 bit1 2 1 Figure 5. Timing diagram System setting mode (bit 1 = “L”) In system set mode, each bit represents a function set flag, with the first 16 bits being valid. Each flag function, when SELMCU is HIGH, performs the same function as the pin with the same name, while the state of those pins is ignored. Table 1. Flag set function table Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Flag name MODE SEL8FS SELEXT (Reserved) (Reserved) SELSBSW SELSBR SELRAM SELFIR1 8fs FIR fixed coefficient 1-4 select SELFIR2 SELDH1 Dither rounding setting SELDH2 DSGAIN MTPCM MTDSD SYNC DSD signal gain setting PCM signal mute DSD signal mute Forced sync SELDH (2, 1) Dither (L, L) OFF (L, H) 1LSB (H, L) 2LSB (H, H) 4LSB “L” “L” “L” “L” “L” SELFIR (2, 1) FIR coeff (L, L) coeff 1 (L, H) coeff 2 (H, L) coeff 3 (H, H) coeff 4 “L” “L” Function System set mode select PCM output data select 2fs PCM external data output select (Reserved) (Reserved) Subwoofer output select Surround back Rch output select Fixed/RAM coefficient select – 8fs PCM output External data select – – Surround back output Both Lch, Rch outputs RAM coefficient “H” Tied "L" 2fs PCM output 2fs PCM output Tied "L" Tied "L" Subwoofer output Lch output only Fixed coefficient “L” Default – “L” “L” “L” “L” “L” “L” “L” “L” 50% modulation = 0dB Mute-OFF Mute-OFF Resync when "L" → "H" 100% modulation = 0dB Mute-ON Mute-ON Note. All 16 bits need to be written even when only changing one portion of the data. SEIKO NPC CORPORATION —20 SM5816AF RAM coefficient write mode (bit 1 = “H”) In RAM coefficient write mode, the bit represent a RAM write address and coefficient write data, with the first 40 bits of data being valid. Table 2. Flag function table Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Flag name MODE (Reserved) (Reserved) COEF28 COEF27 COEF26 COEF25 COEF24 COEF23 COEF22 COEF21 COEF20 COEF19 COEF18 COEF17 COEF16 COEF15 COEF14 COEF13 COEF12 COEF11 COEF10 COEF9 COEF8 COEF7 COEF6 COEF5 COEF4 COEF3 COEF2 COEF1 COEF0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 Function RAM coefficient write mode Reserved flag Reserved flag Coefficient data (MSB) Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data Coefficient data (LSB) RAM write address (MSB) RAM write address RAM write address RAM write address RAM write address RAM write address RAM write address RAM write address (LSB) Coefficient address should be assigned as follows. * Even-order symmetrical coefficients restriction means that only half need be written from the edges to the center. * For 2fs, half 480th-order implies to address 240. RA = (00)h is the edge, RA = (EF)h is the center. * For 8fs, half 240th-order implies to address 120. RA = (00)h, the edge, to RA = (3B)h are the first 60 addresses RA = (80)h to RA = (BB)h are the last 60 addresses. Coefficient data must conform with the following conditions. * Coefficient word length = 29 bits (± 1.0) * Coefficient sum total not to exceed 0.5 (18000000)h to (07FFFFFF)h * Depending on the coefficient, the result may pass the overflow limit. * RAM initial state is indeterminate, thus address-field data must be written before use. Tied "H" Tied "L" Tied "L" Value or state Note. Writing RAM coefficients always takes precedence. As a result, coefficient writing while a RAM coefficient is selected, will mean the coefficients are read incorrectly, generating an output noise. To prevent this problem, the outputs should be muted when writing RAM coefficients or a ROM coefficient should be temporarily selected. SEIKO NPC CORPORATION —21 SM5816AF FFh EFh (Center) BBh (Center) 8fs Mode Last 60 word RAM space 2fs Mode 240word 80h 3Bh 8fs Mode First 60 word 00h 00h (Edge) 00h (Edge) Figure 6. Usable address space diagram (Edge) (Center) 2fs Mode 00h (60) 3Bh 80h (240) EFh (120) BBh 480th order 8fs Mode 00h 240th order Figure 7. Filter coefficient example of RAM address (RA) assignment Note that in 8fs mode, the usable address area is separated into 2 portions. SEIKO NPC CORPORATION —22 SM5816AF Pin-control/Flag-control Relation Table System setting Description Function Control method select Initialization control DSD data input clock (DSBCKF) I/O select DSD data output clock (DSBCKB) I/O select 8fs data output clock (F8BCK, F8WCK) I/O select 2fs data output clock (F2BCK, F2LRCK) I/O select 8fs PCM data format select 8fs PCM word clock format select 2fs PCM data format select PCM output data select 2fs PCM external data output select Subwoofer output select Surround Back Rch output select Fixed/RAM coefficient select “H” Serial I/F control Normal operation Output (Master) Input (Slave) Input (Slave) Input (Slave)1 Pin control Initialize and resync Input (Slave) Output (Master) Output (Master) Output (Master) “L” Pin control Pin name SELMCU INIT DIRDSCK1 DIRDSCK2 DIR8CK DIR2CK FMT8FS FMT8WCK FMT2FS SEL8FS SELEXT SELSBSW SELSBR SELRAM SELFIR1 8fs FIR fixed coefficient 1-4 select SELFIR (2, 1) FIR coeff (L, L) coeff 1 (L, H) coeff 2 (H, L) coeff 3 (H, H) coeff 4 SELFIR2 SELDH1 Dither rounding setting SELDH (2, 1) Dither DSD signal gain setting PCM signal mute DSD signal mute Forced sync (L, L) OFF (L, H) 1LSB (H, L) 2LSB (H, H) 4LSB SELDH2 DSGAIN XMTPCM XMTDSD SYNC 37 5 74 75 78 SELDH2 DSGAIN MTPCM MTDSD SYNC 12 13 14 15 16 “L” “L” “L” “L” “L” 73 38 SELFIR2 SELDH1 10 11 “L” “L” No. 8 79 69 70 22 39 23 24 42 76 77 6 7 71 72 Serial I/F control Flag name – – – – – – – – – SEL8FS SELEXT SELSBSW SELSBR SELRAM SELFIR1 Bit Default – – – – – – – – – 2 3 6 7 8 9 – – – – – – – – – “L” “L” “L” “L” “L” “L” MSB-first right-justified 24-bit MSB-first left-justified 32-bit “L” → “H” (falling edge word boundary) IIS 32bit 8fs PCM output External data select Surround Back output Both Rch, Lch select RAM coefficient “H” → “L” (rising edge word boundary) MSB-first left-justified 32-bit 2fs PCM output 2fs PCM output Subwoofer output Lch output only Fixed coefficient 50% modulation = 0dB Mute-OFF Mute-OFF Resync when "L" → "H" 100% modulation = 0dB Mute-ON Mute-ON 1. In 2fs PCM mode, when external inputs are selected for output(SELEXT="H"), the DIR2CK setting is inactive, and F2BCK, F2LRCK are output. SEIKO NPC CORPORATION —23 SM5816AF Initialization Operation When power is applied, the INIT pin must be held LOW for the rated time to initialize the device. Initialization sets all the CPU interface system control registers to their default values, and the outputs have the states as described below. Pin DSD data outputs 8fs PCM data outputs 2fs PCM data outputs DSBCKF, DSBCKB F8BCK F8WCK F2BCK All “L” All “L” In internal 2fs output mode, all “L” In external data output mode, output as-is in through mode When both output modes are set, “H” When one input mode is set, through mode output In output mode, “H” In output mode using FMT8WCK = “L”, “L” In output mode using FMT8WCK = “H”, “H” In internal data output mode, “H” In external data output mode, external bit clock is output in through mode In left-justified 32-bit output mode, “L” In IIS output mode, “H” In external data output mode, external word clock is output in through mode MCK or EXIMCK, whichever is selected, is output in through mode Cleared to “L” State F2LRCK CKOUT MONTOR When INIT goes “H”, the sync adjustment operation described in section “Input clock sync operation and resynchronization” starts. Also, if DSD or PCM output is muted, the mute condition continues as-is until released. SEIKO NPC CORPORATION —24 SM5816AF BUILT-IN FILTER CHARACTERISTICS 64fs → 2fs Mode 0 0 -10 -20 -30 -40 -50 -60 -70 dB -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 30 40 50 60 70 80kHz 64fs → 8fs Mode 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150kHz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 dB Coeff3 50k Coeff1 50k Coeff2 40k Coeff4 70k Note. These characteristics were obtained by simulation. SEIKO NPC CORPORATION —25 SM5816AF TYPICAL APPLICATION CIRCUITS Surround Processor 2fs-32bit/IIS Multi-channel SA-CD Decoder CXD2752R DSD-PCM converter SM5816 DSP (Surround Processing etc.) DAC Analog LPF DSD-to-PCM Conversion Reproduction 8fs-24bit/32bit Multi-channel SA-CD Decoder CXD2752R DSD-PCM converter SM5816 8fs Processing (Volume etc.) DAC Analog LPF SEIKO NPC CORPORATION —26 SM5816AF Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp NC0108CE 2006.04 SEIKO NPC CORPORATION —27