SM5819HQF

SM5819HQF 6-channel DSD-PCM Converter OVERVIEW The SM5819HQF is a 6-channel DSD data (64fs) to 4fs, 2fs or fs PCM data converter. During conversion, decimation filtering is performed using a filter with selectable fixed coefficients (3 sets). Also, DSD inputs and PCM outputs are available for use in master/slave clock mode operation, in a wide range of system configurations, making it easy to construct a multi-channel DSD/PCM reproduction system. FEATURES I PINOUT (Top view) EXILRCK EXICSW EXIMCK EXIBCK EXISLR EXIFLR TOUT2 26 I 36 35 34 33 32 31 30 29 28 27 25 I I I I SEL1FS SEL4FS SELEXT DSGAIN XMTPCM I I I PACKAGE DIMENSIONS (Unit: mm) 9 ± 0.4 7 ± 0.1 + 0.075 0.125 − 0.025 I I 7 ± 0.1 9 ± 0.4 APPLICATIONS I I TEST1 TEST2 VDDH VDDL I 512fs (22.5792MHz, fs = 44.1kHz), 1:2 to 2:1 duty master clock DSD input and PCM output clock master/slave switching 3-system external data input (3-wire format), PCM output data/BCK/LRCK external input and internal filter output switching (BCK and LRCK are common to all 3 external PCM data inputs) Decimation filter coefficients • Fixed coefficients: 4fs-1/2fs-1/fs-1 PCM output mute operation PCM output format: [MSB-first left-justified 32bit] or [IIS 32-bit] (IIS 32-bit output bit clock frequency = 64 × word clock frequency) FIR filter coefficients • 64fs → 4fs/2fs/fs: 960th-order (6-channel) • ROM coefficients: 24 valid data bits (4-bit MSB extension at 4fs, 5-bit MSB extension at 2fs/fs) +6dB DSD gain switching function External/Internal system clock output switching 3.3V (3.0 to 3.6V) and 2.5V (2.3 to 2.7V) power supplies −40 to 85°C operating temperature range 48-pin QFP package VDDH VDDL MCK VSS VSS VDDL DSBCK DSIFL DSIFR DSICT DSISW DSISL DSISR DIRDSCK SYNC INIT VSS 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 VSS POFLR POCSW POSLR PLRCK PBCK VDDH MCKOUT VSS FMTPCM DIRPCK VDDL TEST3 10 TOUT1 11 VSS 12 1 2 3 4 5 6 7 8 9 Multi-channel SA-CD players SA-CD-compatible AV amplifiers 1.4 ± 0.1 ORDERING INFORMATION Device SM5819HQF Package 48 -pin QFP + 0.09 0.18 − 0.05 0.5 0.08 1.7 MAX 0 ~ 10 NIPPON PRECISION CIRCUITS INC.—1 0.1 0.5 ± 0.2 SM5819HQF PIN DESCRIPTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Name VDDL SEL1FS SEL4FS SELEXT DSGAIN XMTPCM VDDH TEST1 TEST2 TEST3 TOUT1 VSS VDDL DIRPCK FMTPCM VSS MCKOUT VDDH PBCK PLRCK POSLR POCSW POFLR VSS VDDL TOUT2 MCK VSS EXIMCK VDDH EXIBCK EXILRCK EXISLR EXICSW EXIFLR VSS VDDL DSBCK I/O − I I I I I − I I I O − − I I − O − I/O I/O O O O − − O I − I − I I I I I − − I/O Property1 − PD PD PD PD PD − PD PD PD − − − PD PD − 12mA − S, 6mA S, 6mA 2mA 2mA 2mA − − − − − − − S S − − − − − S, 6mA Input voltage 2.5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V − − 2.5V 3.3V 3.3V − − 3.3V 3.3V 3.3V − − − − 2.5V − 3.3V − 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V − 2.5V 3.3V Core power supply PCM output rate select 1 L: 2fs/4fs, H: fs PCM output rate select 2 L: 2fs, H: 4fs fs/2fs/4fs output and external data output select L: fs/2fs/4fs data, H: external data (EXI**) DSD signal gain setting L: 100% modulation = 0dB, H: 50% modulation = 0dB PCM output mute control input L: Mute ON, H: Mute OFF I/O power supply Test input 1 (must be open or tie LOW for normal operation) Test input 2 (must be open or tie LOW for normal operation) Test input 3 (must be open or tie LOW for normal operation) Test output 1 Ground Core power supply PCM output PBCK/PLRCK I/O select L: Output (master mode), H: Input (slave mode) PCM output format select L: MSB-first left-justified 32-bit, H: IIS 32-bit Ground System clock output (selected by SELEXT) I/O power supply PCM output BCK bit clock PCM output LRCK word clock PCM data output: surround left/right-channel PCM data output: center/subwoofer channel PCM data output: front left/right-channel Ground Core power supply Test output 2 Master clock input: 512fs (22.5792MHz, fs = 44.1kHz) Ground External system clock input I/O power supply External PCM data BCK bit clock input External PCM data LRCK word clock input External PCM data input: surround left/right-channel External PCM data input: center/subwoofer channel External PCM data input: front left/right-channel Ground Core power supply DSD data input bit clock. Controlled by DIRDSCK Description NIPPON PRECISION CIRCUITS INC.—2 SM5819HQF Input voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V − DSD data input: front left-channel DSD data input: front right-channel DSD data input: center channel DSD data input: subwoofer channel DSD data input: surround left-channel DSD data input: surround right-channel DSBCK I/O select L: input (slave), H: output (master) Forced synchronization input (active-HIGH edge) Initialization input: Active-LOW, Resync on “L” → “H” Ground No. 39 40 41 42 43 44 45 46 47 48 Name DSIFL DSIFR DSICT DSISW DSISL DSISR DIRDSCK SYNC INIT VSS I/O I I I I I I I I I − Property1 − − − − − − PD S, PU S, PU − Description 1. S = Schmitt, PU = pull-up resistor, PD = pull-down resistor, mA = output current NIPPON PRECISION CIRCUITS INC.—3 SM5819HQF BLOCK DIAGRAM DSIFL DSIFR DSICT DSISL DSISR DSISW FIR FILTER and DOWN SAMPLING UNIT PCM MUTE PCM I/F DSGAIN SEL1FS SEL4FS FMTPCM ROM 24bit 1440word (fs 480w) (2fs 480w) (4fs 480w) POFLR INT/EXT. DATA SELECT POSLR XMTPCM POCSW EXIFLR EXISLR EXICSW SELEXT EXILRCK EXIBCK EXIMCK INT/EXT. CLOCK SELECT SYNC INIT DIRDSCK DSBCK MCK CLOCK GENERATOR and TIMING CONTROL (Internal Clocks) PLRCK PBCK MCKOUT DIRPCK TEST1 TEST2 TEST3 TEST CONTROL TOUT1 TOUT2 NIPPON PRECISION CIRCUITS INC.—4 SM5819HQF SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Supply voltage 1 Supply voltage 2 Input voltage (3.3V) Power dissipation Storage temperature range Symbol VDDH VDDL VIN PD TSTG Rating –0.3 to 4.0 –0.3 to 3.0 –0.3 to VDDH + 0.5 200 –55 to 125 Unit V V V mW °C Recommended Operating Conditions VSS = 0V Parameter Supply voltage 1 Supply voltage 2 Operating temperature Symbol VDDH VDDL TOPR Rating 3.0 to 3.6 2.3 to 2.7 –40 to 85 Unit V V °C DC Electrical Characteristics VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = –40 to 85°C unless otherwise noted. Parameter Current consumption 1 Current consumption 2 Input voltage “H" level “L" level Positive Negative Pin VDDH VDDL (*1) (*1) (*2) (*2) (*2) "H" level Output voltage "L" level Input leakage current Pull-down resistor Pull-up resistor (*3) (*1, 2) (*4) (*5) VOL ILI RPD RPU VI = VDDH VI = VSS (*3) Symbol IDDH IDDL VIH VIL VT+ VT– VH VOH IOH = –2mA (Type1) IOH = –6mA (Type2) IOH = –12mA (Type3) IOL = +2mA (Type1) IOL = +6mA (Type2) IOL = +12mA (Type3) Condition Rating min – – 2.0 – 1.1 0.6 0.1 VDDH – 0.4 typ – – – – – – – – max 5 60 – 0.8 2.4 1.8 – – Unit mA mA V V V V V V All pins no load VDDH = 3.6V VDDH = 3.0V Schmitt-trigger voltage Hysteresis voltage – –5 60 60 – – 120 120 0.4 5 288 288 V µA kΩ kΩ Pin summary (*1) (*2) Input pins and bidirectional (input/output) pins in input mode Inputs with Schmitt characteristic and bidirectional (input/output) pins in input mode Output pins and bidirectional (input/output) pins in output mode Type 3: MCKOUT Type 2: DSBCK, PBCK, PLRCK Type 1: Outputs excluding those above Inputs with pull-down resistor Inputs with pull-up resistor (*3) (*4) (*5) NIPPON PRECISION CIRCUITS INC.—5 SM5819HQF AC Electrical Characteristics VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = –40 to 85°C, fs = 44.1kHz unless otherwise noted. When DSBCK and PLRCK clocks are supplied by external clock input, their frequencies are related to the MCK input frequency by the following frequency divider ratios. (DSBCK) cycle = 8 × MCK cycle (64fs) (PLRCK) cycle [4fs mode] = 128 × MCK cycle (4fs) (PLRCK) cycle [2fs mode] = 256 × MCK cycle (2fs) (PLRCK) cycle [fs mode] = 512 × MCK cycle (fs) System clock I MCK pin Rating Parameter Symbol min typ – – 44.29 (1/512fs) – max – – – 10 ns ns ns ns tMCWH tMCWL tMCY t r , tf 13 13 40 – Unit "H"-level pulsewidth "L"-level pulsewidth Pulse cycle Rise/fall time tMCY tMCWH tMCWL MCK tr tf 0.9VDDH 0.5VDDH 0.1VDDH External system clock I EXIMCK pin Rating Parameter Symbol min typ – – – – max – – – 10 ns ns ns ns tECWH tECWL tECY ter , tef 13 13 40 – Unit "H"-level pulsewidth "L"-level pulsewidth Pulse cycle Rise/fall time tECY tECWH EXIMCK ter tef tECWL 0.9VDDH 0.5VDDH 0.1VDDH NIPPON PRECISION CIRCUITS INC.—6 SM5819HQF DSD input I I DSBCK pin DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins Rating Parameter Symbol min typ 177.16 354.31 (1/64fs) – – max – – – – ns ns ns ns tDSCW tDSCY tDSS tDSH 150 300 50 50 Unit DSD clock pulsewidth DSD clock pulse cycle DSD data setup time DSD data hold time tDSCY tDSCW DSBCK tDSCW tDSS DSI** tDSH DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins Note. DSD clock pulsewidth and DSD clock pulse cycle when DSBCK is in input mode. Note. The data, with DSBCK timing above, enters the internal circuits on the falling edge of the MCK clock. Consequently, if the timing changes, the circuit must be resynchronized using INIT or SYNC. NIPPON PRECISION CIRCUITS INC.—7 SM5819HQF PCM output I PLRCK, PBCK, POFLR, POSLR, POCSW pins Rating Parameter 4fs Symbol min 40 tPBCW 40 40 80 tPBCY 80 80 tPLBS tPLBH tPBDLY tPLDLY 30 10 0 0 typ 44.29 88.58 177.15 88.58 (1/256fs) 177.15 (1/128fs) 354.31 (1/64fs) – – – – max – – – – – – – – 15 15 ns ns ns ns ns ns ns ns ns ns Unit BCK clock pulsewidth 2fs fs 4fs BCK clock pulse cycle 2fs fs Word CK setup time Word CK hold time Bit CK data delay time Word CK data delay time tPBCY tPBCW PBCK tPBCW tPLBH PLRCK tPLBS tPLDLY PO** tPBDLY PO**: POFLR, POSLR, POCSW pins Note. The PCM output relationship applies when the external inputs (EXI**) are not in through mode. Note. fs/2fs/4fs bit clock and word clock relationship applies when PBCK and PLRCK are in input mode. NIPPON PRECISION CIRCUITS INC.—8 SM5819HQF Clock outputs I MCKOUT, DSBCK, PLRCK, PBCK pins Rating Parameter Symbol min typ – – max 10 10 ns ns tCKODLY tCKDLY 0 0 Unit MCKOUT output delay time Word/bit clock output delay time MCK tCKODLY MCKOUT tCKDLY Word/Bit clock outputs tCKODLY Note. Applies when MCK clock is output on MCKOUT in through mode. Note. Applies when each word/bit clock on DSBCK, PBCK, PLRCK is in output mode. Through-mode output I MCKOUT, PBCK, PLRCK, POFLR, POSLR, POCSW pins Through inputs EXIMCK EXIBCK EXIWCK EXIFLR EXISLR EXICSW Through outputs MCKOUT PBCK PLRCK PCM outputs with external inputs selected POFLR POSLR POCSW 15 15 15 ns ns ns Condition tTHDLY MAX 10 10 10 Unit ns ns ns Through mode input tTHDLY Through mode output tTHDLY NIPPON PRECISION CIRCUITS INC.—9 SM5819HQF Initialization and resynchronization I INIT, SYNC pins Rating Parameter Symbol min typ – – max – – ns ns tINTM tSYCW 6 × tMCY 6 × tMCY Unit Initialization time Resynchronization pulsewidth VDDH 3.0V tINTM INIT tINTM tSYCW SYNC NIPPON PRECISION CIRCUITS INC.—10 SM5819HQF FUNCTIONAL DESCRIPTION Data Input/Output Formats DSD input format DSD input data is read in on the rising edge of the DSBCK bit clock. (1/64fs) DSBCK DSI** DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins PCM output format The PCM output format can be assigned to either of two types below using FMTPCM. The output data is in 32bit 2s complement form. The PLRCK and PBCK frequencies are set in response to the fs/2fs/4fs switch mode. However, when external inputs are selected, the inputs are passed to the output in through mode, regardless of the assigned format. (1) MSB-first left-justified 32-bit (FMTPCM = “L”) (1/fs, 1/2fs, or 1/4fs) PLRCK PBCK PO** 31 30 29 28 MSB 2 1 0 LSB Lch (POSLR, POFLR) Center (POCSW) Rch (POSLR, POFLR) SubWoofer (POCSW) 31 30 29 28 2 1 0 31 30 PO**: POFLR, POSLR, POCSW pins I I If more than 32 bit clock cycles are input during a word clock cycle HIGH-level or LOW-level pulse, all bits after the 32nd bit are output as “0”. When PLRCK and PBCK are set to output mode, the number of bit clock cycles during a word clock HIGHlevel or LOW-level pulse is fixed at 32. (2) IIS 32-bit (FMTPCM = “H”) (1/fs, 1/2fs, or 1/4fs) PLRCK PBCK PO** 1 0 31 30 29 MSB Lch (POSLR, POFLR) Center (POCSW) 4 3 2 1 0 LSB Rch (POSLR, POFLR) SubWoofer (POCSW) 31 30 29 4 3 2 1 0 31 PO**: POFLR, POSLR, POCSW pins I In this format, there are 32 bit clock cycles per word clock cycle regardless of the input/output settings. NIPPON PRECISION CIRCUITS INC.—11 SM5819HQF Data Output Selection PCM output selection The PCM output and decimation filter processing is set by SEL4FS, SEL1FS and SELEXT, as shown in the following table. Setting SEL1FS L L H L or H I I I PCM output system SELEXT L L L H POFLR DSIFL DSIFR DSIFL DSIFR DSIFL DSIFR EXIFLR POSLR DSISL DSISR DSISL DSISR DSISL DSISR EXISLR POCSW DSICT DSISW DSICT DSISW DSICT DSISW EXICSW PLRCK PBCK 4fs 2fs fs EXILRCK EXIBCK Clock output MCKOUT MCK MCK MCK EXIMCK Filter processing SEL4FS H L L or H L or H 4fs 960th-order 2fs 960th-order fs 960th-order Invalid The external data setting (SELEXT) has priority over the 4fs/2fs/fs selection setting (SEL1FS, SEL4FS). Also, the fs setting (SEL1FS) has priority over the 4fs/2fs setting (SEL4FS). In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set to HIGH, it may clip depending on signal. Therefore, please use at DSGAIN = LOW. Clock Input/Output Selection and Resynchronization Operation DSD clock input/output switching The DSD input bit clock (DSBCK) can be switched between input and output by DIRDSCK. Setting DIRDSCK L H I/O state DSBCK Input (Slave) Output (Master) PCM clock input/output switching The PCM output word clock (PLRCK) and bit clock (PBCK) can be switched between input and output by DIRPCK. Setting DIRPCK L H I/O state PLRCK PBCK Output (Master) Input (Slave) However, when external data is selected using SELEXT, the clocks PLRCK and PBCK are switched to outputs, regardless of the DIRPCK setting, thus care must be exercised with external connections. NIPPON PRECISION CIRCUITS INC.—12 SM5819HQF Input clock sync operation and resynchronization The internal computation and interface processing for data output is event driven, with the word boundary edge of the word clock as the trigger. This ensures the output signals are synchronized, regardless of the word clock and bit clock input/output settings. The DSD input comprises data read into a buffer on the rising edge of the DSBCK bit clock (BUF_A) and data in another buffer internally delayed by half a bit clock cycle (BUF_B), and then a buffer is selected when the PCM output event occurs in order to avoid DSD input signal transitions. Synchronization of whichever data buffer is selected occurs when the word boundary edge of the word clock is detected after the first DSBCK falling edge following a rising edge on INIT or SYNC. SNYC/INIT ;;;; ;;;; ;;;; ;;;; DSI** ;;;; ;;;; ;;;; D (n) ;;;;;;;; ;;;;;;;;D (n+1) ;;;;;;;; D (n+2) ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; D (n+3) ;;;;;;;; D (n+3) ;;;;;;;; ;;;;;;;; ;;;;;;;; DA (n+3) ;;; ;;; ;;; ;;; ;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;; ;;;;;;;;;;;;;;; DA (n+1) DA (n+2) DA (n) ;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;; (BUF_B) ;;;;;;;;;;;;;; DB (n-1) DB (n) DB (n+1) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; (IN_PHASE) ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (PCM_SEL) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Select "BUF_A") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (BUF_A) PLRCK (Filter Input) DSBCK DB (n+2) DB (n+2) (Word boundary edge) DB (n+1) DB (n+2) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; DA (n+1) ;;;;;;;;;; DA (n-1) DA (n) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins Figure 1. Input timing synchronization operation using INIT and SYNC 1) On the first DSBCK falling edge after a rising edge of SYNC or INIT, (IN_PHASE) is a phase reference signal for input data buffer selection. 2) Then, the input data buffer selected is determined by the logic level of IN_PHASE when the first PLRCK word boundary edge is detected. When synchronization is adjusted using INIT or SYNC (resynchronization), 1 DSD data unit may be lost or repeated depending on the phase difference between input/output clocks. The individual outputs should be muted by a minimum interval, given below, to avoid these data glitches. [4fs PCM output] 36 clock cycles in PLRCK (4fs) mode [2fs PCM output] 18 clock cycles in PLRCK (2fs) mode [fs PCM output] 10 clock cycles in PLRCK (fs) mode NIPPON PRECISION CIRCUITS INC.—13 SM5819HQF External input data and external system clock output switching (1) Switching to external input data When SELEXT is switched LOW to HIGH, the PCM data output is immediately switched to external input data. PLRCK and PBCK are similarly switched immediately to EXILRCK and EXIBCK in through mode, respectively, regardless of the DIRPCK setting. (2) Switching to external system clock The MCKOUT system clock output can be switched between MCK and EXIMCK using SELEXT, as given below. SELEXT = “L”: MCK output SELEXT = “H”: EXIMCK output Note that neither MCK nor EXIMCK clock should be stopped during the switching interval to prevent a micro-pulse being generated when switching. The switching interval lasts from when SELEXT changes state until both clocks have made 4 transitions. During this interval, the LOW-level clock pulsewidth of the first clock is extended until the rising edge of the second clock occurs. When the switching interval ends, the unused clock may then be stopped. MCK ON EXIMCK SELEXT O FF (MCK OFF) (EXIMCK ON) MCKOUT (Switching time) Figure 2. MCK → EXIMCK switching MCK EXIMCK OF SELEXT F (EXIMCK OFF) MCKOUT (Switching time) ON (MCK ON) Figure 3. EXIMCK → MCK switching NIPPON PRECISION CIRCUITS INC.—14 SM5819HQF DSD Gain Switching The PCM output can be adjusted such that 0dB corresponds to 50% modulation level DSD input signal using DSGAIN, as given below. DSGAIN = “L” : 100% modulation = 0dB (PCM) DSGAIN = “H” : 50% modulation = 0dB (PCM) * with +6dB internal amplification 0dB when DSGAIN="L" [7FFFFFFFh] 0dB when DSGAIN="H" +1.0 +0.5 [7FFFFFFFh] 0 [00000000h] [00000000h] -0.5 [80000000h] -1.0 [80000000h] Figure 4. DSD modulation level Note. When DSGAIN = “H”, note that any input DSD signal with modulation of 50% level or higher will be amplitude limited, resulting in output signal clipping. Note. In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set to HIGH, it may clip depending on signal. Therefore, please use at DSGAIN = LOW. Mute Function The PCM outputs can be muted using XMTPCM, as given below. Muting is applied immediately before output. When PCM muting is set ON, the PCM outputs are directly set to value “0”. XMTPCM = “L” : all PCM outputs muting ON XMTPCM = “H” : all PCM outputs muting OFF The mute function is only active for internal computation of fs/2fs/4fs output. It is inactive for external input to output connection in through mode. Initialization Operation The power must be applied in order of VDDL and VDDH. Please avoid the continuous power supply injection of only VDDH. (less than 1 second) After power is applied, INIT must be held LOW for the rated interval to initialize the device. During initialization, the outputs have the following states. Pin PCM data outputs DSBCK PBCK state LOW in internal data output mode External input to output connection in through mode HIGH in output (master) mode HIGH in internal data output mode External bit clock input to output connection in through mode LOW in 32-bit left-justified output mode HIGH in IIS output mode External word clock input to output connection in through mode MCK or EXIMCK, whichever is currently selected. PLRCK MCKOUT When INIT goes HIGH, synchronization operation begins as described in the section “Input clock sync operation and resynchronization”. Note that if the PCM signal muting is ON during initialization, muting operation continues until it is released. The system clock input on MCK must be applied during initialization. NIPPON PRECISION CIRCUITS INC.—15 SM5819HQF BUILT-IN FILTER CHARACTERISTICS Filter Mode Cutoff Characteristics 0 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10 20 30 40 50 60 70 80 90 100 [kHz] fs 2fs 4fs [dB] 0 1 10 20 30 40 50 60 70 [kHz] 0 -1 fs 2fs 4fs [dB] -2 -3 -4 -5 NIPPON PRECISION CIRCUITS INC.—16 SM5819HQF Filter Mode Ripple Characteristics 0 -0.008680 -0.008682 -0.008684 -0.008686 -0.008688 [dB] -0.008690 -0.008692 -0.008694 -0.008696 -0.008698 -0.008700 5 10 15 20 25 30 35 40 45 50 [kHz] fs 2fs 0 0.000010 0.000008 0.000006 0.000004 0.000002 [dB] 0.000000 -0.000002 -0.000004 -0.000006 -0.000008 -0.000010 5 10 15 20 25 30 35 40 45 50 [kHz] 4fs Note. In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set to HIGH, it may clip depending on signal. Therefore, please use at DSGAIN = LOW. NIPPON PRECISION CIRCUITS INC.—17 SM5819HQF Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: sales@npc.co.jp NC0407AE 2004.10 NIPPON PRECISION CIRCUITS INC.—18