SM5838AS

SM5838AS NIPPON PRECISION CIRCUITS INC. 5120 × 8-bit Synchronous FIFO OVERVIEW The SM5838AS is a 5120 × 8-bit synchronous FIFO (first in, first out) high-speed line buffer. Internally, it employs static CMOS circuits which mean that it effectively has limitless data hold times. It can operate at speeds up to 33.3 MHz (normal-voltage specification). The SM5838AS can be used to easily realize a 1-line delay in high-speed facsimile machines and digital copiers. PINOUT (TOP VIEW) DOUT0 1 24 DIN0 23 DIN1 22 DIN2 21 DIN3 DOUT1 2 DOUT2 3 DOUT3 4 S M5 8 3 8 AS OE 5 RR 6 VSS 7 20 WE 19 RW 18 VDD 17 CLK 16 DIN4 15 DIN5 14 DIN6 13 DIN7 FEATURES s s s RE 8 s s s s s s 5120 × 8-bit structure Variable-length delay (21 to 5120 bits) 33.3 MHz high-speed operation (normal-voltage specification) All input/outputs TTL compatible Independent read enable and output enable pins, allowing read address pointer increment in output data hold and output high-impedance states Supply voltage • 4.5 to 5.5 V (normal-voltage specification) • 3.0 to 4.5 V (low-voltage specification) 24-pin SOP package Molybdenum-gate CMOS process A3-paper 1-line (16 dots/mm) compatible DOUT4 9 DOUT5 10 DOUT6 11 DOUT7 12 PACKAGE DIMENSIONS 24-pin SOP (Unit: mm) 15.8TYP 0.6MAX 11.8 0.3 8.4TYP 0 10 1.0 0.2 + 0.10 + 0.08 0.915 1.27 0.1 0.4 - 0.05 0.17 - 0.07 0.10MIN 2.5MAX NIPPON PRECISION CIRCUITS—1 SM5838AS BLOCK DIAGRAM Output buffer S/P converter P/S converter Input buffer DIN 8 32 8 SRAM 32 8 8 DOUT Cache OE Decoder WE RW Write address pointer Read address pointer RE RR CLK PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name DOUT0 DOUT1 DOUT2 DOUT3 OE RR VSS RE DOUT4 DOUT5 DOUT6 DOUT7 DIN7 DIN6 DIN5 DIN4 CLK VDD RW WE DIN3 DIN2 DIN1 DIN0 I/O O O O O I I – I O O O O I I I I I – I I I I I I Read data output bit 0 Read data output bit 1 Read data output bit 2 Read data output bit 3 Output enable input Reset read input Ground (0 V) pin Read enable input (read address pointer) Read data output bit 4 Read data output bit 5 Read data output bit 6 Read data output bit 7 Write data input bit 7 Write data input bit 6 Write data input bit 5 Write data input bit 4 Clock input Supply pin Reset write input Write enable input (write address pointer) Write data input bit 3 Write data input bit 2 Write data input bit 1 Write data input bit 0 Function NIPPON PRECISION CIRCUITS—2 SM5838AS SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage range Input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol V DD VIN T stg PD T sld tsld Condition Rating −0.3 to 7.0 V SS − 0.3 to VDD + 0.3 −40 to 125 500 255 10 Unit V V °C mW °C s Recommended Operating Conditions VSS = 0 V Rating Parameter Symbol Condition min Normal-voltage specification Supply voltage range Operating temperature V DD Topr Low-voltage specification 4.5 3.0 −20 typ 5.0 3.3 – max 5.5 4.5 70 V V °C Unit DC Characteristics 5 V supply Parameter Operating current consumption Standby current consumption Input leakage current2 Input leakage current3 Input voltage2 Input voltage3 Output high-impedance leakage current4 Output voltage4 Symbol Condition min IDD IST ILH ILL V IH V IL IZH IZL VOH VOL OE = HIGH, VOUT = VDD OE = HIGH, VOUT = 0 V IOH = −1 mA IOH = 2 mA V IN = VDD V IN = 0 V No output load1 – – – – 2.4 – – – 2.5 – typ 75 – – – – – – – – – max 90 50 1 1 – 0.5 5 5 – 0.4 min – – – – 2.0 – – – 2.0 – typ 22 – – – – – – – – – max 30 50 1 1 – 0.5 5 5 – V 0.8 mA µA µA µA V V µA 3 V supply Unit 1. Normal-voltage specification (CLK = 33.3 MHz); Low-voltage specification (CLK = 20 MHz, V DD = 3.3 ± 0.3 V) 2. Pins CLK, RR and RE . 3. Pins DIN0 to DIN7, RW, WE and OE . 4. Pins DOUT0 to DOUT7. Input/Outputs Ta = 25°C, f = 1 MHz Rating Parameter Input capacitance Output capacitance Symbol CI CO Condition min – – typ – – max 10 10 pF pF Unit NIPPON PRECISION CIRCUITS—3 SM5838AS AC Characteristics Input timing 5 V supply Parameter Clock cycle time Clock pulsewidth Input data setup time Input data hold time RW and RR setup time RW and RR hold time WE setup time WE hold time RE setup time RE hold time OE setup time OE hold time Rise and fall transition times Symbol tCK tCKW tDS tDH tRS tRH tWES tWEH tRES tREH tOES tOEH t T Condition min 30 13 7 3 10 0 13 0 13 0 10 0 – typ – – – – – – – – – – – – – max – – – – – – – – – – – – 30 min 50 23 10 4 17 0 23 0 23 0 17 0 – typ – – – – – – – – – – – – – max – – – – – – – – – – – – 30 ns ns ns ns ns ns ns ns ns ns ns ns ns 3 V supply Unit 1. All voltages measured with relative to V S . S 2. Input timing input voltage levels are VL = 0 V and VIH = 3.0/2.5 V (5/3 V supply). Transition time is measured between VIH and VIL. I 3. Input signal reference level is V H = 1.5 V. T 4. Input timing ratings measured with t = 5 ns. T Normal-voltage (5 V) specification 3.0V 0V 5ns t CK t CKW CLK t CKW t RS RW t RH t RS RR t RH t WEH WE t REH RE t OEH OE t OES t RES t WES t RR t RW 5ns Low-voltage (3 V) specification 2.5V 0V 5ns 5ns t RH t RS t RH t RS t WEH t WES t REH t RES t OEH t OES DIN ,,,,,, ,,,,,, ,,,,,, ,,,,,, t DS ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, t DH t DS ,,,,,, ,,,,,, ,,,,,, ,,,,,, NIPPON PRECISION CIRCUITS—4 t DH SM5838AS Output timing 5 V supply Parameter Access time Output hold time Output enable delay time1 Output disable delay time1 Symbol tA tOH tZO tOZ “Load circuit 2” 5 – 27 5 – 40 ns Condition min – “Load circuit 1” 5 5 – – – 27 5 5 – – – 40 ns ns typ – max 20 min – typ – max 40 ns 3 V supply Unit 1. tZO and tOZ are measured with ±200 mV tolerance. Normal-voltage (5 V) specification 2.0V Low-voltage (3 V) specification 1.8V 0.8V 1.0V t CK t CKW CLK t CKW t OEH OE t OES t OEH t OES DOUT t OH ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, tA Hi-Z t OZ ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t ZO RR="H" ,RE="L" tA Load circuit 1 VDD 1.8k Ω DOUT 1.1kΩ Load circuit 2 VDD 1.8kΩ DOUT 30pF 1.1kΩ 5pF NIPPON PRECISION CIRCUITS—5 SM5838AS FUNCTIONAL DESCRIPTION At power-ON reset, device operation can become irregular during the interval when the control circuits are being reset. After power-ON reset is released, this can take up to several 10s of ms in some cases. Write Reset Cycle, Read Reset Cycle After power-ON, the write address pointer and read address pointer positions are undefined. Accordingly, it is necessary to initialize the pointers using a write reset cycle and read reset cycle, respectively. A write reset cycle (read reset cycle) is valid when RW (RR) goes LOW for an interval that satisfies Write reset cycle n cycle reset cycle 0 cycle 1 cycle both the CLK rising edge setup time (tRS) and hold time (tRH). Note that a write reset cycle (read reset cycle) can occur simultaneously with a write cycle (read cycle). If the cycles are not simultaneous, then the write reset cycle (read reset cycle) is completed at the start of the next write cycle (read cycle). t CKW CLK t CKW t RS t RW t RH t RS t DS (0) RW t RH DIN (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t DS (n) ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, t DH ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, WE="L" t DH (1) Read reset cycle n cycle reset cycle 0 cycle 1 cycle t CKW CLK t CKW t RS t RR t RH t RS RR DOUT (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t RH tA (n) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t OH tA (0) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t OH tA (0) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t OH RE="L" , OE="L" tA (1) Note the even if a reset period (tRW, tRR) is zero length in the write reset and read reset cycles, the reset operation does take place. NIPPON PRECISION CIRCUITS—6 SM5838AS Write Cycle The input data address is determined by the write address pointer position. The write address pointer is reset by RW (write reset cycle), and is incremented on the rising edge of CLK whenever WE is LOW. Data input occurs on the rising edge of CLK at the end of the write cycle. When WE goes HIGH, write operation is disabled and the write address pointer stops. n cycle t CKW n+1 cycle disable cycle n+2 cycle CLK t CKW t WEH t WES t WEH t WES WE DIN (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t DS (n) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t DH t DS (n+1) ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, t DH RW="H" (n+2) Read Cycle The output data address is determined by the read address pointer position. The read address pointer is reset by RR (read reset cycle), and is incremented on the rising edge of CLK whenever RE is LOW. Data output starts tA (max) after the rising edge of CLK at the start of the read cycle and continues until tOH (min) after the next rising edge of CLK. When RE goes HIGH, read operation is disabled and the read address pointer stops. Note that data being read was written at least 20 write cycles previously (FIFO minimum delay). Therefore, if (write address pointer) − (read address pointer) = 1 to 19, then a possibility exists that data from the preceding line is output instead. n cycle t CKW n+1 cycle disable cycle n+2 cycle CLK t CKW t REH t RES t REH t RES RE DOUT (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, tA (n) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t OH tA (n+1) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t OH RR="H" , OE="L" tA (n+2) NIPPON PRECISION CIRCUITS—7 SM5838AS Output Enable When OE is HIGH, DOUT0 to DOUT7 become high impedance. Note that because RE operation is independent of OE operation, the read address pointer can be incremented even when the outputs are high impedance. n cycle n+1 cycle n+2 cycle n+3 cycle t CKW CLK t CKW t OEH OE t OES t OEH t OES ,,,,,,, DOUT (n-1) ,,,,,,, ,,,,,,, ,,,,,,, tA (n) Hi-Z ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t ZO RR="H" ,RE="L" tA (n+3) t OZ TYPICAL APPLICATIONS Note that at power-ON, the write address pointer and read address pointer positions are undefined. Accordingly, RW and RR reset cycles are required. 1H Delay Line A 5120-word delay line can be realized by performing simultaneous write reset and read reset at powerON. An n-word delay line (21 to 5210-word) can be realized using any of the following methods. 1H (5120-word) delay line timing 1H 5119 cycle 5120+0 cycle 5120+1 cycle 2H 5120+2 cycle 5120+3 cycle 1. Perform reset in sync with desired delay length. 2. Stagger RW and RR timing to desired delay length. 3. Manipulate the write or read address pointer using WE or RE to disable incrementing to maintain sync with desired delay length. 0 cycle 1 cycle 2 cycle CLK t RS RW RR t RH DIN ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, t DS t DH 0 ,,, ,,, ,,, ,,, ,,, 1 DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 5120 cycle ,,, ,,, ,,, ,,, ,,, 2 ,,, ,,, 5118 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 5119 tA ,,, ,,, ,,, ,,, ,,, 0 t OH 0 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 3 ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, 1 2 3 WE="L" , RE="L" , OE="L" NIPPON PRECISION CIRCUITS—8 SM5838AS n-word delay line timing 1 1H n-1 cycle n+0 cycle n+1 cycle 2H n+2 cycle n+3 cycle 0 cycle 1 cycle 2 cycle CLK t RS RW RR t RH ,,,,,,,,,, ,,, ,,, ,,, ,,,,,,,,,, ,,, ,,, ,,, n-2 ,,, n-1 ,, ,,, ,, DIN ,,,,,,,,,, 0 ,,, 1 ,,, 2 ,,, ,,, ,, ,,,,,,,,,, ,,, ,,, ,,, ,,, ,, ,,,,,,,,,, ,,, ,,, ,,, ,,, ,, t n cycle ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, A t DS t DH 0 t OH 0 ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, 1 1 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 2 2 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 3 3 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, WE="L" , RE="L" , OE="L" n-word delay line timing 2 1H n-1 cycle n+0 cycle n+1 cycle 2H n+2 cycle n+3 cycle 0 cycle 1 cycle 2 cycle CLK t RS RW t RS RR t RH t RH DIN ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, t DS t DH 0 ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, n cycle 2 ,,, ,,, ,,, ,,, n-2 ,,, ,,, ,,, ,,, n-1 ,, ,, ,, ,, tA 0 ,, ,, ,, ,, t OH 1 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 3 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, n-word delay line timing 3 1H n-1 cycle n+0 cycle 0 ,, ,, ,, ,, 1 2 3 WE="L" , RE="L" , OE="L" 2H n+1 cycle n+2 cycle n+3 cycle 0 cycle 1 cycle 2 cycle CLK t RS RW RR t RES RE t RH DIN ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, t DS t DH 0 ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, n cycle 2 ,,, ,,, ,,, ,,, n-2 ,,, ,,, ,,, ,,, n-1 ,, ,, ,, ,, tA 0 ,, ,, ,, ,, t OH 1 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 3 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 0 ,, ,, ,, ,, 1 2 3 WE="L" , RE="L" , OE="L" NIPPON PRECISION CIRCUITS—9 SM5838AS High-speed Conversion For example, an NTSC signal interlace-to-noninterlace conversion. If interpolated line data can be assumed to be similar to the preceding line data and the write data rate is 14.3 MHz (4fSC), then conversion can be realized by reading twice at 28.6 MHz (8fSC). Furthermore, interpolated line data, with appropriate signal processing separation, can be read out line-byPreceding line data used as interpolated line 012345 CLK WE RW nH DIN RE OE RR nH-1H DOUT 012345 909 nH 012345 909 * nH 012345 909 nH+1H 012345 909 * 0 1 2 909 0 1 2 nH+1H 909 1819 012 line by alternating between 2 SM5838AS devices (1 line/device). In reality, however, double the number of devices are required for luminance signal (Y) and color difference signal (C) systems. And triple the number of devices are required for RGB signal systems. *Output data 867 to 909 forms the preceding 1H data. Interpolated data used as interpolated line 1819 012345 CLK WE RW nH (A)DIN 0 1 2 nH' (B)DIN (A)RE (A)OE (A)RR nH (A)DOUT 012345 909 * (B)RE (B)OE (B)RR nH'-1H (B)DOUT 012345 909 nH' 012345 909 nH+1H 012345 909 * 0 1 2 909 0 1 2 909 0 1 2 nH'+1H 909 nH+1H 909 012 *Output data 867 to 909 forms the preceding 1H data. NIPPON PRECISION CIRCUITS—10 SM5838AS 1/2 Data Reduction Input data rate reduction by half can be realized by taking WE and RE simultaneously HIGH only once every two clock cycles. Noninterlace-to-interlace conversions line extraction can be realized by switching WE LOW/HIGH in line units and RE LOW/HIGH in word units. 1/2 data reduction 5119 012345 CLK WE RW nH DIN 0123456789 5119 RE OE RR nH-1H DOUT 0 2 4 6 8 10 12 14 5118 0 2 4 6 8 nH 10 12 14 5118 nH+1H 0123456789 5119 012 1/2 line extraction (noninterlace-to-interlace conversion) 1819 012345 CLK WE RW nH-1H DIN 012345 909 RE OE RR nH-2H DOUT 0 1 2 909 0 1 2 nH 909 nH 012345 909 nH+1H 012345 909 nH+2H 012345 909 012 NIPPON PRECISION CIRCUITS—11 SM5838AS 1/2n data reduction (n × n pixel reduction) Screen resolution reduction, or 2 × 2 pixel reduction, can be realized by combining both 1/2 data reduction and 1/2 line extraction schemes. Furthermore, n × n pixel reduction (for integer n) can be realized by changing the WE and RE disable intervals and the RW and RR reset timing. 2 × 2 pixel reduction (1/4 reduction) 2 pixels 2 pixels Valid Invalid Also, if the same data is repeatedly read out in place of other data that has been discarded, the screen resolution can be reduced without changing the data rate to realize a mosaic filter function. Invalid Invalid 909 012345 CLK WE RW nH-1H DIN 012345 909 RE OE RR nH-2H DOUT 0 2 908 0 2 nH 908 nH 012345 909 nH+1H 012345 909 nH+2H 012345 909 2 × 2 pixel reduction (mosaic) 2 pixels 2 pixels Valid 909 012345 CLK WE RW nH-1H DIN 012345 909 RE OE RR nH-2H DOUT 0 2 4 6 908* 0 nH-2H 2 4 908 0 2 nH 4 6 908* 0 2 nH 4 908 nH 012345 909 nH+1H 012345 909 nH+2H 012345 909 *Output date 902 to 908 forms the preceding 1H data. NIPPON PRECISION CIRCUITS—12 SM5838AS Wipe Function (Screen Switching) Because RE and OE operate independently, a screen wipe function can be realized using 2 SM5838AS devices by switching OE LOW/HIGH in field units. Screen wipe (OE changes in field units) 909 012345 CLK WE RW nH-1H (A)DIN 012345 909 nH'-1H (B)DIN 012345 909 (A)RE (A)OE (A)RR nH-2H (A)DOUT 45 909 (B)RE (B)OE (B)RR nH'-2H (B)DOUT 0123 0123 nH'-1H 0123 nH' 0123 nH'+1H nH-1H 45 909 nH 45 909 nH+1H 45 909 nH' 012345 909 nH 012345 909 nH'+1H 012345 909 nH+1H 012345 909 nH'+2H 012345 909 nH+2H 012345 909 Screen wipe image (left to right) (B) (A) NIPPON PRECISION CIRCUITS—13 SM5838AS NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9411AE 1996.09 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—14