SM5843AS1

SM5843A×1 NIPPON PRECISION CIRCUITS INC. Audio Multi-function Digital Filter OVERVIEW The SM5843A×1 is a multi-function digital filter IC, fabricated using NPC’s Molybdenum-gate CMOS process, for digital audio reproduction equipment. It features 8-times oversampling (interpolation), digital deemphasis and soft muting functions. It accepts 16, 18, or 20-bit input data, and outputs data in 18 or 20bit format. It operates using either a 384fs or 256fs system clock. s s s s s 5 V supply Crystal oscillator circuit built-in TTL-compatible input/outputs 28-pin plastic DIP and SOP Molybdenum-gate CMOS APPLICATIONS s s s CD players DAT players PCM systems FEATURES s s s s s s s s s Filter configuration (2-channel processing) • 8-times oversampling (interpolation) - 3-stage FIR configuration • Deemphasis filter - IIR filter configuration for correct gain and phase characteristics - 2-channel independent ON/OFF control - 32/44.1/48 kHz sampling frequency (fs) • 21 × 22-bit parallel multiplier/25-bit accumulator for high precision • Overflow limiter 2 oversampling filter characteristics • Sharp roll-off characteristic (response 1) - ≤ ±0.00005 dB passband ripple (0 to 0.4535fs) - ≥ 110 dB stopband attenuation (0.5465fs to 7.4535fs) • Slow roll-off characteristic (response 2) - ≤ ±0.00003 dB passband ripple (0 to 0.235fs) - ≥ 77 dB stopband attenuation (0.745fs to 7.255fs) Soft muting Digital attenuator Input data format • 2s complement, MSB first - LR alternating, 16/18/20-bit serial, trailing data - LR alternating, 20-bit serial, leading data - LR simultaneous, 20-bit serial, leading data Output data format • 2s complement, MSB first, LR simultaneous • 18/20-bit serial • BCKO burst (NPC format) Dither processing ON/OFF control Jitter-free/Sync mode selectable 256fs/384fs system clock selectable • 21.2/14.2MHz maximum frequency (384fs/256fs) ORDERING INFOMATION Device SM5843AP1 SM5843AS1 Package 28pin DIP 28pin SOP NIPPON PRECISION CIRCUITS—1 SM5843A×1 PINOUT(TOP VIEW) 28-pin DIP PACKAGE DIMENSIONS(Unit: mm) 28-pin DIP DI / INF2N BCKI CKSLN INF1N IW1N / DIL XTI XTO VSS CKO IW2N / DIR MDT MDK MLEN RSTN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LRCI TMOD2 BCKO 13.8 0.2 0° to 15° 15.2 3.0MAX WCKO DOL DOR VDD TMOD1 SYNCN 3.8 0.1 + 0.30 1.5 − 0.05 37.3 0.3 OW20N FSEL2 FSEL1 DEMP MUTE 28-pin SOP 28-pin SOP DI / INF2N BCKI CKSLN INF1N IW1N / DIL XTI XTO VSS CKO IW2N / DIR MDT MDK MLEN RSTN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LRCI 0.6MAX. 3.2 0.2 7.7 0.5 2.54 0.45 0.1 TMOD2 BCKO WCKO 18.3 TYP DOR VDD TMOD1 SYNCN OW20N FSEL2 FSEL1 DEMP 0.45TYP. 1.27 ± 0.15 + 0.10 0.4 − 0.05 11.8 0.3 8.4TYP DOL 3.0MAX. 0.10MIN. 1.0 0.2 0° to 10° + 0.10 0.15 − 0.05 MUTE NIPPON PRECISION CIRCUITS—2 + 0.10 0.25 − 0.05 0° to 10° 4.5 0.3 SM5843AP1 SM5843AS1 SM5843A×1 BLOCK DIAGRAM CKSLN LRCI BCKI DI / INF2N IW1N / DIL IW2N / DIR XTI XTO CKO INF1N Input data Interface System Clock TOMD2 RSTN SYNCN Timing Controller Filter and Attenuation Arithmetic block TMOD1 DEMP FSEL1 FSEL2 Deemphasis Controller Output date Interface BCKO WCKO DOL MUTE Mute/ Attenuation Controller DOR OW20N MDT MCK MLEN VSS VDD NIPPON PRECISION CIRCUITS—3 SM5843A×1 PIN DESCRIPTION Number 1 2 3 Name DI/INF2N BCKI CKSLN I/O1 Ip Ip Ip Description Data input when INF1N is LOW, and input format select pin when INF1N is HIGH. Input bit clock Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW. Input format select pin. INF1N and INF2N select the pin functions below. Pin function selection INF1N LOW LOW HIGH HIGH DI/INF2N LOW LR alternating, trailing data HIGH LOW HIGH LR alternating, leading data INF2N LR simultaneous, leading data DIL DIR DI IW1N IW2N Input format DI/INF2N 4 INF1N Ip IW1N/DIL IW2N/DIR Input bit length select pin when INF1N is LOW, and left-channel data input when INF1N is HIGH. IW1N and IW2N select the input data length. INF1N IW2N/DIL LOW 5 IW1N/DIL Ip LOW HIGH HIGH HIGH 6 7 8 9 10 11 12 13 14 15 16 XTI XTO VSS CKO IW2N/DIR MDT MCK MLEN RSTN MUTE DEMP I O – O Ip Ip Ip Ip Ip Ip Ip Oscillator input connection Oscillator output connection Ground Oscillator output clock. Same frequency as XTI. Input bit length select pin when INF2N is LOW, and right-channel data input when INF2N is HIGH. IW1N and IW2N select the input data length as shown in the table for pin 5. Attenuator serial data input Attenuator bit clock input Attenuator latch enable input System reset. Reset operation when LOW, and normal operation when HIGH. Mute control signal. Muting when HIGH, and normal operation when LOW. Deemphasis control signal. OFF when LOW, and ON when HIGH. Deemphasis filter select inputs 17 FSEL1 Ip FSEL1 LOW LOW 18 FSEL2 Ip HIGH HIGH 19 20 21 22 OW20N SYNCN TMOD1 VDD Ip Ip Ip – FSEL2 LOW HIGH LOW HIGH Sampling frequency (fs) 44.1 kHz 48 kHz Test mode 32 kHz × LOW HIGH × 18 bits 16 bits 20 bits LOW IW1N/DIR LOW HIGH Input bit length 20 bits 20 bits Output bit length select pin. 20-bit output when LOW, and 18-bit output when HIGH. Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH. Dither processing control. ON when LOW, and OFF when HIGH. 5 V supply NIPPON PRECISION CIRCUITS—4 SM5843A×1 Number 23 24 25 26 27 28 Name DOR DOL WCKO BCKO TMOD2 LRCI I/O1 O O O O Ip Ip Right-channel data output Left-channel data output Output word clock Output bit clock Filter characteristic select pin. Sharp roll-off (response 1) when HIGH, and slow roll-off (response 2) when LOW. Input data sample rate (fs) clock Description 1. I = input, Ip = Input with pull-up resistor, O = output NIPPON PRECISION CIRCUITS—5 SM5843A×1 SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage range Input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol VDD VIN Tstg PD Tsld tsld Rating −0.3 to 7.0 −0.3 to VDD + 0.3 −40 to 125 550 (DIP) mW 390 (SOP) 255 10 °C s Unit V V °C Recommended Operating Conditions fs = 384fs (CKSLN = HIGH): VSS = 0 V Parameter Supply voltage range Operating temperature range Symbol VDD Topr Rating 4.5 to 5.5 −20 to 80 Unit V °C fs = 256fs (CKSLN = LOW): VSS = 0 V Parameter Supply voltage range Operating temperature range Symbol VDD Topr Rating 4.75 to 5.25 −20 to 70 Unit V °C DC Electrical Characteristics VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Current consumption XTI HIGH-level input voltage XTI LOW-level input voltage XTI AC-coupled input voltage HIGH-level input voltage2 LOW-level input voltage2 HIGH-level output voltage3 LOW-level output voltage3 XTI HIGH-level input current XTI LOW-level input current LOW-level input current2 Input leakage current2 Symbol IDD VIH1 VIL1 VINAC VIH2 VIL2 VOH VOL IIH IIL1 IIL2 ILH IOH = −0.4 mA IOL = 1.6 mA VIN = VDD VIN = 0 V VIN = 0 V VIN = VDD Condition min VDD = 5.0 V1 – 0.7VDD – 0.3VDD 2.4 – 2.5 – – – – – typ 50 – – – – – – – 10 10 10 – max 65 – 0.3VDD – – 0.5 – 0.4 20 20 20 1.0 mA V V Vp-p V V V V µA µA µA µA Unit 1. fSYS = 256fs = 14.2 MHz (CKSLN = LOW), no output load 2. Pins DI/INF2N, BCKI, CKSLN, INF1N, IW1N/DIL, IW2N/DIR, MDT, MCK, MLEN, RSTN, MUTE, DEMP, FSEL1, FSEL2, OW20N, SYNCN, LRCI, TMOD1, TMOD2 3. Pins CKO, DOL, DOR, BCKO, WCKO NIPPON PRECISION CIRCUITS—6 SM5843A×1 AC Electrical Characteristics Input Clock (XTI) Crystal oscillator fs = 384fs (CKSLN = HIGH): VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Oscillator frequency Symbol min fOSC 2.0 typ – max 21.2 MHz Unit fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Oscillator frequency Symbol min fOSC 1.0 typ – max 14.2 MHz Unit External clock input fs = 384fs (CKSLN = HIGH): VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Clock HIGH-level pulsewidth Clock LOW-level pulsewidth Clock pulse cycle time Symbol min tCWH tCWL tXI 20 20 47 typ – – – max 250 250 500 ns ns ns Unit fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Clock HIGH-level pulsewidth Clock LOW-level pulsewidth Clock pulse cycle time Symbol min tCWH tCWL tXI 30 30 70 typ – – – max 500 500 1000 ns ns ns Unit VlH1 XTI 0.5VDD VlL1 tCWH tXI tCWL NIPPON PRECISION CIRCUITS—7 SM5843A×1 Serial input timing (BCKI, DI, DIL, DIR, LRCI) VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth BCKI pulse cycle DIN setup time DIN hold time Last BCKI rising edge to LRCI edge LRCI edge to first BCKI rising edge Symbol min tBCWH tBCWL tBCY tDS tDH tBL tLB 50 50 100 50 50 50 50 typ – – – – – – – max – – – – – – – ns ns ns ns ns ns ns Unit tBCY tBCWH BCKI tBCWL 1.5V tDS DI DIL DIR tDH 1.5V tBL LRCI tLB 1.5V Reset timing (RSTN) VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Condition min At power-ON RST LOW-level reset pulsewidth tRST At all other times 1 50 typ – – max – – µs ns Unit NIPPON PRECISION CIRCUITS—8 SM5843A×1 Attenuator timing (MDT, MCK, MLEN) VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter MDT setup time MDT hold time MLEN setup time MLEN hold time MLEN LOW-level pulsewidth MLEN HIGH-level pulsewidth MLEN pulse cycle time Symbol min tMDS tMDH tMCS tMCH tMEWL tMEWH tMLEY 20 20 40 20 20 20 6 typ – – – – – – – max – – – – – – – ns ns ns ns ns ns tSYS1 Unit 1. tSYS = 1/384fs when CKSLN is HIGH, and 1/256fs when CKSLN is LOW. MDT 1.5V tMDS MCK tMDH 1.5V tMCS MLEN tMCH 1.5V tMEWL tMEWH tMLEY NIPPON PRECISION CIRCUITS—9 SM5843A×1 Output timing VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C, CL = 15 pF Rating Parameter XTI to XTO delay XTI to CKO delay XTI to BCKO delay (CKSLN = HIGH) Symbol tXTO tCKO tsbH tsbL XTI to BCKO delay (CKSLN = LOW) tsbH tsbL BCKO to DOL, DOR, WCKO delay tbdH tbdL CKO TODOL, DOR, WCKO delay tcdH tcdL XTO TODOL, DOR, WCKO delay txdH txdL Condition min XTI fall to XTO rise XTI fall to CKO fall XTI fall to BCKO rise XTI fall to BCKO fall XTI fall to BCKO rise XTI fall to BCKO fall BCKO fall to output rise BCKO fall to output fall CKO fall to output rise CKO fall to output fall XTO rise to output rise XTO rise to output fall 3 10 20 20 20 20 −5 −5 5 5 15 15 typ – – – – – – – – – – – – max 15 35 60 ns 60 60 ns 60 10 ns 10 25 ns 25 50 ns 50 ns ns Unit Tsys XTI (CKSLN = H) Tsys 0.5VDD tCKO CKO (CKSLN = H) Tsys XTI (CKSLN = L) 0.5VDD 1.5V tCKO CKO (CKSLN = L) 1.5V tsbH BCKO tsbL 1.5V tbdL tcdL XTO rising edge DOL DOR WCKO XTO rising edge 1.5V txdL tbdH tcdH 1.5V txdH NIPPON PRECISION CIRCUITS—10 SM5843A×1 Filter Characteristics 8-times interpolation filter (sharp roll-off: response 1) Parameter Passband Stopband Passband ripple Stopband attenuation Group delay1 SYNCN = LOW SYNCN = HIGH Condition Rating @ 256fs 0 to 0.4535fs 0.5465fs to 7.4535fs ≤ ±0.00005 dB ≥ 110 dB 44.625/fs 44.25/fs to 45.0/fs 1. The digital filter arithmetic computation time from when the completion of data input at rate fs to the start of data output at rate 8fs. 8fs filter response with deemphasis OFF 0 20 Attenuation (dB) 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency (×fs) 8fs filter band transition response with deemphasis OFF 0 20 Attenuation (dB) 40 60 80 100 120 140 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640 Frequency (×fs) 8fs filter passband response with deemphasis OFF -0.0001 Attenuation (dB) -0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500 Frequency (×fs) NIPPON PRECISION CIRCUITS—11 SM5843A×1 8-times interpolation filter (slow roll-off: response 2) Parameter Passband Stopband Passband ripple Stopband attenuation Group delay1 SYNCN = LOW SYNCN = HIGH Condition < 3 dB attenuation > 77 dB attenuation 0 to 0.235fs Rating @ 256fs 0 to 0.455fs 0.745fs to 7.255fs ≤ ±0.00003 dB ≥ 77 dB 25.625/fs 25.25/fs to 26.0/fs 1. The digital filter arithmetic computation time from when the completion of data input at rate fs to the start of data output at rate 8fs. 8fs filter response with deemphasis OFF 0 20 Attenuation (dB) 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency (×fs) 8fs filter band transition response with deemphasis OFF 0 20 Attenuation (dB) 40 60 80 100 120 140 0.00 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 Frequency (×fs) 8fs filter passband response with deemphasis OFF -2.0 Attenuation (dB) 0.0 2.0 4.0 6.0 0.000 0.125 0.250 0.375 0.500 Frequency (×fs) NIPPON PRECISION CIRCUITS—12 SM5843A×1 8fs filter passband response [amplitude gain enlarged] -0.0001 Attenuation (dB) -0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500 Frequency (×fs) Deemphasis filter Sampling frequency (fs) Parameter 32 kHz Passband bandwidth (kHz) Attenuation Deviation from ideal characteristic Phase, θ 0 to 14.5 44.1 kHz 0 to 20.0 ≤ ±0.001 dB 0 to 1.5° 48 kHz 0 to 21.7 Passband response with deemphasis ON (logarithmic frequency axis) 0 2 Attenuation (dB) 4 6 8 10 10 20 50 100 200 500 1k 2k 5k 10k Attenuation 32k A44.1k A48kHz 32kHz Phase 0 -20 Phase θ ( ° ) 44.1kHz 48kHz -40 -60 20k Frequency (Hz) Passband response with deemphasis ON (linear frequency axis) 0 2 Attenuation (dB) 4 6 8 10 0 4k 8k 12k Frequency (Hz) 16k 20k Attenuation 32k A44.1k A48kHz 32kHz -20 44.1kHz 48kHz -40 -60 22k 24k NIPPON PRECISION CIRCUITS—13 Phase θ ( ° ) Phase 0 SM5843A×1 FUNCTIONAL DESCRIPTION The basic arithmetic block is shown in figure 1, and the function of each block is described in the following sections. Input fs 2 - times oversampling 153 - tap (response 1 )or 25 - tap (response 2 ) FIR 2fs 2 - times oversampling 29 - tap FIR 4fs Deemphasis IIR filter Deemphasis ON Deemphasis OFF 4fs Mute function 4fs 2 - times oversampling 17 - tap FIR 8fs Output Figure 1. Arithmetic block diagram 8-times Oversampling (Interpolation) The interpolation arithmetic block is comprised of 3 cascaded, 2-times FIR interpolation filters, as shown in figure 1. The input signal is sampled at rate fs, and then 8times oversampling data is output. Sampling noise in the 0.5465fs to 7.4535fs stopband for the sharp rolloff (response 1) characteristic, 0.745fs to 7.255fs for the slow roll-off (response 2) characteristic, is removed by the interpolation filter. Digital Deemphasis The digital deemphasis filter has the same construction as analog filters. It is implemented as an IIR filter to faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters. The three sets of filter coefficients for the three fs = 32.0/44.1/48.0 kHz sampling frequencies are selected by FSEL1 and FSEL2 when the sampling frequency is specified, as shown in the following table. Deemphasis is ON when DEMP is HIGH, and OFF when DEMP is LOW. FSEL1 LOW LOW HIGH HIGH FSEL2 LOW HIGH LOW HIGH Sampling frequency (fs) 44.1 kHz 48 kHz Test mode 32 kHz Note that test mode is not available for operation. NIPPON PRECISION CIRCUITS—14 SM5843A×1 Soft Muting The muting function controls the muting of both left and right channels simultaneously. Muting is ON when MUTE is HIGH, muting is OFF when MUTE is LOW. When MUTE goes HIGH, the attenuation changes smoothly from 0 to −∞ dB in 512/fs, or approximately 11.6 ms when fs = 44.1 kHz. When MUTE goes LOW, muting is released and the attenuation changes smoothly from −∞ to 0 dB, again taking approximately 11.6 ms. MUTE L H L 0dB (Gain) −∞ 512 / fs 512 / fs Figure 2. Mute timing When RSTN goes LOW, the DOL and DOR outputs go LOW, immediately muting the output signal. Muting is released and timing is synchronized immediately after RSTN goes HIGH. Digital Attenuator (MDT, MCK, MLEN) The attenuation function is controlled by MDT, MCK and MLEN. MDT data, in 11-bit serial MSB first format, is shifted into an internal shift register on the rising edge of the serial data clock MCK. The B1 MDT a0 MSB MCK B2 a1 B3 a2 B4 a3 B5 a4 B6 a5 contents of the shift register are transferred to the internal processing circuits on the rising edge of the MLEN gate pulse. The attenuation data format is shown in figure 3. B7 a6 B8 a7 B9 B10 B11 a8 a9 a10 LSB MLEN Figure 3. Attenuation data format The attenuation register data DATT can take on any value between 0 and 1024 (400H). The attenuation is given by the following equation for both left and right channels simultaneously. Attenuation = 20 × log10(DATT/1024) [dB] Thus, the attenuation level is −∞ when DATT is 0, and attenuation is 0 dB when DATT is 1024. DATT is set to 1024 (400H) after system reset initialization. The attenuation data and attenuation level for sample DATT values are shown in the following table. Attenuation data DATT 000H 001H to 3FFH 400H Attenuation level (dB) −∞ −60.206 to −0.0085 0 NIPPON PRECISION CIRCUITS—15 SM5843A×1 Attenuation operation When an attenuation value DATT is set, the attenuation changes smoothly from the current attenuation level to the new level. The new attenuation data is stored in the attenuation register while the current attenuation data is stored in a temporary register. The attenuation then changes smoothly by ramping between the two register values, updating the temporary register with each step. If a new attenuation value for DATT is set before the previous target attenuation level is reached, the attenuation then ramps toward the new attenuation level. When MUTE is HIGH, the attenuation level is −∞. When MUTE goes LOW (muting OFF), the attenuation level returns to that of the original value of DATT. Setting1 DATT1 (Gain) −∞ MUTE DATT2 Setting2 L H Setting4 DATT4 DATT2 DATT3 Setting3 L Time Figure 4. Attenuation and mute timing System Clock (XTI, XTO, CKO, CKSLN) Two system clock frequencies, 384fs and 256fs, can be used. An external clock source can be input on XTI, or a crystal oscillator can be constructed by connecting a crystal between XTI and XTO. The system clock is also buffered and then output on CKO. The system clock frequency selection and the internal clock frequency are shown in the following table. CKSL Parameter HIGH XTI input clock frequency (fXI = 1/tXI) CKO clock frequency Internal clock frequency (tSYS) 384fs 384fs 2 × tXI LOW 256fs 256fs tXI to timing controller CKSLN XTI 1/2 Internal system clock (192fs or 256fs) XTO CKO Figure 5. Clock generator circuit NIPPON PRECISION CIRCUITS—16 SM5843A×1 Audio Data Input (INF1N, INF2N, IW1N, IW2N, DI, DIL, DIR, BCKI, LRCI) INF1N LOW LOW HIGH HIGH DI/INF2N LOW HIGH LOW HIGH Input format The input data format and several input pin functions are selected by the state of INF1N and INF2N. Pin function selection DI/INF2N IW1N/DIL IW1N IW2N/DIR IW2N LR alternating1, trailing data LR alternating, leading data LR simultaneous2, leading data DI INF2N DIL DIR 1. Alternating left-channel and right-channel data input on a single input DI. 2. Simultaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively. The input data word length is selected by the state of IW1N and IW2N when INF1N is LOW. 20-bit is selected when INF1N is HIGH. INF1N IW2N/DIL LOW LOW LOW HIGH HIGH HIGH × LOW HIGH × 18 bits 16 bits 20 bits IW1N/DIR LOW HIGH Input bit length 20 bits 20 bits exceeds a certain value. There are 2 timing error values at which resynchronization occurs, selected by the state of SYNCN. Jitter-free mode (SYNCN = HIGH) When SYNCN is HIGH, the timing error value is ±3/8 × (LRCI clock period). When the difference between the input timing and LRCI start edge position do not exceed this value, internal timing is not resynchronized and all functions continue to operate normally. Sync mode (SYNCN = LOW) When SYNCN is LOW, the timing error value is ±1 × (system clock period), which is a much smaller timing error tolerance than in jitter-free mode. In this mode, the internal timing is guaranteed to follow the LRCI clock timing within this tolerance, making this mode useful for systems constructed from a multiple number of SM5843A×1 devices. Note that resynchronization affects the internal operation and can generate a momentary click noise output. Jitter-free Function (SYNCN) The arithmetic circuit and output control timing is derived from the system clock, and is therefore independent of the input LRCI and BCKI clocks. Accordingly, any jitter in the data input clock (LRCI and BCKI) does not cause jitter in the output. Generally, the internal timing is synchronized to the LRCI input timing after a system reset release, when RSTN goes from LOW to HIGH, on the first LRCI clock start edge. If the input timing and LRCI start edge timing subsequently drift, the input timing is automatically resynchronized when the timing error Audio Data Output (DOL, DOR, BCKO, WCKO, OW20N) The output data is in serial, simultaneous left and right-channel, 2s complement, MSB first, BCKO burst (NPC format) format. The output data word length is selected by the state of OW20N. 18-bit output is selected when OW20N is HIGH, and 20-bit output when OW20N is LOW. 8fs serial data is output in sync with the falling edge of the internal system clock and BCKO clock. The number of BCKO bit clock pulses per word changes depending on the output bit length selected (18/20 bits). Consequently, output data is latched into the internal output register on the falling of the edge of an output word clock WCKO, which has timing independent of the number of output bits as specified in the following table. Parameter Bit clock rate Data word length Symbol TB TDW CKSLN = HIGH 1/192fs 24tSYS CKSLN = LOW 1/256fs 32tSYS NIPPON PRECISION CIRCUITS—17 SM5843A×1 System Reset (RSTN) The SM5843A×1 must be reset under the following conditions. s s s s s At power-ON. When the LRCI clock and internal operation timing need to be resynchronized. When switching the CKSLN clock select input. When switching between filter characteristics using TMOD2. When either or both of the LRCI and XTI clocks stop or are interrupted. and INF2N. When INF1N is LOW or when both INF1N and INF2N are HIGH, the start edge is the rising edge. When INF1N is HIGH and INF2N is LOW, the start edge is the falling edge. When RSTN is LOW, the DOL and DOR outputs are LOW, muting the output signal to an attenuation level of −∞. The power-ON reset pulse can be applied by a microcontroller or, for systems where XTI and LRCI are stable at power-ON, by connecting a capacitor of several hundred pF between RSTN and VSS. For systems that do not use a microcontroller, the capacitor must be chosen such that the XTI and LRCI clocks fully stabilize before RSTN goes from LOW to HIGH. The system is reset by applying a LOW-level pulse on RSTN. The arithmetic and output timing counters are reset on the first LRCI start edge after reset is released, as long as the XTI clock has already stabilized. The LRCI start edge is determined by the state of INF1N RSTN LRCI Internal reset WCKO 1 2 DOL DOR Figure 6. System reset timing and output muting Filter Characteristic Selection (TMOD2) There are 2 digital filter frequency response characteristics incorporated into the SM5843A×1, selected by the state of TMOD2. A sharp roll-off characteristic (response 1) is selected when TMOD2 is HIGH, and a slow roll-off characteristic (response 2) when TMOD2 is LOW. The response is modified by changing the number of taps in the 1st FIR filter stage, as shown in figure 1. s Dither Rounding-off Processing (TMOD1) Dither rounding-off processing of output data is ON when TMOD1 is LOW. Dither is OFF and normal processing mode is selected when TMOD1 is HIGH. s Filter response 1 • 153-tap 1st FIR • 29-tap 2nd FIR • 17-tap 3rd FIR Filter response 2 • 25-tap 1st FIR • 29-tap 2nd FIR • 17-tap 3rd FIR Note that the device should be reset when changing TMOD2 during normal operation. NIPPON PRECISION CIRCUITS—18 SM5843A×1 TIMING DIAGRAMS Input Timing Examples (DIN, BCKI, LRCI) 1 / fs Lch DATA (MSB) DI 1 2 (LSB) 14 15 16 (MSB) 1 2 Rch DATA (LSB) 14 15 16 BCKI LRCI Figure 7. LR alternating, trailing data, 16-bit input 1 / fs Lch DATA (MSB) DIL 1 2 3 (LSB) 19 20 Rch DATA (MSB) DIR BCKI LRCI 1 2 3 (LSB) 19 20 1 Data after lsb (bit 20) is ignored. After bit 20, BCKI clock input is not needed. Figure 8. LR alternating, leading data, 20-bit input 1 / fs (MSB) DIL 1 2 3 Lch DATA 4 5 6 18 (LSB) 19 20 (LSB) 18 19 20 1 1 (MSB) DIR 1 2 3 Rch DATA 4 5 6 BCKI LRCI Data after lsb (bit20) is ignored. After bit 20, BCKI clock input is not needed. Figure 9. LR simultaneous, leading data, 20-bit input NIPPON PRECISION CIRCUITS—19 SM5843A×1 Output Timing Examples (DOL, DOR, BCKO, WCKO) 24TB(TDW) System Clock DOL 1 2 3 4 17 18 19 20 (*) 1 2 3 4 DOR BCKO 1 2 3 4 17 18 19 20 (*) 1 2 3 4 TB TB WCKO 12TB 12TB The number of output bits is determined by the output bit length selected. Figure 10. 18/20-bit output (CKSL = HIGH) 32TB(TDW) System Clock DOL 1 2 3 15 16 17 18 19 20 (*) 1 2 DOR BCKO 1 2 3 15 16 17 18 19 20 (*) 1 2 WCKO TB TB 16TB 16TB The number of output bits is determined by the output bit length selected. Figure 11. 18/20-bit output (CKSL = LOW) NIPPON PRECISION CIRCUITS—20 SM5843A×1 Data Input to Output Delay Timing This is the digital filter arithmetic computation time from the completion of data input at rate fs (tINPUT) Filter response CKSLN LOW (256fs) HIGH Filter response 1 LOW HIGH (384fs) HIGH LOW LOW (256fs) HIGH Filter response 2 LOW HIGH (384fs) HIGH Jitter-free mode After reset + sync mode Jitter-free mode Jitter-free mode After reset + sync mode After reset + sync mode Jitter-free mode on the rising edge of LRCI to the start of data output at rate 8fs (tOUTPUT) on the falling edge of WCKO. Mode After reset + sync mode tOUTPUT − tINPUT 44.625/fs 44.25/fs − 45.0/fs 44.75/fs 44.375/fs − 45.125/fs 25.625/fs 25.25/fs − 26.0/fs 25.75/fs 25.375/fs − 26.125/fs SYNCN LOW 1/fs LRCI Serial data Input tINPUT WCKO (256fs) WCKO (384fs) 44/fs(Filter Response 1) 25/fs(Filter Response 2) tOUTPUT Serial data output tOUTPUT Serial data output Figure 12. Delay timing (SYNCN = LOW) 44.625/fs (Filter Response 1) tINPUT 25.625/fs (Filter Response 2) tOUTPUT tINPUT tOUTPUT Figure 13. Delay timing (SYNCN = CKSLN = LOW) NIPPON PRECISION CIRCUITS—21 SM5843A×1 APPLICATION CIRCUITS Input Interface Circuits CD decoder (CXD2500Q) connection C16M LRCK 16.9344MHz 44.1kHz XTI LRCI DI CKSLN SONY DA16 CD DECODER DA15 CXD2500Q PSSL EMPH SM5843 MUTE 2.1168MHz BCKI DEMP IW1N IW2N INF1N MUTE FSEL1 FSEL2 Digital audio interface receiver (YM3623B) connection 384fs øA L/R (16.9344MHz) fs(44.1kHz) XTI LRCI DI BCKI DEMP IW1N IW2N INF1N MUTE FSEL1 FSEL2 MUTE CKSLN YAMAHA DIR YM3623B S1 S2 DO BCO DEF SM5843 NIPPON PRECISION CIRCUITS—22 SM5843A×1 Output Interface Circuits 20-bit input Σ∆ DAC (SM5864AP) connection 1 X'tal 384fs to SIGNAL PROCESSOR CKSLN (CD DECODER) 384fs CKO 74HCU04 XDIVN XTI BCKO WCKO DOL 384fs CKO BCKI 8fs WCKI XTI LOA (20bitOUT) SM5843 DOR NPC LOBN Σ∆DAC DINL SM5864 ROA DINR (ΣDECO) Analog LPF Analog LPF LchOUT ROBN RchOUT OW20N COMPN X3SL 20-bit input Σ∆ DAC (SM5864AP) connection 2 L/R-channel independent complementary PWM output to SIGNAL PROCESSOR (CD DECODER) 384fs CKSLN CKO XTI BCKO WCKO (20bitOUT) XDIVN 384fs CKO BCKI 8fs WCKI DINL LOA SM5843 DOL DOR NPC LOBN Σ∆DAC SM5864 ROA DINR (ΣDECO) Analog LPF LchOUT ROBN OW20N X3SL COMPN XTI 74HCU04 X'tal 384fs XDIVN BCKI WCKI DINL XTI LOA NPC LOBN DINR Σ∆DAC SM5864 ROA (ΣDECO) Analog LPF RchOUT ROBN X3SL COMPN NIPPON PRECISION CIRCUITS—23 SM5843A1 NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NIPPON PRECISION CIRCUITS INC. NC9626AE 1997.03 NIPPON PRECISION CIRCUITS—24