SM5844AF

SM5844AF NIPPON PRECISION CIRCUITS LTD. Asynchronous Sample Rate Converter APPLICATIONS s OVERVIEW The SM5844AF is a digital audio signal, asynchronous sample rate converter LSI. It reads 16 or 20-bit word length input data, and writes 16, 18, or 20-bit word length output data. It also features a built-in digital deemphasis filter and digital attenuator. The SM5844AF operates from a 5 V supply, and is available in 44-pin QFPs. s s Digital audio equipment, sample rate conversion (audiovisual amplifiers, CD-R, DAT, MD and 8 mm VTRs) Commercial recording/editing equipment, sample rate conversion Input data jitter elimination PINOUT THRUN BCKO LRCO OCLK OCKSL SLAVE DOUT DI FEATURES Functions s s s s s s PACKAGE DIMENSIONS Unit: mm 44-pin QFP 12.80 + 0.30 10.00 s s s 12.80 + 0.30 - MLEN/DEEM OW18N DMUTE VDD s s s s s s 0.17 + 0.05 - 0 to 0.20 NIPPON PRECISION CIRCUITS—1 1.75MAX Left/right-channel processing (stereo) Input sample rate (fsi) ranges • 24 to 48 kHz (256fsi mode) • 27 to 55 kHz (384fsi mode) Output sample rate (fso) range • 20 to 100 kHz Sample rate conversion ratio (fso/fsi) • 0.5 to 2.0 times Asynchronous input and output timing (clock inputs) System clock inputs (input and output clocks independent) • 256fsi or 384fsi input system clock • 256fso or 384fso output system clock Deemphasis filter • IIR-type filter • 44.1, 48 or 32 kHz Digital attenuator • 11-bit data for 1025 levels • Smooth, incremental attenuation change • +12 dB gain shift function Direct mute function Through mode operation • Input to output direct Output data clocks (LRCO, BCKO) • External input (slave mode) • Output system clock generated internally (master mode) CMOS-level input/outputs 5 V (standard) single supply 44-pin QFP Molybdenum-gate CMOS process VSS SM5844AF BCKI LRCI ICLK ICKSL IFM1 IFM2 RSTN TST2N TST1N STATE IISN OW20N MCOM MDT/FSI1 MDT/FSI2 10.00 0.60 + 0.20 - 0.80 0.35 + 0.10 1.45 0 to 10 S M5844AF Filter Characteristics and Converter Efficiency s s Interfaces s s s s 20-bit internal data word length Deemphasis filter characteristics (IIR filter) • ±0.03 dB gain deviation from ideal filter characteristics Converter noise levels • ≤ −110 dB internally-generated noise • −98 dB (16-bit output), −110 dB (18-bit output) and −122 dB (20-bit output) word rounding noise Anti-aliasing LPF characteristics (4 FIR filters) with automatic output/input sample rate conversion ratio selection • Up converter LPF (1.0 to 2.0 times) • Down converter LPF 1 (48.0 to 44.1 kHz or 0.92 times) • Down converter LPF 2 (44.1 to 32.0 kHz or 0.73 times) • Down converter LPF 3 (48.0 to 32.0 kHz or 0.67 times) Output S/N ratio (theoretical values) S/N ratio O utput signal word length 1 6 bits 18 bits 20 bits 16-bit input word length 94.8 dB 97.5 dB 97.7 dB 20-bit input word length 97 dB Input data format • 2s-complement, L/R alternating, serial • Normal format (non IIS) Mode 1 2 3 4 20 bits Front Rear LSB first W ord length 16 bits Rear M S B fi rst Front/rear p a cking Data sequence s Output data format • 2s-complement, MSB first, L/R alternating, serial • Continuous bit clock Mode 1 2 3 4 5 6 W ord length 16 bits 18 bits 20 bits 20 bits 16 bits Front 18 bits 20 bits IIS 7 Nor mal (non IIS) Rear IIS selection Front/rear p a cking 106 dB 109 dB NIPPON PRECISION CIRCUITS—2 S M5844AF BLOCK DIAGRAM IFM1 IFM2 BCKI DI MCOM MDT/FSI1 MCK/FSI2 MLEN/DEEM Deemphasis and attenuator setup Input data interface Arithmetic operations ICLK ICKSL Input-stage divider Deemphasis operation LRCI RSTN Input timing controller Attenuator Filter characteristic select Interpolation filter operation TST1N TST2N Output operation timing controller Output operation OW18N OW20N IISN Output format controller Dither Output data interface SLAVE Output-stage clock select LRCI BCKI DI OCLK OCKSL Output-stage divider Through mode switching THRUN DMUTE Mute generator Direct mute STATE LRCO BCKO DOUT NIPPON PRECISION CIRCUITS—3 S M5844AF PIN DESCRIPTION Number1 1, 2 3, 4 5 6 7 Name DI BCKI LRCI3 ICLK ICKSL I/O 2 Ip Ip Ip I Ip Data input Input bit clock Input word clock (fsi) Input system clock input Input system clock (ICLK) select. 384fsi when HIGH, and 256fsi when LOW . Input format select 8, 9 IFM1 Ip IFM1 LOW LOW 10, 11 IFM2 Ip HIGH HIGH 12, 13 14, 15 16 VDD DMUTE MCOM – Ip Ip 5 V supply pin Direct mute pin Interface switch control pin. M D T, MCK and MLEN control when HIGH. FSI1, FSI2 and DEEM control when LOW . W h e n M C O M i s H I G H : Microcontroller interface data input (MDT) W h e n M C O M i s L OW : Deemphasis frequency set pins FSI1 LOW 18 MCK/FSI2 Ip W h e n M C O M i s H I G H : Microcontroller interface bit clock (MCK) × HIGH FSI2 HIGH LOW HIGH fsi 48.0 kHz 44.1 kHz 32.0 kHz IFM2 LOW HIGH LOW HIGH 20 bits LSB first W ord length 16 bits Rear packed M S B fi rst Front packed Rear packed Data sequence Data position D escription 17 MDT/FSI1 Ip 19, 20 MLEN/DEEM Ip W h e n M C O M i s H I G H : Microcontroller data word latch clock (MLEN) W h e n M C O M i s L OW : Deemphasis ON/OFF control (DEEM) Output format select When IISN = HIGH (nor mal mode) OW20N OW18N LOW 20 bits LOW HIGH HIGH When IISN = LOW (IIS mode) OW20N LOW OW18N LOW 20 bits LOW HIGH HIGH HIGH LOW HIGH 18 bits 16 bits IIS mode Front packed W ord length Data position HIGH LOW HIGH 18 bits 16 bits Rear packed W ord length Data position Front packed 21, 22 OW18N Ip LOW 23, 24 OW20N Ip 25, 26 27 28 29 IISN S TAT E TST1N TST2N Ip O Ip Ip IIS output mode select. Normal mode when HIGH, and IIS mode when LOW . Internal operation status output (for operation check) Output dither control. Dither ON when LOW , and OFF when HIGH. Test pin. Test mode when LOW . Normal operating mode when HIGH. NIPPON PRECISION CIRCUITS—4 S M5844AF Number1 3 0, 31 32, 33 34, 35 36, 37 38 39 40 41, 42 43, 44 Name RSTN VSS S L AV E THRU N OCKSL OCLK LRCO3 B C KO DOUT I/O 2 Ip – Ip Ip Ip I I /O I/O O Reset pin 0 V ground pin B C K O and LRCO mode set. Outputs (master mode) when LOW , and inputs (slave mode) when HIGH. DOUT through mode set. Normal mode when HIGH, and through mode when LOW . Output system clock (OCLK) select. 384fso when HIGH, and 256fso when LOW . Output system clock input Output word clock input/output (fso). Input/output mode set by the level on SLAVE. Output bit clock input/output. Input/output mode set by the level on SLAVE. Data output D escription 1 . Pins which have the same name are connected internally. Accordingly, circuit connections can be made to either pin or to both pins. 2. I = input, Ip = Input with pull-up resistor (HIGH-level pins can be left open), O = output, I/O = input/output 3. fsi is the input word clock (LRCI) frequency, and fso is the output word clock (LRCO) frequency. SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V P arameter S upply voltage range Input voltage range Storage temperature range Pow er dissipation Soldering temperature Soldering time Symbol VDD V IN T s tg PD T s ld ts ld Rating −0 .3 to 7.0 −0 .3 to V D D + 0 .3 −4 0 to 125 5 50 2 55 10 Unit V V °C mW °C s Recommended Operating Conditions VSS = 0 V P arameter S upply voltage range Operating temperature range Symbol VDD T o pr Rating 4 .75 to 5.5 −2 0 to 70 Unit V °C NIPPON PRECISION CIRCUITS—5 S M5844AF DC Electrical Characteristics VDD = 4.75 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C P arameter C urrent consumption HIGH-level input voltage 2 ,3 voltage 2 voltage 4 L O W -level input voltage 2 ,3 A C-coupled input H IGH-level output voltage 4 L O W -level output HIGH-level input current 2 L O W -level input current 2 ,3 Input leakage current 3 Pull-up resistance 3 Symbol ID D V IH V IL V A CI VOH VOL II H II L IL H R IH IO H = −1 .0 mA IO L = 1 .0 mA V IN = V D D V IN = 0 V V IN = V D D Condition V D D = 5 .0 V 1 Rating min – 0 .7V D D – 0 .3V D D V D D − 0 .5 – – – – 2 50 typ – – – – – – 10 10 – 500 max 80 – 0.3V D D – – 0.4 20 20 1.0 1000 Unit mA V V V p -p V V µA µA µA kΩ 1 . ICKSL = LOW , OCKSL = LOW , fI C L K = 1 3.0 MHz, f O C L K = 1 3.0 MHz, no output load 2. Pins ICLK and OCLK. 3. Pins DI, BCKI, LRCI, ICKSL, IFM1, IFM2, DMUTE, MCOM, MDT/FSI1, MCK/FSI2, MLEN/DEEM, OW 1 8 N , OW20N, IISN, TST1N, T S T 2 N , R S T N , T H R U N , O C K S L a n d S L AVE. 4. P i n s D O U T, BCKO , LRCO and STATE. AC Electrical Characteristics VDD = 4.75 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C ICLK input P arameter L O W -level clock pulsewidth HIGH-level clock pulsewidth Clock pulse cycle Symbol Condition ICKSL LOW HIGH LOW HIGH LOW HIGH System clock 256fsi 384fsi 256fsi 384fsi 256fsi 384fsi min 30 10 30 10 80 47 Rating typ – – – – – – max – – – – 162 106 Unit tC W L tC W H tC Y ns ns ns OCLK input P arameter L O W -level clock pulsewidth HIGH-level clock pulsewidth Clock pulse cycle Symbol Condition OCKSL LOW HIGH LOW HIGH LOW HIGH System clock 256fso 384fso 256fso 384fso 256fso 384fso min 15 10 15 10 39 26 Rating typ – – – – – – max – – – – 200 130 Unit tC W L tC W H tC Y ns ns ns ICLK and OCLK timing >0.7VDD ICLK OCLK t CWH t CY t CWL 0.5VDD