SM5849

SM5849AF NIPPON PRECISION CIRCUITS INC. Asynchronous Sample Rate Converter OVERVIEW The SM5849AF is a digital audio signal, asynchronous sample rate converter LSI. It supports 16/20/24-bit word length input data, 16/20/24-bit word length output data, 2kHz to 100kHz input sample rate range, and 4kHz to 200kHz output sample rate range. It also features a built-in digital deemphasis filter and digital attenuator. FEATURES Functions s s s s Filter Characteristics and Converter Efficiency s s s s s s s s s s s s s Left/right-channel processing (stereo) 2 to 100kHz input sample rate range (fsi) 4 to 200kHz output sample rate range (fso) 0.45 to 2.2-times variable sample rate conversion ratio (fso/fsi) Asynchronous input and output timing (clock inputs) System clock inputs (input and output clocks independent) • 256fsi or 384fsi input system clock select • 256fso or 384fso output system clock select Deemphasis filter • IIR-type filter • 44.1, 48 or 32kHz Digital attenuator • 11-bit data, 1025 levels • Smooth attenuation change • +12dB gain shift function Direct mute function Through mode operation • Direct connection from input to output Output data clocks (LRCO, BCKO) • Slave mode: external input • Master mode: output system clock generated internally Dither round-off processing • Dither round-off ON/OFF selectable 3.3V single supply 80-pin QFP Silicon-gate CMOS process s s s 24-bit internal data word length Deemphasis filter characteristics (IIR filter) • ±0.03dB gain deviation from ideal filter characteristics Anti-aliasing LPF characteristics • Output/input sample rate conversion ratio automatic filter select (6 FIR filters) - Up converter LPF 1.0 to 2.2 times - Down converter LPF I 0.92 times: 48.0 to 44.1kHz - Down converter LPF II 0.73 times: 44.1 to 32.0kHz - Down converter LPF III 0.67 times: 48.0 to 32.0kHz - Down converter LPF IV 0.5 times: 48.0 to 24.0kHz - Down converter LPF V 0.45 times: 48.0 to 22.1kHz • ±0.00005dB passband ripple • > 110dB stopband attenuation Converter noise levels • ≤ −110dB internal calculation (quantization) noise • −98dB (16-bit output), −122dB (20-bit output), and −146dB (24-bit output) word rounding noise Output S/N ratio (theoretical values) S/N ratio O utput signal w ord length 1 6 bits 20 bits 24 bits 16-bit input w ord length 94.8dB 97.7dB 97.7dB 20-bit input w ord length 97.7dB 109.5dB 109.7dB 24-bit input w ord length 97.7dB 109.7dB 110dB NIPPON PRECISION CIRCUITS—1 S M5849AF Interfaces s Input data format • 2s-complement, L/R alternating, serial • IIS/non-IIS format Mode 1 2 16 bits 3 4 5 6 20 bits 7 8 9 10 24 bits 11 12 Left justified IIS M S B fi rst M S B fi rst Left justified IIS Right justified Right justified M S B fi rst M S B fi rst M S B fi rst LSB first Left justified IIS Right justified Right justified M S B fi rst M S B fi rst M S B fi rst LSB first W ord length Data position Right justified Right justified Data sequence M S B fi rst LSB first s Output data format • 2s-complement, MSB first, L/R alternating, serial • Continuous bit clock Mode 1 2 3 4 5 6 7 W ord length 16 bits 20 bits 24 bits 24 bits 16 bits Left justified 20 bits 24 bits IIS Nor mal (non IIS) Right justified IIS selection Data position APPLICATIONS s Digital audio equipment-interface sample rate conversion (AV amplifiers, CD-R, DAT, MD and 8mm VTRs) s Commercial recording/editing equipment sample rate conversion ORDERING INFORMATION D e vice SM5849AF P ackag e 80-pin QFP NIPPON PRECISION CIRCUITS—2 S M5849AF PINOUT Top view 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SLAVE THRUN RSTN DITHN TST2N STATE IISN OWL1 OWL2 VDD VDD OCKSL OCLK VSS LRCO BCKO DOUT N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SM5849AF JAPAN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. MLEN/DEEM MCK/FSI2 MDT/FSI1 MCOM DMUTE VDD PACKAGE DIMENSIONS (Unit: mm) 80-pin QFP 14 0.4 12 0.1 14 0.4 12 0.1 VDD DI BCKI LRCI VSS ICLK ICKSL IFM1 IFM2 IWL1 IWL2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS 0.5 1.7max 0.1 0.18 0.05 1.4 0.1 0.05 0.125 0.025 0 to 10 0.1 0.5 0.2 NIPPON PRECISION CIRCUITS—3 S M5849AF BLOCK DIAGRAM IWL1 IWL2 IFM1 IFM2 BCKI DI MCOM MDT/FSI1 MCK/FSI2 MLEN/DEEM Deemphasis and attenuator setup Input data interface Arithmetic operations ICLK ICKSL Input-stage divider Deemphasis operation LRCI RSTN Input timing controller Attenuator Filter characteristic select Interpolation filter operation Dither operation DITHN TST2N Output operation timing controller Output operation OWL1 OWL2 IISN Output format controller Output data interface SLAVE Output-stage clock select LRCI BCKI DI OCLK OCKSL Output-stage divider Through mode switching THRUN DMUTE Mute generator Direct mute STATE LRCO BCKO DOUT NIPPON PRECISION CIRCUITS—4 S M5849AF PIN DESCRIPTION Number 1 2 3 4 5 6 7 Name VDD DI BCKI LRCI VSS ICLK ICKSL I/O 1 – Ip Ip Ip – I Ip Supply voltage Digital input signal Bit clock input W ord clock input Ground System clock input System clock select. 384fs clock when HIGH, and 256fs clock when LOW . Input format select 8 IFM1 Ip IFM1 LOW LOW HIGH 9 IFM2 Ip HIGH IFM2 LOW HIGH LOW HIGH Data position Right justified Right justified 1 Left justified IIS D escription 1. Data is in LSB first sequence Input word length select 10 IWL1 Ip IWL1 LOW LOW 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 IWL2 NC NC NC NC NC NC NC NC VSS VDD DMUTE MCOM MDT/FSI1 MCK/FSI2 MLEN/DEEM NC NC NC NC NC NC NC NC NC NC NC Ip – – – – – – – – – – Ip Ip Ip Ip Ip – – – – – – – – – – – HIGH HIGH IWL2 LOW HIGH LOW HIGH Data length 16 bits 24 bits 20 bits 24 bits No connection (must be open) No connection (must be open) No connection No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) Ground Supply voltage Direct mute pin. Muting ON when HIGH. Microcontroller control select. Microcontroller control when HIGH. W h e n M C O N = H I G H : Microcontroller interface data input (MDT) W h e n M C O N = L OW : Deemphasis filter fs select 1 (FSI1) W h e n M C O N = H I G H : Microcontroller interface clock (MCK) W h e n M C O N = L OW : Deemphasis filter fs select 2 (FSI2) W h e n M C O M i s H I G H : Microcontroller interface latch enable (MLEN) W h e n M C O M i s L OW : Deemphasis function select (DEEM) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) NIPPON PRECISION CIRCUITS—5 S M5849AF Number 38 39 40 41 Name NC NC VSS VDD I/O 1 – – – – No connection (must be open) No connection (must be open) Ground Supply voltage Output word length select 42 OWL2 Ip OWL1 LOW LOW HIGH 43 OWL1 Ip HIGH OWL2 LOW HIGH LOW HIGH Data length 16 bits 24 bits 20 bits 24 bits 1 D escription 1. Data is in left justified sequence. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 IISN S TAT E TST2N DITHN RSTN THRU N S L AV E NC NC NC NC NC NC NC NC NC VSS VDD OCKSL OCLK VSS LRCO B C KO DOUT NC NC NC NC NC NC NC NC NC NC NC NC VSS Ip O Ip Ip Ip Ip Ip – – – – – – – – – – – Ip I – O O O – – – – – – – – – – – – – IIS output mode select. Normal mode when HIGH, and IIS mode when LOW . Status output IC test mode pin 2. Test mode when LOW . Leave HIGH or open circuit for normal operation. Output dither control pin. Dither when LOW , and normal mode when HIGH. Reset input. Reset when LOW . Through mode set. Normal mode when HIGH, and through mode when LOW . Slave mode set. Slave mode when HIGH, and master mode when LOW . No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) Ground Supply voltage Output system clock select. 384fs when HIGH, and 256fs when LOW . Output system clock input Ground W ord clock output Bit clock output Data output No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) No connection (must be open) Ground 1 . Ip = input pin with internal pull-up resistor NIPPON PRECISION CIRCUITS—6 S M5849AF SPECIFICATIONS Absolute Maximum Ratings VSS = 0V P arameter S upply voltage range Input voltage range Storage temperature range Pow er dissipation 1 . Ratings also apply at supply switch ON and OFF. Symbol VDD V IN T s tg PD Rating 1 −0 .3 to 4.0 V S S − 0 .3 to V D D + 0 .3 −5 5 to 125 4 00 U nit V V °C mW Recommended Operating Conditions VSS = 0V P arameter S upply voltage range Operating temperature range Symbol VDD T o pr Rating 3 .0 to 3.6 −4 0 to 85 Unit V °C DC Electrical Characteristics VDD = 3.0 to 3.6V, VSS = 0V, Ta = −40 to 85°C Rating P arameter C urrent consumption HIGH-level input L O W -level input HIGH-level input L O W -level input voltage 1 voltage 1 voltage 2 voltage 2 voltage 3 voltage 3 current 2 current 2 Symbol ID D V I H1 V I L1 V I H2 V I L2 VOH VOL II H II L IL H IL L I O H = −1 . 0 m A IO L = 1 .0mA V IN = V D D V IN = 0V V IN = V D D V IN = 0V Condition min N o output load – 2 .0 – 2 .0 – V D D – 0.4 – – – – – typ 70 – – – – – – – – – – max 100 – 0.8 – 0.8 – 0.4 1.0 90 1.0 1.0 mA V V V V V V µA µA µA µA Unit HIGH-level output L O W -level output HIGH-level input L O W -level input Input leakage current 1 1 . Pins ICLK and OCLK. 2 . Pins DI, BCKI, LRCI, ICKSL, IFM1, IFM2, IWL1, IWL2, DMUTE, MCOM, MDT/FSI1, MCK/FSI2, MLEN/DEEM, OW L 1 , OWL2, IISN, DITHN, TST2N, RSTN, T H R UN, SLAVE, OCKSL. 3 . Pins STAT E , L R C O, BCKO , D O U T. NIPPON PRECISION CIRCUITS—7 S M5849AF AC Electrical Characteristics Input clock (ICLK) Condition P arameter Symbol System clock 2 56fsi H IGH-level clock pulsewidth tC W H 1 384fsi 2 56fsi L O W -level clock pulsewidth tC W L 1 384fsi 2 56fsi Clock pulse cycle tC Y 1 384fsi min 17.5 11.7 17.5 11.7 39.0 26.0 typ – – – – – – max – ns – – ns – 2000 ns 1300 Rating Unit Output clock (OCLK) Condition P arameter Symbol System clock 2 56fso H IGH-level clock pulsewidth tC W H 2 384fso 2 56fso L O W -level clock pulsewidth tC W L 2 384fso 2 56fso Clock pulse cycle tC Y 2 384fso min 8.7 5.8 8.7 5.8 19.5 13.0 typ – – – – – – max – ns – – ns – 1000 ns 650 Rating Unit ICLK and OCLK timing ICLK OCLK t CWH1, t CWH2 t CY1, t CY2 t CWL1, t CWL2 0.5VDD NIPPON PRECISION CIRCUITS—8 S M5849AF Serial inputs (DI, LRCI, BCKI) Rating P arameter B CKI HIGH-level pulsewidth B C K I L OW -level pulsewidth BCKI pulse cycle DI setup time DI hold time Last BCKI rising edge to LRCI edge LRCI edge to first BCKI rising edge Symbol min tB C W H 1 tB C W L 1 tB C Y 1 tD S tD H tB L 1 tL B 1 50 50 1 00 50 50 50 50 typ – – – – – – – max – – – – – – – ns ns ns ns ns ns ns Unit t BCY1 t BCWH1 t BCWL1 BCKI 0.5VDD t DS t DH DI 0.5VDD t BL1 t LB1 LRCI 0.5VDD NIPPON PRECISION CIRCUITS—9 S M5849AF Serial inputs (LRCO, BCKO: SLAVE = HIGH) Rating P arameter B C K O HIGH-level pulsewidth B C K O L OW -level pulsewidth B C K O pulse cycle Last BCKO rising edge to LRCO edge LRCO edge to first BCKO rising edge Symbol min tB C W H 2 tB C W L 2 tB C Y 2 tB L 2 tL B 2 39 39 78 39 39 typ – – – – – max – – – – – ns ns ns ns ns Unit N ote: B C KO clock inputs exceeding 64 fso cannot be detected, and will cause incorrect operation. t BCY2 t BCWH2 t BCWL2 BCKO 0.5VDD t BL2 t LB2 LRCO 0.5VDD NIPPON PRECISION CIRCUITS—10 S M5849AF Microcontroller interface (MCK, MDT, MLEN) Rating P arameter M C K L O W -level pulsewidth MCK HIGH-level pulsewidth MDT setup time MDT hold time M L E N L OW -level pulsewidth MLEN HIGH-level pulsewidth MLEN setup time MLEN hold time Symbol min tM C W L tM C W H tM D S tM D H tM LW L tM LW H tM L S tM L H 50 50 50 50 50 50 50 50 typ – – – – – – – – max – – – – – – – – ns ns ns ns ns ns ns ns Unit MDT 0.5VDD t MDS t MDH MCK t MCWL t MCWH t MLS MLEN t MLWL t MLWH t MLH 0.5VDD 0.5VDD Reset input (RSTN) Rating P arameter First HIGH-level pulsewidth after supply ON RSTN pulsewidth N ote: tC Y i s the system clock input cycle time. tR S T = a pproximately 3.8 µs w hen t C Y = 5 9ns. Symbol min tH R S T tR S T – 64 typ 640 – max – – tC Y tC Y Unit VDD RSTN t HRST t RST NIPPON PRECISION CIRCUITS—11 S M5849AF Serial outputs (DOUT, BCKO, LRCO) SLAVE = LOW, CL = 15pF Rating P arameter LRCO pulse cycle L R C O L OW -level pulsewidth LRCO HIGH-level pulsewidth B C K O pulse cycle Symbol tL O C Y tL O W L tL O W H O C K S L = L OW tB O C Y OCKSL = HIGH O C K S L = L OW B C K O L OW -level pulsewidth tB O W L OCKSL = HIGH O C K S L = L OW B C K O HIGH-level pulsewidth B C K O to DOUT and LRCO delay time tB O W H tB D H 1 tB D L 1 OCKSL = HIGH B C K O fall to DOUT, LRCO rise B C K O fall to DOUT, LRCO fall Condition min – – – – – – – – – –5 –5 typ 1/fso 1/2fso 1/2fso 1/64fso 1/48fso 1/128fso 1/96fso 1/128fso 1/96fso – – max – – – – ns – – ns – – ns – 20 20 ns ns ns ns ns Unit SLAVE = HIGH, CL = 15pF Rating P arameter Symbol tB D H 2 tB D L 2 Condition min B C K O fall to DOUT rise B C K O fall to DOUT fall 0 0 B C K O to DOUT delay time typ – – max 50 50 ns ns Unit t BOCY t BOWL t BOWH BCKO 0.5VDD t BDH1, t BDL1 t BDH2, t BDL2 DOUT 0.5VDD t BDH t BDL LRCO t LOWH t LOCY t LOWL 0.5VDD NIPPON PRECISION CIRCUITS—12 S M5849AF Filter Characteristics Anti-aliasing filter frequency characteristic Filter5 48 to 24kHz 0 Filter3 44.1 to 32kHz Filter4 48 to 32kHz Filter1 Up converter Filter2 48 to 44.1kHz Filter6 48 to 22.05kHz -20 -40 Attenuation [dB] -60 -80 -100 -120 -140 0.15 0.17 0.19 0.22 0.24 0.26 0.28 0.3 0.33 0.35 0.37 0.39 0.41 0.43 0.46 0.48 0.5 0.52 0.54 0.57 0.59 0.61 0.63 Frequency [× fsi] Deemphasis filter frequency characteristic 0.00 -2.00 Attenuation [dB] -4.00 -6.00 -8.00 44.1KHz 48KHz 32KHz -10.00 -12.00 10 20.23 40.93 82.79 167.5 338.8 685.5 1387 2805 5675 11482 23227 Frequency [Hz] 0 32KHz 44.1KHz 48KHz Phase Characteristics θ [°] -20 -40 -60 -80 -100 -120 10 17.3 29.92 51.76 89.54 154.9 267.9 463.4 801.7 1387 2399 4150 7178 12417 21478 Frequency [Hz] NIPPON PRECISION CIRCUITS—13 S M5849AF FUNCTIONAL DESCRIPTION Input Data Interface (DI, LRCI, BCKI, IFM1, IFM2, IWL1, IWL2) Table 1. Input data format (IFM1, IFM2, IWL1, IWL2) Mode 1 2 3 4 5 6 7 8 9 10 11 12 IFM1 LOW LOW HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH HIGH IFM2 LOW HIGH LOW LOW HIGH LOW HIGH HIGH LOW HIGH LOW HIGH L O W or HIGH LOW HIGH HIGH 24 bits Left justified IIS M S B fi rst M S B fi rst LOW 20 bits Left justified IIS Right justified Right justified M S B fi rst M S B fi rst M S B fi rst LSB first LOW 16 bits Left justified IIS Right justified Right justified M S B fi rst M S B fi rst M S B fi rst LSB first IWL1 IWL2 W ord length Data position Right justified Right justified Data sequence M S B fi rst LSB first Attenuator and Deemphasis Selection The attenuator is set using the microcontroller interface. When the attenuator is used, deemphasis settings also need to be set using the microcontroller Table 2. Attenuator and deemphasis function select Function set method Function External pins ( M C O M = L OW ) DEEM FSI1, FSI2 N/A (no attenuation) N/A (test mode 1) Microcontroller interface (MCOM = HIGH) FDEEM FFSI1, FFSI2 11 bits (B0 to B10) FTST1, FTST2 interface. The microcontroller interface comprises MDT, MCK and MLEN, and is used to transfer all input serial data. Deemphasis ON/OFF Deemphasis frequency (fsi) select Attenuator data set Test mode select MCON should not be switched after a power-ON reset. When MCOM is HIGH, serial data received on MDT, MCK and MLEN sets the attenuation data and control flag data. When MCOM is LOW, the logic levels on FSI1, FSI2 and DEEM select the device function. NIPPON PRECISION CIRCUITS—14 S M5849AF Microcontroller Interface (MCOM, MDT, MCK, MLEN) When MCOM is HIGH, the microcontroller interface is active, comprising MDT (data), MCK (clock) and MLEN (latch enable clock) interface pins. Input data on MDT is synchronized to the MCK clock. Data is read into the input stage shift register on the rising edge of MCK. Accordingly, the input data should change on the falling edge of MCK. Input data enters an internal SIPO (serial-to-parallel converter register), and then the parallel data is latched into the mode register on the rising edge of the latch enable clock MLEN. The mode register addressed is determined by bit D1 of the 12 data bits before MLEN goes HIGH. If this bit is LOW, then the data is read into the attenuation data register as shown in figure 1. If this bit is HIGH, then the data is read into the mode flag register as shown in figure 2. The function of each bit in the mode flag register is described in table 3. MLEN MCK MDT ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,, ,,,,, ,,,,,,,,, ,,,,, ,,,,, 1 12 D1 D2 MSB D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 LSB ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, "L" B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Figure 1. Attenuation data format (D1 = LOW) MLEN MCK MDT ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, , ,,,,, ,,,, 1 12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, "H" "L" "L" "L" "L" FTST1 FTST2 FRATE F12DB FFSI1 FFSI2 FDEEM Figure 2. Mode flag data format (D1 = HIGH) NIPPON PRECISION CIRCUITS—15 S M5849AF Table 3. Mode flag description Mode function select D1 Bit M o d e fl ag P arameter L OW/HIGH Select IC test mode flags. Not used for normal operation. D2 to D7 should be set LOW . HIGH D8 F R AT E Input/output rate LOW HIGH D9 HIGH D10 FFSI1 Deemphasis filter fs select 1 F12DB Attenuator LOW No gain shift (normal operation) fsi select FFSI2 LOW LOW D11 FFSI2 Deemphasis filter fs select 2 HIGH HIGH HIGH LOW FFSI1 LOW 44.1kHz HIGH LOW HIGH 48.0kHz 32.0kHz LOW fsi LOW Set the input/output sample rate ratio with high accuracy every 2048 output samples +12dB gain shift LOW Set the input/output sample rate ratio for each output sample LOW Reset mode D2 to D7 (Not used) Test mode select LOW D12 FDEEM Deemphasis control ON/OFF Deemphasis filter ON LOW Deemphasis filter OFF Deemphasis (DEEM, FSI1, FSI2 pins or FDEEM, FFSI1, FFSI2 flags) The digital deemphasis filter is an IIR filter with variable coefficients to faithfully reproduce the gain and phase characteristics of analog deemphasis filters. The filter coefficients are selected by FSI1 (or FFSI1 flag) and FSI2 (or FFSI2 flag) to correspond to the sampling frequencies fs = 44.1, 48.0 and 32.0kHz. Table 4. Deemphasis ON/OFF DEEM ( M C O M = L OW ) HIGH LOW FDEEM (MCOM = HIGH) Deemphasis ON OFF Table 5. Deemphasis fs select (FSI1, FSI2 pins or FFSI1, FFSI2 flags) M C O M = L OW ( M C O M = H I G H ) fs FSI1 (FFSI1) LOW HIGH LOW HIGH FSI2 (FFSI2) LOW 44.1kHz LOW HIGH HIGH 48.0kHz 32.0kHz NIPPON PRECISION CIRCUITS—16 S M5849AF Attenuation (MDT, MCK, MLEN) The digital attenuator coefficients are read in as serial data on the microcontroller interface. Data on MDT is read into the internal shift register on the rising edge of MCK, and then 12 bits are latched internally on the rising edge of MLEN. When the leading bit is 0 (D1 = LOW), the following 11 bits are read into the attenuation register and used as an unsigned integer in MSB first format. See figure 3. MLEN MCK MDT ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,, ,,,,, ,,,,,,,,, ,,,,, ,,,,, 1 12 D1 D2 MSB D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 LSB ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, "L" B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Figure 3. Attenuation data format (microcontroller interface) Although the attenuation data comprises 11 bits, only 1025 levels are valid as given by the following. DATT Gain = 20 × log  --------------- [dB]  1024  when F12DB = LOW DATT = 20 × log  --------------- [dB]  256  when F12DB = HIGH After a system reset initialization, DATT is set to 400H and the F12DB flag is LOW, corresponding to 0dB gain. (The F12DB flag is described in table 3.) DATT = ∑ i=0 10 ai × 2 ( 10 – i ) The gain of the attenuator for values of DATT from 001H to 400H are given by the following equations. Note that when the F12DB flag is HIGH, the gain is shifted by a fixed +12.0412dB. Table 6. Attenuator settings D1 Attenuation data D AT T 000H 001H ↓ LOW 100H ↓ 3FFH 400H (to 7FFH) F 1 2 D B = L OW (default) Gain (dB) −∞ −6 0.206 ↓ −1 2.041 ↓ −0 .0085 0 Linear expression 0 .0 1/1024 ↓ 256/1024 ↓ 1023/1024 1.0 F12DB = HIGH Gain (dB) −∞ −4 8.165 ↓ 0.0 ↓ 12.032 12.041 Linear expression 0 .0 1/256 ↓ 256/256 ↓ 1023/256 4.0 NIPPON PRECISION CIRCUITS—17 S M5849AF Attenuator operation A change in the attenuation data DATT causes the gain to change smoothly from its previous value towards the new setting. The new attenuation data is stored in the attenuation data register and the current attenuation level is stored in a temporary register. Consequently, if a new attenuation level is read in before the previously set level is reached, the gain changes smoothly from the current value towards the latest setting as shown in figure 4. The attenuation counter output changes, and hence the gain changes, by 1 step every output sample. The time taken to reduce the gain from 0dB (or 12dB) to −∞dB is (1024/fso), which corresponds to approximately 23.2ms when fso = 44.1kHz. Level 1 0 dB Level 3 Level 5 Gain Level 2 —∞ ∆t Level 4 Time Figure 4. Attenuator operation example Mute (DMUTE) Direct mute Table 7. DMUTE operation ON/OFF DMUT E LOW HIGH Function Nor mal data is output from the next output word (mute OFF) 0 data is output from the next output word (mute ON) Table 8. Other mute operations I nput R S T N = L OW Function 0 data is output from the next output word (mute ON) Nor mal data is output from the 3073rd output word (mute OFF) RSTN = HIGH FSI1, FSI2 input settings c h a n g e d ( M C O M = L OW). FFSI1, FFSI2 input settings changed (MCOM = HIGH) ICKSL, IFM1, IFM2 input settings change. ICLK input system clock stops. ICLK input system clock restarts. Other mute operations The direct mute function is also invoked at the following times. s s 0 data is output from the next output word (mute ON). Nor mal data is output from the 3073rd output word (mute OFF) s s When the reset input (RSTN) changes. When the fs setting changes, for deemphasis, using either FSI1, FSI2 inputs or FFSI1, FFSI2 flags. When the ICKSL, IFM1, or IFM2 setting changes. When the ICLK input system clock stops. 0 data is output from the next output word (mute ON) Nor mal data is output from the 3073rd output word (mute OFF) NIPPON PRECISION CIRCUITS—18 S M5849AF Internal Operating Status (STATE) Internally, all functions are performed on 24-bit serial data, and the conversion rate and filter type are Table 9. Status data description O utput bit position Content (Output data cycle/input data cycle) − 1 29 Ex. 1st 20th 00.111111111111011111 ⇒ 1 .0 times 01.111111111111011111 ⇒ 2 .0 times (1/2 conversion rate ratio) 00.011111111111011111 ⇒ 0 .5 times (2.0 conversion rate ratio) Not used. Selected filter type 22 DA2 DA2 0 0 23 DA1 0 0 24 DA0 1 1 DA1 0 0 1 1 0 0 DA0 0 1 0 1 0 1 Filter type 1 2 3 4 5 6 C o nversion frequency (example) Up converter 48 to 44.1kHz 44.1 to 32kHz 48 to 32kHz 96 to 48kHz, 48 to 24kHz 96 to 44.1kHz, 48 to 22.05kHz selected accordingly. The output format is 24-bit left-justified. 1 t o 20 21 Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE output. Input System Clock (ICLK, ICKSL) The input system clock can be set to run at either 256fsi or 384fsi, where fsi is the input frequency on LRCI. Note that ICLK and LRCI should be divided from a common clock source or PLL to maintain synchronism. Table 10. ICKSL and input system clock ICKSL HIGH LOW ICLK system clock rate 384fsi 256fsi Output System Clock (OCLK, OCKSL) The output system clock can be set to run at either 256fso or 384fso, where fso is the output frequency on LRCO. In through mode, OCLK and OCKSL have no function and are not used. Note that even in slave mode, a suitable clock must be input on OCLK. A malfunction prevention circuit uses this clock so that operation continues when the ICLK stops. Table 11. SLAVE, OCKSL and output system clock S L AV E LOW LOW HIGH × 256fso N ot used OCKSL HIGH O C L K s y s t e m clock rate 384fso NIPPON PRECISION CIRCUITS—19 S M5849AF Output Data Interface and Output Clock Selection (LRCO, BCKO, DOUT, SLAVE) Table 12. Output mode description Function THRUN S L AV E Mode LOW HIGH HIGH Slave mode Output word clock (LRCO) and output bit clock ( B C KO) are supplied externally. Output word clock (LRCO), output bit clock (BCKO) and output data (DOUT) are the same as LRCI, BCKI and DI, respectively. DMUTE is valid. Inputs 1 Master mode Description Output word clock (LRCO) and output bit clock ( B C KO) are divided from OCLK. L R C O , B C KO state Outputs LOW × T hrough mode Outputs 1 . The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits. Output Format Control (OWL1, OWL2, IISN) The output is in MSB-first, 2s-complement, L/R alternating, bit serial format with a continuous bit clock. Inputs Mode IISN 1 2 HIGH 3 4 5 6 7 LOW HIGH HIGH LOW LOW HIGH LOW HIGH LOW HIGH × 24 bits 24 bits 16 bits 20 bits 24 bits IIS Left justified OWL2 LOW LOW OWL1 LOW HIGH W ord length 16 bits 20 bits Nor mal (non IIS) Right justified Output format IIS selection Data position Output Timing Calculation The output timing is controlled to maintain the desired ratio between the output data cycle and the input data cycle. Output round-off processing The internal processor data length and output data length are different, making output data round-off processing necessary. The SM5849AF supports selectable normal round-off processing and trigonometric function dither round-off processing*. * DITHN HIGH LOW Output round-off processing Nor mal round-off Dither round-off TPDF: Triangular Probability Density Function NIPPON PRECISION CIRCUITS—20 S M5849AF Filter Characteristic Selection Conversion rates from 0.45 to 2.2 times are supported using the following 6 filter types. The ratio between the output sample rate and input sample rate is measured automatically and the most suitable filter type for this ratio is selected automatically. Table 13. fs ratio and filter selection Filter mode 1 2 3 4 5 6 fs ratio (fso/fsi) 1.0 to 2.2 0.91875 0.72562 0.66667 0.50000 0.459375 Selects range ≥ 0 .969697 0.864865 to 0.969697 0.711111 to 0.864865 0.627451 to 0.711111 0.492308 to 0.627451 ≤ 0 .492308 C o nversion frequency (example) Up converter 48.0 to 44.1kHz 44.1 to 32.0kHz 48 to 32kHz 48 to 24kHz, 96 to 48kHz 48 to 22.05kHz, 96 to 44.1kHz When the selected fs conversion ratio and the actual sample rate conversion ratio do not coincide, the following phenomenon occur. Table 14. Mismatch condition and response Condition 1 Actual sample rate conversion ratio is low er than the selected filter conversion ratio Actual sample rate conversion ratio is higher than the selected filter conversion ratio Response The audio band high-pass develops aliasing noise. The audio band high-pass is cut off. 1. An output noise may be generated if the fs conversion ratio changes at a rate greater 0.119%/sec. System Reset (RSTN) At power-ON, all device functions must be reset. The device is reset by applying a LOW-level pulse on RSTN. At system reset, the internal arithmetic operation, output timing counter and internal flag register operation are synchronized on the next LRCI rising edge. Note that all flags are set to their defaults (all LOW). A power-ON reset signal can be applied from an external microcontroller. For systems where ICLK and LRCI are stable at power ON, initialization can be performed by connecting a 0.001µF capacitor between RSTN and VSS. Otherwise, a capacitor value should be chosen such that RSTN does not go HIGH until after LRCI and ICLK have stabilized. Through Mode (THRUN) Table 15. Through mode function description THRUN LOW HIGH Mode Through mode Nor mal mode Description Direct connections are made: LRCI to LRCO, BCKI to BCKO , and DI to D O U T. DMUTE is valid. Sample rate converter operation Synchronizing Internal Arithmetic Timing The clock on LRCI should pass through 1 cycle for every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW) ICLK clock cycles to maintain correct internal arithmetic sequence. If the number of ICLK cycles is different, increases or decreases, or any jitter is present, device operation could be affected. There is a fixed-value tolerance within which the internal sequence and LRCI clock timing are not adversely affected. Table 16. ICLK and clock tolerance ICKSL HIGH (384fs mode) L O W (256fs mode) Allow a b le clock variation +8 to −6 cycles +4 to −3 cycles Whenever the allowable tolerance is exceeded, the internal sequence start-up may be delayed or fail. When this occurs, there is a possibility that a click noise will be generated. NIPPON PRECISION CIRCUITS—21 S M5849AF TIMING DIAGRAMS Input Timing Examples (DI, BCKI, LRCI) Audio data input timing (right-justified 16-bit word, IFM1 = L, IFM2 = L, IWL1 = L, IWL2 = L) LRCI(fsi) 1 24 25 48 BCKI(48fsi) MSB LSB MSB LSB DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Audio data input timing (right-justified 24-bit word, IFM1 = L, IFM2 = L, IWL1 = H, IWL2 = H) LRCI(fsi) 1 24 25 48 BCKI(48fsi) MSB LSBMSB LSB DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data input timing (left-justified 20-bit word, IFM1 = H, IFM2 = L, IWL1 = H, IWL2 = L) LRCI(fsi) 1 24 25 48 BCKI(48fsi) MSB LSB MSB LSB DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 All data bits after the LSB (20th bit) are ignored. Note that more than 20 BCKI cycles are required. Audio data input timing (IIS-format 24-bit word, IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H) LRCI(fsi) 1 32 33 64 BCKI(64fsi) MSB LSB MSB LSB DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data input timing (right-justified 24-bit word, LSB first, IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H) LRCI(fsi) 1 32 33 64 BCKI(64fsi) LSB MSB LSB MSB DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NIPPON PRECISION CIRCUITS—22 S M5849AF Output Timing Examples (DOUT, BCKO, LRCO) Audio data output timing (right-justified 16-bit word, IISN = H, OWL1 = L, OWL2 = L) LRCO(fso) 1 24 25 48 BCKO(48fso) MSB LSB MSB LSB DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Audio data output timing (right-justified 24-bit word, IISN = H, OWL1 = L, OWL2 = H) LRCO(fso) 1 24 25 48 BCKO(48fso) MSB LSBMSB LSB DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data output timing (left-justified 24-bit word, IISN = H, OWL1 = H, OWL2 = H) LRCO(fso) 1 32 33 64 BCKO(64fso) MSB LSB MSB LSB DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data output timing (IIS-format 24-bit word, IISN = L, OWL1 = L, OWL2 = H) LRCO(fso) 1 32 33 64 BCKO(64fso) MSB LSB MSB LSB DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data output timing (right-justified 24-bit word, IISN = H, OWL1 = L, OWL2 = H) LRCO(fso) 1 32 33 64 BCKO(64fso) MSB LSB MSB LSB DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NIPPON PRECISION CIRCUITS—23 S M5849AF State Data Output Timing State data output timing IISN = H LRCO(fso) 1 32 33 64 BCKO(64fso) MSB LSB STATE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IISN = L LRCO(fso) 1 32 33 64 BCKO(64fso) MSB LSB STATE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Delay Time tINPUT is the time when the serial input data read in is completed (on the rising edge of LRCI). tOUTPUT is the time when the serial output data read out is completed (on the rising edge of LRCO). The delay between input and output is given by tOUTPUT − tINPUT = (55 ± 5)/fsi. 1/fs Serial data input t input 55 ± 5 1/fso Serial data output t output t INPUT t OUTPUT — t INPUT t OUTPUT NIPPON PRECISION CIRCUITS—24 S M5849AF TYPICAL APPLICATIONS Input Interface Circuit Digital audio interface receiver (CS8414) (256fsi) MCK FSYNC SCK SDATA Co/F0 5V SEL CS12/FCK M3 M2 M1 M0 3.3V ICKSL MCOM IFM1 IFM2 IWL1 IWL2 ICLK LRCI Level Shifter (5V to 3.3V) BCKI DI MLEN/DEEM DIR CS8414 SM5849AF Output Interface Circuit Digital audio interface receiver (CS8404) External Clock 24.576MHz (256fso) 3.3V 12.288MHz (128fso) 5V OCLK LRCO BCKO DOUT 5V PRO FSYNC MCK Level Shifter (3.3V to 5V) SCK SDATA SM5849AF OCKSL OWL1 OWL2 3.3V TRNPT/FC1 M2 M1 DIT CS8404 IISN THRUN SLAVE 3.3V M0 NIPPON PRECISION CIRCUITS—25 S M5849AF NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9914BE 2000.06 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—26