SM5865AM

SM5865AM NIPPON PRECISION CIRCUITS INC. D/A Converter The SM5865AM is a 24-bit input D/A converter for high-quality digital audio equipment. It comprises newly developed DEM (dynamic element matching) circuits, 3rd-order Σ∆ noise shaper and 23-level quantizer to control wide-band residual quantization noise in the signal band, making it ideal for application with high-frequency sampling formats. Also, the order of the required final-stage analog lowpass filter can be reduced, compared to filters for available devices, enhancing output tone quality. The output stage employs complementary outputs for high-accuracy analog signals, with appropriate lowpass filtering of the output signal. A single SM5865AM IC can be used in combination with an 8-times oversampling digital filter for conversion for a single audio channel. lim Package 0.8 FEATURES s s s s pre s s s s Single-channel D/A converter built-in High performance (120 dB signal-to-noise ratio) (0.001% total harmonic distortion and noise) (110 dB dynamic range) Σ∆ D/A converter • 3rd-order noise shaper • 23-level quantizer Input data format • 20 or 24-bit word length • MSB first, right-justified format • 8 or 4 times oversampling at fs = 32/44.1/48/ 88.2/96/192 kHz System clock frequency • 128/192/256/384/512/768 fs Single 5 V operating supply voltage 24-pin SSOP package Molybdenum-gate CMOS process 5.40 0.20 7.80 0.30 ORDERING INFORMATION Device 0.10 0.10 +0.20 1.90−0.10 0.36 0.10 0.10 1.80 SM5865AM 24-pin SSOP ina ry (Top view) DVSS DI BCKI 1 24 OVERVIEW PINOUT AVSSA RAP IOUTA RAN WCKI IWSL RSTN TO IOUTAN AVDDA AVDDB RBP IOUTB RBN S M 5 8 6 5 AM TSTN DVDD CKI IOUTBN AVSSB CKDVN CVSS 12 13 PACKAGE DIMENSIONS (Unit: mm) 24-pin SSOP 10.05 0.20 10.20 0.30 0.15 − 0.0 + 0.1 5 0.12 M 0.50 0.20 0 10 NIPPON PRECISION CIRCUITS—1 SM5865AM BLOCK DIAGRAM TO 8 TSTN 7 RSTN 6 IWSL 5 WCKI 4 BCKI 3 DI 2 9 DVDD CKI CKDVN CVSS 10 11 12 Divider Timing control Noise shaper lim 23 Level DEM DAC 23 Level DEM DAC 14 15 16 17 18 19 20 RBN IOUTBN IOUTB RBP AVDDB AVDDA AVSSB 13 pre ina ry Input interface Interpolation 1 DVSS Noise shaper 24 23 Level DEM DAC 23 Level DEM DAC AVSSA 21 IOUTAN 22 IOUTA 23 RAP RAN NIPPON PRECISION CIRCUITS—2 SM5865AM PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IP : Pull-up input Name DVSS DI BCKI WCKI IWSL RSTN TSTN TO DVDD CKI CKDVN CVSS AVSSB RBN IOUTBN IOUTB RBP AVDDB AVDDA RAN I/O – I I I Ip Ip Ip O – I Ip – – I O O I – – I Digital ground Data input Bit clock input Word clock input Description Input data word length select. 24-bit when HIGH, and 20-bit when LOW. System reset. Reset when LOW. Test pin. Tie HIGH or leave open for normal operation. Test output Digital supply System clock input System clock frequency divider ratio select. 1 when HIGH (no division), and 2 when LOW. System clock ground Analog ground B Built-in resistor connection B Inverse-phase analog output B In-phase analog output B Built-in resistor connection B Analog supply B Analog supply A IOUTAN IOUTA RAP AVSSA pre NIPPON PRECISION CIRCUITS—3 lim Built-in resistor connection A O Inverse-phase analog output A In-phase analog output A O I Built-in resistor connection A Analog ground A – ina ry SM5865AM SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB Parameter Supply voltage range Input voltage range1 Storage temperature range Power dissipation Soldering temperature Soldering time 1. Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN. Also applicable during supply switching. Symbol DVDD, AVDDA, AVDDB VIN Rating −0.3 to 7.0 DVSS − 0.3 to DVDD + 0.3 −55 to 125 250 Unit V V Recommended Operating Conditions DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB Parameter Supply voltage range Symbol lim Topr Supply voltage variation Operating temperature range pre NIPPON PRECISION CIRCUITS—4 ina ry Tstg PD °C mW °C s Tsld tsld 255 10 Rating Unit V DVDD, AVDDA, AVDDB DVDD − AVDDA, DVDD − AVDDB, AVDDA − AVDDB, DVSS − AVSSA, DVSS − AVSSB, AVSSA − AVSSB, DVSS − CVSS, AVSSA − CVSS, AVSSB − CVSS 4.5 to 5.5 ±0.1 V −40 to 85 °C SM5865AM DC Electrical Characteristics Recommended operating conditions, unless otherwise specified Rating Parameter DVDD supply current1 AVDDA, AVDDB supply current1 CKI HIGH-level input voltage CKI LOW-level input voltage CKI input voltage HIGH-level input voltage2 LOW-level input voltage2 HIGH-level output voltage3 LOW-level output voltage3 CKI HIGH-level input current CKI LOW-level input current LOW-level input current4 HIGH-level input leakage current5 LOW-level input leakage current5 HIGH-level input leakage current6 1. 2. 3. 4. 5. 6. Symbol IDDD IDDA VIHC VILC VINAC VIH VIL VOH VOL IIHC IILC IIL2 IIH1 IIL1 IIH2 Condition min typ max mA mA V Unit pre NIPPON PRECISION CIRCUITS—5 lim DVDD = AVDDA = AVDDB = 5 V, system clock input frequency fCKI = 16.9344 MHz, no output load, NPC-standard input data pattern. Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN. Pin TO. Pins CKDVN, IWSL, RSTN, TSTN. Pins DI, BCKI, WCKI. Pins CKDVN, IWSL, RSTN, TSTN. ina ry 0.7VDD – – – – 0.3VDD – V AC coupling 1.0 – V 2.4 – – – V – 0.5 – V IOH = −1 mA IOL = 1 mA DVDD − 0.4 – – V – 0.4 V VIN = DVDD VIN = 0 V VIN = 0 V 30 60 120 µA 30 – 60 9 120 18 µA µA VIN = DVDD – – 1.0 µA VIN = 0 V – – 1.0 µA VIN = DVDD – – 1.0 µA TBD SM5865AM AC Electrical Characteristics System clock (CKI) Rating Parameter HIGH-level clock pulsewidth LOW-level clock pulsewidth Clock pulse cycle Symbol min tCWH tCWL tCKI TBD typ – max TBD ns Unit CKI Reset Input (RSTN) Parameter Symbol RSTN LOW-level pulsewidth tRSTN Serial input (BCKI, DI, WCKI) lim Symbol tBCWH tBCWL tBCY tDS tDH tBW tWB Parameter BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth BCKI pulse cycle DI setup time DI hold time pre WCKI edge to first BCKI rising edge Last BCKI rising edge to WCKI edge BCKI t BCWH t BCY t BCWL DI t DS WCKI t WB t WL ina ry TBD TBD – – TBD TBD ns ns t CWL t CWH VIH1 0.5VDD VIL1 t CKI Rating typ – Condition Unit µs min 1 max – At power ON After power ON 100 – – ns Rating Unit min 10 10 20 5 5 10 10 typ – – – – – – – max – – – – – – – ns ns ns ns ns ns ns 1.5V 1.5V t DH 1.5V NIPPON PRECISION CIRCUITS—6 SM5865AM AC Analog Characteristics DVDD = AVDDA = AVDDB = 5 V, DVSS = AVSSA = AVSSB = CVSS = 0 V, Ta = 25 °C, 44.1 kHz input sampling frequency, fCKI = 16.9344 MHz (384fs), 48fs operation Rating Parameter Total harmonic distortion LSI output level Dynamic range Signal-to-noise ratio Symbol THD + N Vout1 D.R S/N Condition min 1 kHz, 0 dB typ max % Unit Estimated values for audio signal data with up to 20 kHz bandwidth, DVDD = AVDDA = AVDDB = 5 V, DVSS = AVSSA = AVSSB = CVSS = 0 V, Ta = 25 °C, 48 kHz input sampling frequency, fCKI = 24.576 MHz (512fs), 64fs operation 96 kHz input sampling frequency, fCKI = 24.576 MHz (256fs), 32fs operation Parameter Total harmonic distortion LSI output level Dynamic range Signal-to-noise ratio Symbol THD + N Vout1 D.R S/N Condition Measurement circuit block diagram lim CKO(384fs) BCK WCKI Signal Generator Evaluation Board DATA fs= 44.1kHz pre Measurement conditions Parameter Symbol Total harmonic distortion THD + N Vout D.R Output level Dynamic range Signal-to-noise ratio S/N DVDD = AVDDA = AVDDB = 5 V, DVSS = AVSSA = AVSSB = CVSS = 0 V, Ta = 25 °C 3346A left/right-channel selector switch THRU D-RANGE THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF JIS A filter ON AD725C distortion analyzer with built-in filter 20 kHz lowpass filter ON 400 Hz highpass filter OFF ina ry 1 kHz, 0 dB 1 kHz, −60 dB TBD Vrms dB 1 kHz, 0/−∞ dB dB Rating typ Unit % min max 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, −60 dB TBD Vrms dB 1 kHz, 0/−∞ dB dB L/R Channel Selector Distortion Analyzer 10kΩ Input Impedance NF Corporation 3346A RMS Measurement Corresponds to Shibasoku AD725C NIPPON PRECISION CIRCUITS—7 SM5865AM Measurement circuit pre NIPPON PRECISION CIRCUITS—8 lim ina ry TBD SM5865AM FUNCTIONAL DESCRIPTION Quantization Noise Reduction The SM5865AM employs a 3rd-order 23-level quantizer noise shaper to effectively reduce quantization noise in the audio band. The quantization noise component at 16fs to 96fs operation is shown in figure 1. 0 10 20 30 40 50 60 70 80 Quantization noise 90 (dB) 100 110 120 130 140 150 160 170 180 0 dB sine wave equivalent white noise level 16-bit, fs quantization noise level lim 0 0.5 1 1.5 2 CKDVN = HIGH where n = 1, 2, 3, ... Figure 1. Quantization noise level Internal Oversampling Operation pre Table 1. Operating conditions Parameter fWCKI and fCKI compulsory conditions1 Noise shaper operating frequency The SM5865AM accepts data output from an 8-times or 4-times oversampling digital filter, and oversampled internally again up to the noise shaper operating rate. The internal oversampling factor is determined automatically from the system clock input frequency and the input sampling frequency. This internal oversampling factor (n) must be an integer satisfying the conditions shown in table 1. f CKI f ns = f WCKI × n = ---------8 1. fWCKI = word clock frequency, fCKI = input system clock frequency, n = internal oversampling factor ina ry 16fs 24fs 32fs 48fs 64fs 96fs 20-bit, fs quantization noise level 24-bit, fs quantization noise level 2.5 3 3.5 4 Frequency (fs) CKDVN = LOW f CKI = f WCKI × 8 × n f CKI = f WCKI × 16 × n where n = 1, 2, 3, ... f CKI f ns = f WCKI × n = ---------16 NIPPON PRECISION CIRCUITS—9 SM5865AM Word clock input WCKI SM5865 System clock input CKI Figure 2. Clock-related inputs Table 2 shows some possible combinations for the circuit configuration shown in figure 3. fs Interpolating filter (8-times/4-times) Figure 3. Circuit configuration Table 2. System clock frequencies (CKDVN = HIGH) fs 32 kHz 32 kHz 32 kHz 32 kHz 32 kHz 32 kHz System clock frequency1 fCKI 4.096 MHz (128fs) 6.144 MHz (192fs) 8.192 MHz (256fs) lim Noise shaper operating rate 16fs 24fs 32fs 48fs 64fs 96fs 12.288 MHz (384fs) 16.384 MHz (512fs) 24.576 MHz (768fs) 5.6448 MHz (128fs) 8.4672 MHz (192fs) 16fs 24fs 32fs 48fs 64fs 96fs 16fs 24fs 32fs 48fs 64fs 96fs 11.2896 MHz (256fs) 16.9344 MHz (384fs) 22.5792 MHz (512fs) 33.8688 MHz (768fs) 6.144 MHz (128fs) 9.216 MHz (192fs) 12.288 MHz (256fs) 18.432 MHz (384fs) 24.576 MHz (512fs) 36.864 MHz (768fs) pre 44.1 kHz 44.1 kHz 44.1 kHz 44.1 kHz 44.1 kHz 44.1 kHz 48 kHz 48 kHz 48 kHz 48 kHz 48 kHz 48 kHz ina ry System clock divider select CKDVN fWCKI SM5865 fCKI CKDVN Internal factor (8fs input) 2 3 4 6 8 12 2 3 4 6 8 12 2 3 4 6 8 12 Internal factor (4fs input) 4 6 8 12 16 24 4 6 8 12 16 24 4 6 8 12 16 24 NIPPON PRECISION CIRCUITS—10 SM5865AM Table 2. System clock frequencies (CKDVN = HIGH) fs 88.2 kHz 88.2 kHz 88.2 kHz 88.2 kHz 96 kHz 96 kHz 96 kHz 96 kHz 192 kHz 192 kHz System clock frequency1 fCKI 11.2896 MHz (128fs) 16.9344 MHz (192fs) 22.5792 MHz (256fs) 33.8688 MHz (384fs) 12.288 MHz (128fs) 18.432 MHz (192fs) 24.576 MHz (256fs) 36.864 MHz (384fs) 24.576 MHz (128fs) 36.864 MHz (192fs) Noise shaper operating rate 16fs 24fs 32fs 48fs Internal factor (8fs input) 2 3 4 6 Internal factor (4fs input) 4 6 8 1. When CKDVN = LOW, the system clock frequency fCKI is halved, so the values shown are half the input frequency required for the same sampling rate and internal factors. System Clock Divider (CKDVN) System Reset (RSTN) The device should be reset in the following cases. s s At power ON When the system clock CKI stops, or other abnormalities occur. The device is reset by applying a LOW-level pulse on RSTN. pre lim The SM5865AM has a built-in divide-by-2 system clock frequency divider. The divider enables the internal system clock to operate at half the input frequency, for example when the external master clock input frequency is high. ina ry 12 4 6 8 16fs 24fs 32fs 48fs 2 3 4 6 12 4 6 16fs 24fs 2 3 Audio Data Input (DI, BCKI, WCKI, IWSL) Input data format The audio data is input in MSB-first, 2s-complement, 24-bit/20-bit serial format. The input word bit length is selected by IWSL, 24-bit when HIGH or open circuit, and 20-bit when LOW. Jitter-free function Serial input data bits on DI are read into an SIPO register (serial-to-parallel converter register) on the rising edge of the bit clock BCKI where the serial data is converted into parallel data. The internal parallel data control timing is derived from the system clock, and is not affected by any jitter on the input data clocks (WCKI and BCKI). After a reset operation is released when RSTN goes HIGH, the internal timing and the WCKI input timing are phase compared on the first and subsequent WCKI falling edges and the comparison result is used to perform timing adjustment to maintain the word boundary relationship between the internal timing and the WCKI clock. NIPPON PRECISION CIRCUITS—11 SM5865AM TIMING DIAGRAMS 384fs System Clock Input Timing 1 / 8fs WCKI CKI BCKI (1)20bit * DI MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit DI (3)24bit lim BCKI MSB DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 * Data can be input at any period within the word clock cycle. pre NIPPON PRECISION CIRCUITS—12 ina ry LSB MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LSB SM5865AM 256fs System Clock Input Timing 1 / 8fs CKI BCKI (1)20bit * DI MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit DI BCKI (3)24bit * DI lim MSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BCKI (4)24bit DI pre * Data can be input at any period within the word clock cycle. ina ry LSB MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NIPPON PRECISION CIRCUITS—13 WCKI SM5865AM TYPICAL APPLICATIONS Input Interface Circuit XTI SM5847 DOL DOR WCKO BCKO lim pre ina ry CKI DI WCKI BCKI SM5865 CKI DI WCKI BCKI SM5865 NIPPON PRECISION CIRCUITS—14 SM5865AM Analog Output Circuit 1 RAP IOUTA IOUTAN 23 Level DEM DAC SM5865 23 Level DEM DAC 23 Level DEM DAC IOUTB IOUTBN Analog Output Circuit 2 23 Level DEM DAC 23 Level DEM DAC pre SM5865 23 Level DEM DAC 23 Level DEM DAC lim RAP IOUTA IOUTAN RAN RBP IOUTB IOUTBN RBN NIPPON PRECISION CIRCUITS—15 ina ry RAN RBP RBN 23 Level DEM DAC SM5865AM Analog Output Circuit 3 RAP IOUTA IOUTAN 23 Level DEM DAC SM5865 23 Level DEM DAC 23 Level DEM DAC IOUTB IOUTBN Analog Output Circuit 4 23 Level DEM DAC 23 Level DEM DAC pre SM5865 23 Level DEM DAC 23 Level DEM DAC Note that the analog output characteristics are not guaranteed for non-standard output circuit configurations. NIPPON PRECISION CIRCUITS—16 lim RAP IOUTA IOUTAN RAN RBP IOUTB IOUTBN RBN ina ry RAN RBP RBN 23 Level DEM DAC SM5865AM pre lim NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9804BE 1999.2 ina ry NIPPON PRECISION CIRCUITS—17