SM5902AF

SM5902AF NIPPON PRECISION CIRCUITS INC. compression and non compression type shock-proof memory controller Overview The SM5902 is a compression and non compression type shock-proof memory controller LSI for compact disc players. The compression level can be set in 4 levels, and external memory can be selected from 4 options (1M, 4M, 4M × 2 , 16M). Digital attenuator, soft mute and related functions are also incorporated. It operates from a 2.4 to 5.5 V wide supply voltage range. Features - 2-channel processing - Serial data input ⋅ 2s complement, 16-bit/MSB first, right-justified format ⋅ Wide capture function (up to 3 × speed input rate) - System clock input ⋅ 384fs (16.9344 MHz) - Shock-proof memory controller ⋅ ADPCM compression method ⋅ 4-level compression mode selectable 4-bit compression mode 2.78 s/Mbit 5-bit compression mode 2.22 s/Mbit 6-bit compression mode 1.85 s/Mbit Full-bit non compression mode 0.74 s/Mbit ⋅ 4 external DRAM configurations selectable 1 × 16M DRAM (4M × 4 bits, refresh cycle = 2048 cycle) 1 × or 2 × 4M DRAM (1M × 4 bits) 1 × 1M DRAM (256k × 4 bits) ⋅ DRAM at 5V operation is usable for Low-voltage operation - Compression mode selectable - Microcontroller interface ⋅ Serial command write and status read-out ⋅ Data residual detector: 15-bit operation, 16-bit output ⋅ Digital attenuator 8-bit setting ⋅ Soft attenuator function Noiseless attenuation-level switching (256- step switching in 23 ms max.) ⋅ Soft mute function Mute ON in 23 ms max. Direct return after soft mute release ⋅ Forced mute - Extension I/O Microcontroller interface for external control using 5 extension I/O pins - +2.4 to +5.5 V wide operating voltage range - Schmitt inputs All input pins (including I/O pins) except CLK (system clock) - Reset signal noise elimination Approximately 3.8 µs or longer (65 system clock pulses) continuous LOW-level reset - Digital audio interface (DIT) - 44-pin QFP package (0.8 mm pin pitch) Ordering Information SM5902AF 44pin QFP NIPPON PRECISION CIRCUITS-1 SM5902AF Package dimensions (Unit: mm) 44-pin QFP 1 12.80 + 0.30 10.00 + 0.30 (1.40) 12.80 + 0.30 10.00 + 0.30 0 to 10 0.60 + 0.20 0.80 0.35 + 0.10 0.20 M (1.45) 0.10 + 0.10 0.17 + 0.05 0.15 44-pin QFP 2 12.80 0.30 10.00 0.30 + 0.20 1.55 0.10 0.17 0.05 (1.40) 12.80 0.30 10.00 0.30 0 to 10 4 0.80 0.35 0.10 0.15 0.20 M Pinout (Top View) A3 A2 A1 A0 A4 A5 A6 A7 A8 A9 NRAS 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 0.20 1.50 0.10 (1.40) 0.10 0.10 0.05 C0 .7 0.60 0.20 38 37 36 VDD2 UC1 UC2 UC3 UC4 UC5 DIT NTEST CLK VSS YSRDATA 35 1 2 3 4 5 6 7 8 9 10 11 NWE D1 D0 D3 D2 NCAS A10/ NCAS2 YMCLK YMDATA YMLD YDMUTE YBLKCK NRESET ZSENSE YFCLK ZSRDATA ZLRCK YLRCK YFLAG VDD1 SM5 9 0 2 A F ZSCK YSCK NIPPON PRECISION CIRCUITS-2 SM5902AF Pin description Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin name VDD2 UC1 UC2 UC3 UC4 UC5 DIT NTEST CLK VSS YSRDATA YLRCK YSCK ZSCK ZLRCK ZSRDATA YFLAG YFCLK YBLKCK NRESET ZSENSE VDD1 YDMUTE YMLD YMDATA YMCLK A10 (NCAS2) NCAS D2 D3 D0 D1 NWE NRAS A9 A8 A7 A6 A5 A4 A0 A1 A2 A3 I/O Ip/O Ip/O Ip/O Ip/O Ip/O O Ip I I I I O O O I I I I O I I I I O O O I/O I/O I/O I/O O O O O O O O O O O O O Function H VDD supply pin Microcontroller interface extension I/O 1 Microcontroller interface extension I/O 2 Microcontroller interface extension I/O 3 Microcontroller interface extension I/O 4 Microcontroller interface extension I/O 5 Digital audio interface Test pin 16.9344 MHz clock input Ground Audio serial input data Audio serial input LR clock Audio serial input bit clock Audio serial output bit clock Audio serial output LR clock Audio serial output data Signal processor IC RAM overflow flag Crystal-controlled frame clock Subcode block clock signal System reset pin Microcontroller interface status output VDD supply pin Forced mute pin Microcontroller interface latch clock Microcontroller interface serial data Microcontroller interface shift clock DRAM address 10 DRAM2 CAS control (with 2 DRAMs) DRAM CAS control DRAM data input/output 2 DRAM data input/output 3 DRAM data input/output 0 DRAM data input/output 1 DRAM WE control DRAM RAS control DRAM address 9 DRAM address 8 DRAM address 7 DRAM address 6 DRAM address 5 DRAM address 4 DRAM address 0 DRAM address 1 DRAM address 2 DRAM address 3 Mute Reset Overflow Left channel Right channel Left channel Right channel Test Setting L Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when in input mode) NIPPON PRECISION CIRCUITS-3 SM5902AF Absolute maximum ratings Parameter Supply voltage Input voltage Storage temperature Power dissipation Soldering temperature Soldering time Symbol VDD VI TSTG PD TSLD (VSS = 0V, VDD1, VDD2 pin voltage = VDD) Rating Unit - 0.3 to 7.0 VSS - 0.3 to VDD + 0.3 - 55 to 125 350 255 10 V V ˚C mW ˚C sec tSLD (*1) Refer to pin summary on the next page. Note. Values also apply for supply inrush and switch-off. Electrical characteristics Recommended operating conditions (VSS = 0V, VDD1, VDD2 pin voltage = VDD) Parameter Supply voltage Operating temperature Symbol VDD TOPR Rating 2.4 to 5.5 - 40 to 85 Unit V ˚C DC characteristics Standard voltage: (VDD1 = VDD2 = 4.5 to 5.5 V, VSS = 0 V, Ta = - 40 to 85 ˚C) Parameter Current consumption Input voltage Pin VDD CLK H level L level (*2,3,4) (*5) Output voltage (*4,6) (*5,7) Input current CLK (*3,4) Input leakage current (*2,3,4,5) (*2,5) H level L level H level L level H level L level H level L level IIH1 IIL1 IIL2 ILH ILL Symbol IDD VIH1 VIL1 VINAC VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 IOH = - 0.5 mA IOL = 0.5 mA IOH = - 0.5 mA IOL = 0.5 mA VIN = VDD VIN = 0V VIN = 0V VIN = VDD VIN = 0V 40 40 6 95 95 12 VDD - 0.4 0.4 190 190 25 1.0 1.0 VDD - 0.4 0.4 0.6VDD 0.2VDD AC coupling 0.3 0.7VDD 0.3VDD Condition Min (*A)SHPRF ON (*A)Through mode 0.7VDD 0.3VDD Rating Typ 13.5 5.0 Max 25.0 7.5 mA mA V V VP-P V V V V V V V V µA µA µA µA µA Unit (*A) VDD1 = VDD2 = 5 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD1 = VDD2 = 5 V. NIPPON PRECISION CIRCUITS-4 SM5902AF Low-voltage:(VDD1 = VDD2 = 2.4 to 4.5 V, VSS = 0 V, Ta = - 20 to 70 ˚C) Parameter Current consumption Input voltage Pin VDD CLK H level L level (*2,3,4) (*5) Output voltage (*4,6) (*5,7) Input current CLK (*3,4) Input leakage current (*2,3,4,5) (*2,5) H level L level H level L level H level L level H level L level IIH1 IIL1 IIL2 ILH ILL Symbol IDD VIH1 VIL1 VINAC VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 IOH = - 0.5 mA IOL = 0.5 mA IOH = - 0.5 mA IOL = 0.5 mA VIN = VDD VIN = 0V VIN = 0V VIN = VDD VIN = 0V 10 10 1.5 30 30 3 VDD - 0.4 0.4 115 115 15 1.0 1.0 VDD - 0.4 0.4 0.6VDD 0.2VDD AC coupling 0.3 0.7VDD 0.3VDD Condition Min (*B)SHPRF ON (*B)Through mode 0.7VDD 0.3VDD Rating Typ 6.0 2.5 Max 12.0 4.0 mA mA V V VP-P V V V V V V V V µA µA µA µA µA Unit (*B) VDD1 = VDD2 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD1 = VDD2 = 3 V. (*1) (*2) Pin function Pin name Pin function Pin name (*3) (*4) (*5) (*6) (*7) Pin function Pin name Pin function Pin name Pin function Pin name Pin function Pin name Pin function Pin name Clock input pin (AC input) CLK Schmitt input pins YSRDATA, YLRCK, YSCK, YFLAG, YFCLK, NRESET, YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK Schmitt input pin with pull-up NTEST I/O pins (Schmitt input with pull-up in input state) UC1, UC2, UC3, UC4, UC5 I/O pins (Schmitt input in input state) D0, D1, D2, D3 Outputs ZSCK, ZLRCK, ZSRDATA, ZSENSE, DIT Outputs NCAS, NWE, NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9,A10 NIPPON PRECISION CIRCUITS-5 SM5902AF AC characteristics Standard voltage: VDD1 = VDD2 = 4.5 to 5.5 V, VSS = 0 V, Ta = -40 to 85 ˚C Low-voltage: VDD1 = VDD2 = 2.4 to 4.5 V, VSS = 0 V, Ta = -20 to 70 ˚C (*) Typical values are for fs = 44.1 kHz System clock (CLK pin) Parameter Clock pulsewidth (HIGH level) Clock pulsewidth (LOW level) Clock pulse cycle Symbol Condition System clock Min 26 26 384fs 56 Rating Typ 29.5 29.5 59 Max 125 125 250 ns ns ns Unit tCWH tCWL tCY System clock input CLK t CWH t CY t CWL 0.5VDD Serial input (YSRDATA, YLRCK, YSCK pins) Parameter YSCK pulsewidth (HIGH level) YSCK pulsewidth (LOW level) YSCK pulse cycle YSRDATA setup time YSRDATA hold time Last YSCK rising edge to YLRCK edge YLRCK edge to first YSCK rising edge YLRCK pulse frequency See note below. fs fs Symbol Min Rating Typ Max ns ns ns ns ns ns ns 3fs Memory system ON (MSON=H) Memory system OFF (MSON=L) Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode operation. 75 75 150 50 50 50 50 0 Unit Condition tBCWH tBCWL tBCY tDS tDH tBL tLB t BCWH YSCK t DS YSRDATA t BL YLRCK t DH t BCY t BCWL 0.5VDD 0.5VDD t LB 0.5VDD NIPPON PRECISION CIRCUITS-6 SM5902AF Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins) Parameter YMCLK LOW-level pulsewidth YMCLK HIGH-level pulsewidth YMDATA setup time YMDATA hold time YMLD LOW-level pulsewidth YMLD setup time YMLD hold time Rise time Fall time ZSENSE output delay Note. tCY is the system clock cycle time (59ns typ). Symbol Min Rating Typ Max ns ns ns ns ns ns ns 100 100 100 + 3tCY ns ns ns 30 + 2tCY 30 + 2tCY 30 + tCY 30 + tCY 30 + 2tCY 30 + tCY 30 + tCY Unit tMCWL tMCWH tMDS tMDH tMLWL tMLS tMLH tr tf tPZS YMDATA t MDS YMCLK t MCWL YMLD t MLWL ZSENSE t PZS t MLS t MCWH t MLH t MDH 0.5VDD 0.5VDD 0.5VDD 0.5VDD tf YMCLK YMDATA YMLD 0.7 V DD 0.3 V DD tr 0.7 V DD 0.3 V DD 0.5VDD Reset input (NRESET pin) Parameter First HIGH-level after supply voltage rising edge NRESET pulsewidth Note. tCY is the system clock (CLK) input (384fs) cycle time. Symbol Min Rating Typ Max 0 64 Unit tHNRST tNRST tCY (Note) tCY (Note) tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz VDD NRESET t HNRST t NRST NIPPON PRECISION CIRCUITS-7 SM5902AF Serial output (ZSRDATA, ZLRCK, ZSCK pins) Parameter ZSCK pulsewidth ZSCK pulse cycle ZSRDATA and ZLRCK output delay time Symbol Condition Min 15 pF load 15 pF load 15 pF load 15 pF load 0 0 Rating Typ 1/96fs 1/48fs 60 60 ns ns Max Unit tSCOW tSCOY tDHL tDLH ZSCK t SCOW t SCOW t SCOY ZSRDATA ZLRCK t DHL t DLH 0.5VDD 0.5VDD DRAM access timing (NRAS, NCAS, NCAS2, NWE, A0 to A10, D0 to D3) Parameter NRAS pulsewidth NRAS falling edge to NCAS falling edge NCAS pulsewidth NRAS falling edge to address NCAS falling edge to address NCAS falling edge to data write NCAS rising edge to data read Setup time Hold time Setup time Hold time Setup time Hold time Input setup Input hold Symbol Condition Min 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 40 0 15 pF load 15 pF load Non compression 1M 6-bit compression Rating Typ 5 3 2 5 3 1 1 1 5 3 3 Max Unit NWE pulsewidth NWE falling edge to NCAS falling edge Refresh cycle (fs = 44.1 kHz playback) tRASL tRASH tRCD tCASH tCASL tRADS tRADH tCADS tCADH tCWDS tCWDH tCRDS tCRDH tWEL tWCS tCY(note) tCY tCY tCY tCY tCY tCY tCY tCY tCY tCY ns ns 6 3 1.5 3.7 4.4 5.5 3.0 7.3 8.8 10.9 5.9 14.6 17.5 21.8 tCY tCY ms ms ms ms ms ms ms ms ms ms ms ms DRAM 5-bit compression tREF Memory system ON Decode sequence operation (RDEN=H) ×1 4M 4-bit compression Non compression 6-bit compression DRAM 5-bit compression × 1 or × 2 4-bit compression Non compression 16M ×1 6-bit compression DRAM 5-bit compression 4-bit compression Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz NIPPON PRECISION CIRCUITS-8 SM5902AF DRAM access timing (with single DRAM) t RASL 5 tCY NRAS t RCD 2tCY NCAS t CASL 3 tCY t CASH 5tCY t RASH 3 tCY ,,,,,,, A0 to A10 ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, D0 to D3 (WRITE) t RADS 1tCY t RADH 1tCY t CADS 1tCY t CADH 5tCY t CWDS 3tCY t CWDH 3tCY ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, D0 to D3 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (READ) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, t WCS 3tCY t WEL 6tCY t CRDS t CRDH NWE (WRITE) The NWE terminal output is fixed HIGH during read timing. DRAM access timing (with 2 DRAMs) t RASL 5 tCY NRAS t RCD 2tCY t CASL 3tCY t CASH 5tCY t RASH 3tCY NCAS (DRAM1 SELECT) NCAS2 (DRAM2 SELECT) t RDC 2 tCY t CASL 3tCY t CASH 5tCY A0 to A9 ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t RADS 1tCY t RADH 1tCY t CADS 1tCY t CADH 5tCY D0 to D3 (WRITE) t CWDS 3tCY t CWDH 3tCY ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, D0 to D3 (READ) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, t 3 tCY WCS t CRDS t CRDH NWE (WRITE) t WCS t WEL 6 tCY The NWE terminal output is fixed HIGH during read timing. NCAS terminal output is fixed HIGH when selecting "DRAM2". NCAS2 terminal output is fixed HIGH when selecting "DRAM1". NIPPON PRECISION CIRCUITS-9 SM5902AF DIT Interface (DIT pin) Parameter 0 data H level 0 data L level 1 data H level 1 data L level Symbol Condition Min 15 pF load 15 pF load 15 pF load 15 pF load Rating Typ 6 6 3 3 Max Unit tDI0H tDI0L tDI1H tDI1L tCY(Note) tCY tCY tCY Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz. DIT tDI0H 6tCY tDI0L 6tCY tDI1H tDI1L 3tCY 3tCY 0.5VDD NIPPON PRECISION CIRCUITS-10 SM5902AF Block diagram ZSRDATA ZLRCK ZSCK SM5902 YBLKCK YFCLK YFLAG Control Input 1 Output Interface Input Interface YMDATA Attenuator YMCLK YMLD ZSENSE DIT Compression Mode Through Mode Input Buffer Microcontroller Interface UC1 to UC5 General Port Decoder Encoder YDMUTE NRESET NTEST Control Input 2 DRAM Interface A0 to A10 NRAS NWE YSCK NIPPON PRECISION CIRCUITS-11 D0 to D3 NCAS2 NCAS CLK YSRDATA YLRCK SM5902AF Functional description SM5902AF has two modes of operation; shockproof mode and through mode. The operating sequences are controlled using commands from a microcontroller. Microcontroller interface Commands from the microcontroller are input using 3-wire serial interface inputs; data (YMDATA), bit clock (YMCLK) and load signal (YMLD). Write command format (Commands 80 to 86) DATA 8bit YMDATA D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 COMMAND 8bit B5 B4 B3 B2 B1 B0 In the case of a read command from the microcontroller, bit serial data is output (ZSENSE) synchronized to the bit clock input (YMCLK). YMCLK YMLD Write command format (Commands 87) DATA 12bit YMDATA D11 D10 D4 D3 D2 D1 D0 B7 B6 COMMAND 8bit B5 B4 B3 B2 B1 B0 YMCLK YMLD Read command format (Commands 90, 91, 93) COMMAND 8bit YMDATA B7 B6 B5 B4 B3 B2 B1 B0 YMCLK YMLD STATUS 8bit ZSENSE S7 S6 S5 S4 S3 S2 S1 S0 Read command format (Command 92 (memory residual read)) COMMAND 8bit YMDATA B7 B6 B5 B4 B3 B2 B1 B0 YMCLK YMLD RESIDUAL DATA 16bit ZSENSE S7 S6 S1 S0 M1 M2 M7 M8 NIPPON PRECISION CIRCUITS-12 SM5902AF Command table Write command summary MS command 80 B7 B6 B5 B4 Shock-proof memory system settings Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MSWREN MSWACL MSRDEN MSRACL MSDCN2 MSDCN1 WAQV MSON Function Encode sequence start/stop Write address reset Decode sequence start/stop Read address reset MSDCN2=H, MSDCN1=H: 3-pair comparison start MSDCN2=H, MSDCN1=L: 2-pair comparison start MSDCN2=L, MSDCN1=H: Direct-connect start MSDCN2=L, MSDCN1=L: Connect operation stop Q data valid Memory system ON 80hex = 1000 0000 H operation Reset level Start Reset Start Reset Valid ON Extension I/O settings 81 B7 B6 B5 B4 Extension I/O port input/output settings Bit D7 D6 D5 D4 D3 D2 D1 D0 UC5OE UC4OE UC3OE UC2OE UC1OE Extension I/O port UC5 input/output setting Extension I/O port UC4 input/output setting Extension I/O port UC3 input/output setting Extension I/O port UC2 input/output setting Extension I/O port UC1 input/output setting Name Function 81hex = 1000 0001 H operation Reset level Output Output Output Output Output Extension I/O output data settings 82 Extension port HIGH/LOW output level A port setting is invalid if that port has already been defined as an input using the 81H command above. Bit D7 D6 D5 D4 D3 D2 D1 D0 UC5WD UC4WD UC3WD UC2WD UC1WD Extension I/O port UC5 output data setting Extension I/O port UC4 output data setting Extension I/O port UC3 output data setting Extension I/O port UC2 output data setting Extension I/O port UC1 output data setting Name Function B7 B6 B5 B4 82hex = 1000 0010 H operation Reset level H output H output H output H output H output NIPPON PRECISION CIRCUITS-13 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L L L L L L L L L L L L L L SM5902AF ATT, MUTE settings 83 B7 B6 B5 B4 83hex = 1000 0011 Bit D7 D6 D5 D4 D3 D2 D1 D0 Refer to "Attenuation", "Soft mute", "Force mute", "12-bit comparison connection". Name ATT MUTE SOFT NS CMP12 Function Attenuator enable Forced muting (changes instantaneously) Soft muting (changes smoothly when ON only) Includes noise shaper function when encoding 12-bit comparison connect/ 16-bit comparison connect H operation Attenuator ON Reset level Mute ON Soft mute NS ON 12-bit comparison Attenuation level settings 84 B7 B6 B5 B4 B3 B2 B1 B0 84hex = 1000 0100 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name K7 K6 K5 K4 K3 K2 K1 K0 Function MSB 2-1 2 2 2 2 2 LSB 2 -2 -3 -4 -5 H operation Reset level 2-6 -7 -8 Refer to "Attenuation", "Soft mute", "Force mute". Option settings 85 B7 B6 B5 B4 85hex = 1000 0101 Bit D7 Name RAMS1 Function DRAM type setting RAMS1=0 RAMS2=0 when 1MDRAM(256k × 4bit) × single RAMS1=1 RAMS2=0 when 4MDRAM(1M × 4bit) × single D6 D5 RAMS2 YFLGS RAMS1=0 RAMS2=1 when 4MDRAM(1M × 4bit) × double RAMS1=1 RAMS2=1 when 16MDRAM(4M × 4bit) × single FLAG6 set conditions (reset using status read command 90H) - When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L - When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L D4 D3 D2 D1 D0 YFCKP COMPFB COMP6B COMP5B COMP4B - When YFLGS=1, YFCKP=0, YFLAG=L - When YFLGS=1, YFCKP=1, YFLAG=H Full-bit compression mode 6-bit compression mode 5-bit compression mode 4-bit compression mode L H L L L L L H operation Reset level When the number of compression bits is set incorrectly (2 or more bits in D0 to D3 are set to 1 or all bits are set to 0), 6-bit compression mode is selected. NIPPON PRECISION CIRCUITS-14 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L L H L L L L L L L SM5902AF Digital Audio Interface settings 86 B7 B6 B5 B4 86hex = 1000 0110 Bit D7 D6 Name CP1 CP2 Function Channel status and clock accuracy setting CP1= 0, CP2= 0 Level 2 (max ± 300 ppm) CP1= 0, CP2= 1 Level 3 (max ± 10 %) CP1= 1, CP2= 0 Level 1 (max ± 50 ppm) CP1= 1, CP2= 1 Not supported D5 D4 D3 D2 D1 D0 LBIT DIT Digital audio signal generation logic. 0 = post-recording software Digital audio interface (DIT) enable. 0 = DIT output LOW Unassigned DIT= ON L L L H operation Reset level Sub code Q data settings 87 B7 B6 B5 B4 87hex = 1000 0111 Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name QAD3 QAD2 QAD1 QAD0 QD7 QD6 QD5 QD4 QD3 QD2 QD1 QD0 LSB Function Q data setting and word address specification QAD3 (MSB) to QAD0 (LSB) specify one of 10 valid addresses in the range 0000 to 1001. * If an address in the range 1010 to 1111 is specified, the data on QD7 to QD0 is ignored. Note that writing to address 1001 also functions as the write stop command. MSB Q data setting ward data Q data setting ward data Q data setting ward data Q data setting ward data Q data setting ward data Q data setting ward data Q data setting ward data Q data setting ward data H operation Reset level Indefined Indefined Indefined Indefined Indefined Indefined Indefined Indefined Adderss map for Q data setting beuffer QAD3 0 0 0 0 0 0 0 0 1 1 QAD2 0 0 0 0 1 1 1 1 0 0 QAD1 0 0 1 1 0 0 1 1 0 0 QAD0 0 1 0 1 0 1 0 1 0 1 QD7 CTL0 DQ1 DQ9 DQ17 DQ25 DQ33 DQ41 DQ49 DQ57 DQ65 QD6 CTL1 DQ2 DQ10 DQ18 DQ26 DQ34 DQ42 DQ50 DQ58 DQ66 QD5 CTL2 DQ3 DQ11 DQ19 DQ27 DQ35 DQ43 DQ51 DQ59 DQ67 QD4 CTL3 DQ4 DQ12 DQ20 DQ28 DQ36 DQ44 DQ52 DQ60 DQ68 QD3 ADR3 DQ5 DQ13 DQ21 DQ29 DQ37 DQ45 DQ53 DQ61 DQ69 QD2 ADR2 DQ6 DQ14 DQ22 DQ30 DQ38 DQ46 DQ54 DQ62 DQ70 QD1 ADR1 DQ7 DQ15 DQ23 DQ31 DQ39 DQ47 DQ55 DQ63 DQ71 QD0 ADR0 DQ8 DQ16 DQ24 DQ32 DQ40 DQ48 DQ56 DQ64 DQ72 When shockproof mode is ON, the Q data is specified according to the data output from the SM5902AF. NIPPON PRECISION CIRCUITS-15 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L SM5902AF Read command summary Shock-proof memory status (1) 90 B7 B6 B5 B4 90hex = 1001 0000 Bit S7 S6 S5 S4 S3 S2 S1 S0 Refer to "Status flag operation summary". DCOMP MSWIH MSRIH Data compare-connect sequence operating Encode sequence stop due to internal factors Decode sequence stop due to internal factors Compare-connect sequence operating Encoding stopped Decoding stopped Name FLAG6 MSOVF BOVF Function Signal processor IC jitter margin exceeded Write overflow (Read once only when RA exceeds WA) Input buffer memory overflow because sampling rate of input data is too fast HIGH-level state Exceeded DRAM overflow Input buffer memory overflow Shock-proof memory status (2) 91 B7 B6 B5 B4 B3 B2 B1 B0 91hex = 1001 0001 Bit S7 S6 S5 S4 S3 S2 S1 S0 Refer to "Status flag operation summary". Name MSEMP OVFL ENCOD DECOD QRDY Function Valid data empty state (Always HIGH when RA exceeds VWA) Write overflow state (Always HIGH when WA exceeds RA) Encode sequence operating state Decode sequence operating state Subcode Q data write-buffer write enable HIGH-level state No valid data Memory full Encoding Decoding Write enabled NIPPON PRECISION CIRCUITS-16 B3 B2 B1 B0 SM5902AF Shock-proof memory valid data residual 92 B7 B6 B5 B4 92hex = 1001 0010 Bit S7 S6 S5 S4 S3 S2 S1 S0 M1 M2 M3 M4 M5 M6 M7 M8 Name AM21 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12 AM11 AM10 AM09 AM08 AM07 AM06 Function Valid data accumulated VWA-RA (MSB) 8M bits 4M bits 2M bits 1M bits 512k bits 256k bits 128k bits 64k bits 32k bits 16k bits 8k bits 4k bits 2k bits 1k bits 512 bits 256 bits Note. The time conversion factor varies depending on the compression bit mode.(M = 1,048,576 K= 1,024) Residual time (sec) = Valid data residual (Mbits) × Time conversion value K where the Time conversion value K (sec/Mbit) ≈ 2.78 (4 bits), 2.22 (5 bits), 1.85 (6 bits) and 0.74 (Full bits). Extension I/O inputs 93 Input data entering (or output data from) an extension port terminal is echoed to the microcontroller. (That is, the input data entering an I/O port configured as an input port using the 81H command, OR the output data from a pin configured as an output port using the 82H command.) Bit S7 S6 S5 S4 S3 S2 S1 S0 UC5RD UC4RD UC3RD UC2RD UC1RD Name Function B7 B6 B5 B4 93hex = 1001 0011 HIGH-level state NIPPON PRECISION CIRCUITS-17 B3 B2 B1 B0 B3 B2 B1 B0 SM5902AF Status flag operation summary Flag name FLAG6 Read method READ 90H bit 7 Set Meaning - Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a disturbance has exceeded the RAM jitter margin. - Set according to the YFLAG input and the operating state of YFCKP and YFLGS. FLAG6 set conditions When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L When YFLGS=1, YFCKP=0, YFLAG=L When YFLGS=1, YFCKP=1, YFLAG=H Reset - By 90H status read - By 80H command when MSON=ON - After external reset MSOVF READ 90H bit 6 Set Reset Meaning - Indicates once only that a write to external DRAM has caused an overflow. (When reset by the 90H status read command, this flag is reset even if the overflow condition continues.) - When the write address (WA) exceeds the read address (RA) - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset BOVF READ 90H bit 5 Meaning Set Reset - Indicates input data rate was too fast causing buffer overflow and loss of data - When inputs a data during a buffer memory overflow - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset DCOMP READ 90H bit 3 Reset Meaning Set - Indicates that a compare-connect sequence is operating - When a (3-pair or 2-pair) compare-connect start command is received (MSDCN2=1) - When a direct connect command is received (MSDCN2=0, MSDCN1=1) - When a (3-pair or 2-pair) comparison detects conforming data - When the connect has been performed after receiving a direct connect command - When a compare-connect stop command (MSDCN2=0, MSDCN1=0) is received - When a MSWREN=1 command is received (However, if a compare-connect command is received at the same time, the compare-connect command has priority.) - After external reset MSWIH READ 90H bit 2 Set Meaning - Indicates that the encode sequence has stopped due to internal factors (not microcontroller commands) - When FLAG6 (above) is set - When BOVF (above) is set - When MSOVF (above) is set Reset - When conforming data is detected after receiving a compare-connect start command - When the connect has been performed after receiving a direct connect command - When a read address clear (MSRACL) or write address clear (MSWACL) command is received - After external reset MSRIH READ 90H bit 1 Set Reset Meaning - Indicates that the decode sequence has stopped due to internal factors (not microcontroller commands) - When the valid data residual becomes 0 - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset NIPPON PRECISION CIRCUITS-18 SM5902AF Flag name MSEMP Read method READ 91H bit 7 Reset Meaning Set - Indicates that the valid data residual has become 0 - When the VWA (final valid data's next address) = RA (address from which the next read would take place) - Whenever the above does not apply - Indicates a write to external DRAM overflow state - When the write address (WA) exceeds the read address (RA). (Note: This flag is not set when WA=RA through an address initialize or reset operation.) Reset - When the read address (RA) is advanced by the decode sequence - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset Meaning Set OVFL READ 91H bit 6 ENCOD READ 91H bit 5 Meaning Set - Indicates that the encode sequence (input data entry, encoding, DRAM write) is operating - By the 80H command when MSWREN=1 - When conforming data is detected during compare-connect operation - When the connect has been performed after receiving a direct connect command Reset - When the FLAG6 flag=1 (above) - When the OVFL flag=1 (above) - By the 80H command when MSWREN=0 - By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command) - By the 80H command when MSON=0 - After external reset Note. Reset conditions have priority over set conditions. For example, if the 80H command has MSWREN=1 and MSDCN1=1, the ENCOD flag is reset and compare-connect operation starts. DECOD READ 91H bit 4 Meaning Set Reset Meaning Set Reset - Indicates that the decode sequence (read from DRAM, decoding, attenuation, data output) is operating - By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above) - Whenever the above does not apply Subcode Q data write-buffer write enable indicator After internal subcode Q data write-buffer contents are read out. When data is written to address 1001 using the 87H command. QRDY READ 91H bit 3 NIPPON PRECISION CIRCUITS-19 SM5902AF Write command supplementary information 80H (MS command) - MSWREN When 1: Encode sequence starts Invalid when MSON is not 1 within the same 80H command Invalid when FLAG6=1 Invalid when OVFL=1 Invalid when a compare-connect start command (MSDCN2=1 or MSDCN1=1) occurs simultaneously Direct connect if a compare-connect sequence is already operating When 0: Encode sequence stops - MSWACL When 1: Initializes the write address (WA) When 0: No operation - MSRDEN When 1: Decode sequence starts Does not perform decode sequence if MSON=1.If there is no valid data, decode sequence temporarily stops. But, because the MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. When 0: Decode sequence stops -MSRACL When 1: Initializes the read address (RA) When 0: No operation - MSDCN2, MSDCN1 When 1 and 1: 3-pair compare-connect sequence starts When 1 and 0: 2-pair compare-connect sequence starts When 0 and 1: Direct connect sequence starts When 0 and 0: Compare-connect sequence stops. No operation if a compare-connect sequence is not operating. - WAQV When 1: The immediately preceding YBLKCK falling-edge timing WA (write address) becomes the VWA (valid write address). When 0: No operation - MSON When 1: Memory system turns ON and shockproof operation starts When 0: Memory system turns OFF and throughmode playback starts. (In this mode, the attenuator is still active.) 81H (Extension I/O port settings) 82H (Extension I/O port output data settings) NIPPON PRECISION CIRCUITS-20 SM5902AF 83H (ATT, MUTE, 12-bit comparison connection settings) - ATT (attenuator enable) When 1: Attenuator settings become active (84H command) When 0: Attenuator settings become inactive, and output continues without attenuation - MUTE (forced muting) When 1: Outputs are instantaneously muted to 0.(note 1) Same effect as taking the YDMUTE pin HIGH. When 0: No muting(note 1) (note1) Effective at the start of left-channel output data. - SOFT (soft muting) When 1: Outputs are smoothly muted to 0. When 0: No muting. Soft mute release occurs instantaneously to either the value set by the 84H command (When ATT=1) or 0dB (When ATT=0) 85H (option settings) - RAMS1, RAMS2 When 0 and 0 : 1M DRAMs (256k×4 bits)×single When 1 and 0 : 4M DRAMs (1M×4 bits)×single When 0 and 1 : 4M DRAMs (1M×4 bits)×double When 1 and 1 : 16M DRAMs (4M×4 bits)×single - RAMX2 When 1: Uses 2 DRAMs When 0: Uses a single DRAM - YFLGS, YFCKP When 0 and 0: Sets FLAG6 on the falling edge of YFCLK when YFLAG=0 When 0 and 1: Sets FLAG6 on the rising edge of YFCLK when YFLAG=0 When 1 and 0: Sets FLAG6 when YFLAG=0 When 1 and 1: Sets FLAG6 when YFLAG=1 - COMPFB, COMP6B, COMP5B, COMP4B When 0, 0, 0 and 1: Selects 4-bit compression mode When 0, 0, 1 and 0: Selects 5-bit compression mode When 1, 0, 0 and 0: Selects full-bit compression mode In all other cases: Selects 6-bit compression mode Changing mode without initializing during operation is possible. - MUTE, SOFT, YDMUTE relationship When all mute inputs are 0, mute is released. - NS (noise shaper enable) When 1: Includes noise shaper function in compression-mode shockproof operation. When 0: Performs comparison connection using all 16 bits of input data. - CMP12 (12-bit comparison connection) When 1: Performs comparison connection using only the most significant 12 bits of input data. When 0: Performs comparison connection using all 16 bits of input data. NIPPON PRECISION CIRCUITS-21 SM5902AF 86H (digital audio interface settings) - CP1, CP2 (channel status and clock accuracy setting) When 0 and 0: Level 2 (max ± 300 ppm) When 0 and 1: Level 3I (max ± 10%) When 1 and 0: Level 1 (max ± 50 ppm) When 1 and 1: Not supported - LBIT (digital audio signal generation logic) When 1: Not assigned When 0: Post-recording software - DIT (digital audio interface enable) When 1: DIT output enable When 0: DIT LOW-level output 87H (subcode Q data setting) - QAD3 to QAD0 (Q data setting and word address specification) QAD3 (MSB) to QAD0 (LSB) specify one of 10 valid addresses in the range 0000 to 1001. If an address in the range 1010 to 1111 is specified, the data on QD7 to QD0 is ignored. Note that writing to address 1001 also functions as the write stop command. - QD7 to QD0 (Q data setting and word data) The CD Q-channel has the general data format shown below. The write data required to fully specify the Q data is the 80 bits comprising CONTROL, ADR, and DATA-Q. The CRC write data is not required because it is generated by recalculation. S0, S1 bit 0 Control 1 2 3 4 ADR 5 6 7 8 9 DATA-Q 78 79 80 CRC 95 S0, S1 80 bit 96 bit Adderss map for Q data setting beuffer QAD3 0 0 0 0 0 0 0 0 1 1 QAD2 0 0 0 0 1 1 1 1 0 0 QAD1 0 0 1 1 0 0 1 1 0 0 QAD0 0 1 0 1 0 1 0 1 0 1 QD7 CTL0 DQ1 DQ9 DQ17 DQ25 DQ33 DQ41 DQ49 DQ57 DQ65 QD6 CTL1 DQ2 DQ10 DQ18 DQ26 DQ34 DQ42 DQ50 DQ58 DQ66 QD5 CTL2 DQ3 DQ11 DQ19 DQ27 DQ35 DQ43 DQ51 DQ59 DQ67 QD4 CTL3 DQ4 DQ12 DQ20 DQ28 DQ36 DQ44 DQ52 DQ60 DQ68 QD3 ADR3 DQ5 DQ13 DQ21 DQ29 DQ37 DQ45 DQ53 DQ61 DQ69 QD2 ADR2 DQ6 DQ14 DQ22 DQ30 DQ38 DQ46 DQ54 DQ62 DQ70 QD1 ADR1 DQ7 DQ15 DQ23 DQ31 DQ39 DQ47 DQ55 DQ63 DQ71 QD0 ADR0 DQ8 DQ16 DQ24 DQ32 DQ40 DQ48 DQ56 DQ64 DQ72 - Subcode Q data setting process Initially, data is written to word address range 0000 to 1000, and then data is written to address 1001. Next, only data that needs to be changed is written if the 91H command QRDY bit is 1, and then address 1001 is written again. Note that when shockproof mode is ON, the Q data is specified according to the data output from the SM5902AF. NIPPON PRECISION CIRCUITS-22 SM5902AF Shock-proof operation overview Shock-proof mode is the mode that realizes shockproof operation using external DRAM. Shock-proof mode is invoked by setting MSON=H in microcontroller command 80H. This mode comprises the following 3 sequences. - Encode sequence 1. Input data from a signal processor IC is stored in internal buffers. 2. Encoder starts after a fixed number of data have been received. - Decode sequence 1. Reads compressed data stored in external buffer RAM at rate fs. 2. Decoder starts, using the predicting filter type and quantization levels used when encoded. 3. Performs attenuation operation (including muting operation) 4. Outputs the result. 3. The encoder, after the most suitable predicting filter type and quantization steps have been determined, performs ADPCM encoding and then writes to external DRAM. - Compare-connect sequence 1. Encoding immediately stops when either external buffer RAM overflows or when a CD read error occurs due to shock vibrations. 2. Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. 3. Compares data re-read from the CD with the processed final valid data stored in RAM (confirms its correctness). 4. As soon as the comparison detects conforming data, compare-connect sequence stops and encode sequence re-starts, connecting the data directly behind previous valid data. NIPPON PRECISION CIRCUITS-23 SM5902AF RAM addresses The SM5902 uses either 1 or 2 external 1M or 4M DRAMs as external buffers. Three kinds of addresses are used for external RAM control. WA (write address) RA (read address) VWA (valid write address) Among these, VWA is the write address for conforming data whose validity has been confirmed. Determination of the correctness of data read from the CD is delayed relative to the encode write processing, so VWA is always delayed relative to WA. The region available for valid data is the area between VWA-RA. - Connect data work area This is an area of memory reserved for connect data. This area is 2k bits if using 1M DRAMs, 4k bits if using 4M DRAMs, or 8k bits if using 16M DRAMs. VWA (valid write address) The VWA is determined according to the YBLKCK pin and WAQV command. Refer to the timing chart below. 1.YBLKCK is a 75 Hz clock(HIGH for 136 µs) when used for normal read mode and it is a 150 Hz clock when used for double-speed read mode, synchronized to the CD format block end timing. When this clock goes LOW, WA which is the write address of internal encode sequence, is stored (see note 2). Connect data work area RA WA VWA Valid data area Fig 1. RAM addresses 2.The microcontroller checks the subcode and, if confirmed to be correct, generates a WAQV command (80H). 3.When the WAQV command is received, the previously latched WA is stored as the VWA. (note 2) Actually, there is a small time difference, or gap, between the input data and YBLKCK. This gap serves to preserves the preceding WA to protect against incorrect operation. 13.3ms YBLKCK Microcontroller data set Refer to Microcontroller interface VWA latch set WAQV set VWA VWA(x) VWA(x + 1) Values shown are for rate fs. The values are 1/2 those shown at rate 2fs. Fig 2. YBLKCK and VWA relationship NIPPON PRECISION CIRCUITS-24 SM5902AF YFLAG, YFCLK, FLAG6 Correct data demodulation becomes impossible for the CD signal processor IC when a disturbance exceeding the RAM jitter margin occurs. The YFLAG signal input pin is used to indicate when such a condition has occurred. The YFCLK is a 7.35 kHz clock synchronized to the CD format frame 1. The IC checks the YFLAG input and stops the encode sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depending on the YFLGS flag and YFCKP flag (85H command). See table1. If YFLAGS is set to 1, then YFCLK should be tied either High or Low. 85H command YFLGS 1 2 3 4 1 0 YFCKP 0 1 0 1 FLAG6 set conditions When YFLAG=LOW on YFCLK input falling edge When YFLAG=LOW on YFCLK input rising edge When YFLAG=LOW When YFLAG=HIGH YFCLK be tied either High or Low FLAG6 reset conditions - By status read (90H command) - When MSON=LOW - After system reset Table 1. YFLAG signal check method NIPPON PRECISION CIRCUITS-25 SM5902AF Compare-connect sequence The SM5902AF supports three kinds of connect modes; 3-pair compare-connect, 2-pair compareconnect and direct connect. Note that the SM5902AF can also operate in 12-bit comparison connect mode using only the most significant 12 bits of data for connection operation. In 3-pair compare-connect mode, the final 6 valid data (3 pairs of left- and right-channel data input before encode processing) and the most recently input data are compared until three continuous data pairs all conform. At this point, the encode sequence is re-started and data is written to VWA. In 2-pair compare-connect mode, comparison occurs just as for 3-pair comparison except that only 2 pairs from the three compared need to conform with the valid data. At this point, the encode sequence is re-started and data is written to VWA. In direct-connect mode, comparison is not performed at all, and encode sequence starts and data is written to the VWA. This mode is for systems that cannot perform compare-connect operation. - Compare-connect preparation time 1. Comparison data preparation time Internally, when the compare-connect start command is issued, a sequence starts to restore the data for comparison. The time required for this preparation after receiving the command is approximately 2.5 × (1/fs). (approximately 60 µs when fs = 44.1 kHz) 2. After the above preparation is finished, data is input beginning from the left-channel data and comparison starts. 3. If the compare-connect command is issued again, the preparation time above is not necessary and operation starts from step 2. 4. The same sequence takes place in direct-connect mode also. However, at the point when 3 words have been input, all data is directly connected as if comparison and conformance had taken place. - Compare-connect sequence stop If a compare-connect stop command (80H with MSDCN1= 1, MSDCN2= 0) is input from the microcontroller, compare-connect sequence stops. If compare-connect sequence was not operating, the compare-connect stop command performs no operation. However, make sure that the other bit settings within the same 80H command are valid. NIPPON PRECISION CIRCUITS-26 SM5902AF Encode sequence temporary stop - When RAM becomes full, MSWREN is set LOW using the 80H command and encode sequence stops. (For details of the stop conditions, refer to the description of the ENCOD flag.) - Then, if MSWREN is set HIGH without issuing a compare-connect start command, the encode sequence re-starts. At this time, new input data is written not to VWA, but to WA. In this way, the data already written to the region between VWA and WA is not lost. - But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued. After comparison and conformance are detected, no operation is performed because the encode sequence has already been started. However, make sure that the other bit settings within the same 80H command are valid. DRAM refresh - DRAM initialization refresh A 15-cycle RAS-only refresh is carried out for DRAM initialization under the following conditions. When MSON changes from 0 to 1 using command 80H. When from MSON=1, MSRDEN=0 and MSWREN=0 states only MSWREN changes to 1. In this case, encode sequence immediately starts and initial data is written (at 2fs rate input) after a delay of 0.7ms. - Refresh during Shock-proof mode operation In this IC, a data access operation to any address also serves as a data refresh. Accordingly, there are no specific refresh cycles other than the initialization refresh cycle (described above). This has the resulting effect of saving on DRAM power dissipation. A data access to DRAM can occur in an encode sequence write operation or in a decode sequence read operation. Write sequence write operation stops during a connect operation whereas a read sequence read operation always continues while data is output to the D/A. The refresh rate for each DRAM during decode sequence is shown in the table below. The decode sequence, set by MSON=1 and MSRDEN=1, operates when valid data is in DRAM (when MSEMP=0). - When MSON=0, DRAM is not refreshed because no data is being accessed. Although MSON=1, DRAM is not refreshed if ENCOD=0 and DECOD=0 (both encode and decode sequence are stopped). DRAMs used (same for 1 or 2 DRAMs) Data compression mode 4 bit 5 bit 6 bit Full bit 1M (256K×4 bits) 5.44 ms 4.35 ms 3.63 ms 1.36 ms 4M (1M×4 bits) 10.88 ms 8.71 ms 7.26 ms 2.72 ms 16M(4M×4 bits) 21.77ms 17.42ms 14.52ms 5.81ms Table 2. Decode sequence refresh rate NIPPON PRECISION CIRCUITS-27 SM5902AF Selecting compression mode Even when the compression mode in selected with the 85H command during shock-proof operation,no malfunction occurs. The compression mode change is not performed immediately after input of the 85H command, but it is performed at the following timing. YMLD When 85H generated WA CAS 3FE 3FF 001 002 003 004 005 RA CAS Encode compression mode 3FD 3FE 3FF 001 002 A B Decode compression mode A B (note) CAS-000 is connect data. NIPPON PRECISION CIRCUITS-28 SM5902AF Through-mode operation If MSON is set LOW (80H command), an operating mode that does not perform shock-proof functions becomes active. In this case, input data is passed as-is (after attenuator and mute operations) to the output. External DRAM is not accessed. - In this case, input data needs to be at a rate fs and the input word clock must be synchronized to the CLK input (384fs). However, short range jitter can be tolerated (jitter-free system). - Jitter-free system timing starts from the first YLRCK rising edge after either (A) a reset (NRESET= 0) release by taking the reset input from LOW to HIGH or (B) by taking MSON from HIGH to LOW. Accordingly, to provide for the largest possible jitter margin, it is necessary that the YLRCK clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs (80 clock cycles). This jitter margin is the allowable difference between the system clock (CLK) divided by 384 (fs rate clock) and the YLRCK input clock. If the timing difference exceeds the jitter margin, irregular operation like data being output twice or, conversely, incomplete data output may occur. In the worst case, a click noise may also be generated. When switching from shock-proof mode to through mode, an output noise may be generated, and it is therefore recommended to use the YDMUTE setting to mute ZSRDATA until just before data output. Attenuation - The attenuation register is set by the 84H command. - The attenuation register set value becomes active when the 83H command sets the ATT flag to 1. When the ATT flag is 0, the attenuation register value is considered to be the equivalent of 256 for a maximum gain of 0 dB. - The gain (dB) is given from the set value (Datt) by the following equation. Gain = 20 × log(Datt/256) [dB]; left and right channels - For the maximum attenuation register set value (Datt = 255), the corresponding gain is -0.03 dB. But when the ATT flag is 0 (Datt = 256), there is no attenuation. - After a system reset initialization, the attenuation register is set to 64 (-12 dB). However, because the ATT flag is reset to 0, there is no attenuation. - When the attenuation register setting changes or when the ATT flag changes, the gain changes smoothly from the previous set gain towards the new set value. If a new value for the attenuation level is set before the previously set level is reached, the gain changes smoothly towards the latest setting. The gain changes at a rate of 4 × (1/fs) per step. A full-scale change (255 steps) takes approximately 23.3 ms (when fs = 44.1 kHz). See fig 3. set 1 set 3 Gain set 5 set 2 set 4 time Fig 3. Attenuation operation example NIPPON PRECISION CIRCUITS-29 SM5902AF Soft mute Soft mute operation is controlled by the SOFT flag using a built-in attenuation counter. Mute is ON when the SOFT flag is 1. When ON, the attenuation counter output decrement by 1 step at a time, thereby reducing the gain. Complete mute takes 1024/fs (or approximately 23.2 ms for fs = 44.1 kHz). Conversely, mute is released when the SOFT flag is 0. In this case, the attenuation counter instantaneously increases. The attenuation register takes on the value when the ATT flag was 1. If the ATT flag was 0, the new set value is 256 (0 dB). SOFT Attenation level or full scale (Gain) −∞ 256 step / 1024TS Fig 4. Soft mute operation example Force mute Serial output data is muted by setting the YDMUTE pin input HIGH or by setting the MUTE flag to 1. Mute starts and finishes on the leading left-channel bit. When MSON is HIGH and valid data is empty (MSEMP=H), the output is automatically forced into the mute state. 12-bit comparison connection When the CMP12 flag is set to 1, the least significant 4 bits of the 16-bit comparison connection input data are discarded and comparison connection is performed using the remaining 12 bits. Note that if the CMP12 flag is set to 1 during a comparison connection operation, only the most significant 12 bits are used for comparison connection from that point on. NIPPON PRECISION CIRCUITS-30 SM5902AF Digital audio interface When the DIT flag is set to 1, the digital audio interface output from pin DIT is enabled. The output data structure is modulated using a preamble and biphase mark encoding. M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2 Sub Frame Frame 191 Start Block Sub Frame Frame 1 Frame 0 Figure 5. Frame format 0 34 LSB 78 MSB LSB 27 28 MSB 31 Preamble (Sync Groupe) Auxiliary Digital Audio Sample Data V U C P Audio Sample Validity User Bit Data Audio Channel Status Sub Frame Parity Figure 6. Subframe format Preamble The preamble is a particular bit pattern used to perform subframe and block synchronization and discrimination, assigned to one of 4 time slot divisions (0 to 3), comprising 8 continuous biphase modulated transfer rate status indicators. Preamble Leading symbol = 0 B M W 11101000 11100010 11100100 There are 3 types of preamble. The leading preamble pattern of all blocks is preamble pattern B, which is then followed by preamble pattern M for channel 1, and preamble pattern W for channel 2. Channel coding Leading symbol = 1 00010111 00011101 00011011 The SM5902AF starts with 0, so only the preamble patterns for leading symbol = 0 are used. Digital audio sample data and auxiliary audio The digital audio sample data is a 20-bit digitized audio signal. Auxiliary audio data, on the other hand, can be audio sample data of varying length. The SM5902AF uses a 16-bit audio data structure internally with audio data output bits 4 to 11 set to 0 and bits 12 to 27 output in LSB first format. Audio sample validity The validity flag is set to 0 when the digital audio sample data is output correctly, or it is set to 1 if the output is incorrect. It is also set to 1 if encoding does not start when the device is operating in forced mute, microcontroller forced mute, and shockproof mode. NIPPON PRECISION CIRCUITS-31 SM5902AF User bit data User bit data is data specified by the user. The data is output, after the Q data has been specified, in the following sequence. 0 0 12 24 36 1164 0 0 1 1 • 1 1 0 0 Q1 Q2 • Q96 2 0 0 0 0 • 0 3 0 0 0 0 • 0 4 0 0 0 0 • 0 5 0 0 0 0 • 0 6 0 0 0 0 • 0 7 0 0 0 0 • 0 8 0 0 0 0 • 0 9 0 0 0 0 • 0 10 0 0 0 0 • 0 11 0 0 0 0 • 0 - Using Q data Initially, Q1 to Q80 are set using the 87H command, the DIT flag is set using the 86H command, and then data is output from DIT according to the digital audio interface format. Q 81 to Q 96 data are not required as these are set internally by CRC calculation. There are 2 Q data buffers; a data output buffer and a data storage buffer. As a result, after all data has been specified in the first data write, only that data that has changed needs to be written during the 2nd and subsequent data write operations. Note that address 1001 is the write stop command and is, therefore, required after every data write operation. When space becomes available in the data output buffer, QRDY is set to 1 (91H command status bit S3) to indicate available space and then the contents of the data storage buffer are transferred to the data output buffer. After data is transferred, a data write to address 1001 (write stop command) resets the QRDY flag to 0. The Q data buffer read access time for a complete data cycle is approximately 13.3 ms. Audio channel status The channel status are information bits transferred to indicate the audio sample data length, preemphasis, sampling frequency, time code, source 0 0 16 32 48 64 80 96 112 128 144 160 176 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 4 0 L= 1 0 0 0 0 0 0 0 0 0 0 5 0 R= 1 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 number, destination code, and other information. Seven bits comprising CP1, CP2, LBIT, and CTL0 to CTL3 can be set. All other bits are fixed. 8 1 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 12 0 CP1 0 0 0 0 0 0 0 0 0 0 13 0 CP2 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 15 LBIT 0 0 0 0 0 0 0 0 0 0 0 CTL0 CTL1 CTL2 CTL3 Subframe parity The parity bit is used to indicate the detection of an odd number of bit errors. It is set to 1 if the number of 1s in the digital audio interface 27-bit data is odd, and is set to 0 if the number of 1s is even. The 27bit data plus parity bit form 28-bit data that always has an even number of 1s. NIPPON PRECISION CIRCUITS-32 SM5902AF Timing charts Input timing (YSCK, YSRDATA, YLRCK) 16 16 YSCK L ch MSB MSB LSB LSB R ch LSB YSRDATA YLRCK 1/(3fs ) Output timing (ZSCK, ZSRDATA, ZLRCK) 1 9 24 33 48 ZSCK L ch MSB MSB LSB LSB R ch LSB ZSRDATA ZLRCK 1/fs NIPPON PRECISION CIRCUITS-33 SM5902AF DRAM write timing (NRAS, NCAS, NCAS2, NWE, A0 to A10, D0 to D3) Write timing (with single DRAM) t RASL NRAS t RDC NCAS t RADS A0 to A10 t RADH t CADS t CADH t CASL t RASH t CASH ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, t CWDS t CWDH ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, , ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, D0 to D3 (WRITE) t WEL NWE Write timing (with 2 DRAMs) t RASL NRAS t RDC NCAS1 (DRAM1 SELECT) t RDC NCAS2 (DRAM2 SELECT) t RADS A0 to A9 t RADH t CADS t CADH t CASL t CASL t RASH t CASH t CASH ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t CWDS t CWDH ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, D0 to D3 (WRITE) t WEL NWE NIPPON PRECISION CIRCUITS-34 SM5902AF DRAM read timing (NRAS, NCAS, NCAS2, NWE, A0 to A10, D0 to D3) Read timing (with single DRAM) t RASL NRAS t RCD NCAS t RADS A0 to A10 ,,,,,,,, t CRDS t CRDH D0 to D3 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (READ) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, t RADH t CADS t CADH t CASL t RASH t CASH ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, t OEL ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, NWE Read timing (with 2 DRAMs) t RASL NRAS t RCD NCAS1 (DRAM1 SELECT) t RCD NCAS2 (DRAM2 SELECT) t RADS A0 to A9 t RADH t CADS t CADH t CASL t CASL t RASH t CASH t CASH ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, t CRDS t CRDH ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, D0 to D3 (READ) NWE NIPPON PRECISION CIRCUITS-35 SM5902AF Connection example SM5902 Microcontroller YMDATA YMCLK YMLD ZSENSE UC1 to UC5 DIT DRAM 1 YBLKCK YFCLK YFLAG NRAS NWE A0 to A10 D0 to D3 NCAS RAS WE A0 to A10 D0 to D3 CAS OE DRAM 2 RAS WE A0 to A9 D0 to D3 CAS OE DSP Matsushita MN662740 YSCK YLRCK YSRDATA ZSCK ZLRCK ZSRDATA CLK NRESET YDMUTE NCAS2 D/A converter SM5902 Microcontroller YMDATA YMCLK YMLD ZSENSE UC1 to UC5 DIT DRAM 1 SCOR XROF DSP SONY CXD2517 YSCK YLRCK YSRDATA YBLKCK YFLAG YFCLK NRAS NWE A0 to A10 D0 to D3 NCAS NCAS2 ZSCK ZLRCK ZSRDATA CLK NRESET YDMUTE D A RAS WE A0 to A10 D0 to D3 CAS OE DRAM 2 RAS WE A0 to A9 D0 to D3 CAS OE note1 - When 2 DRAMs are used, the DRAM OE pins should be tied LOW. - When single DRAM is used, the DRAM OE pin should be tied LOW or controlled by the SM5902 NOE signal. note 2 When CXD 2517 (Sony) is used Set 85H of microcontroller command (option setting) as setting YFLAG take in; D5: YFLAGS= 1 D4: YFCKP= 0 NIPPON PRECISION CIRCUITS-36 SM5902AF Device comparison with SM5856A1F Pin differences Pin No. 1 7 8 22 27 SM5856A1F VDD NTEST1 NTEST2 UC6 NOE / NCAS2 SM5902AF VDD2 DIT NTEST VDD1 A10 / NCAS2 VDD pins The SM5902AF operates from a 3 V supply voltage, but a built-in level shifter is provided for use with external 5 V DRAM ICs. There are, therefore, 2 supply pins. VDD1 is the internal 3 V IC supply, and VDD2 is the external DRAM interface supply. If, however, the DRAM also operates from a 3 V supply, VDD1 and VDD2 can be connected to the same supply. DIT pin The SM5902AF incorporates a digital audio interface output from pin DIT. Leave open circuit if not used. Microcontroller interface extensions The SM5902AF supports additional function extensions. Also, the UC6 pin has been removed, which Additional commands Command 83H 86H 87H 90H 91H Bit D4 D5 D4 to D7 D0 to D11 S5 S3 Name NS CMP12 CP1, 2, LBIT, DIT QAD0 to 3, QD0 to 7 BOVF QRDY Function Noise shaper ON/OFF switch 12-bit comparison connection ON/OFF switch Digital audio interface settings Subcode Q data settings Input buffer overflow Q data write buffer status means that UC6-related commands have been redefined. Modified commands Command 85H 92H Bit D6, D7 S0 to 7, M1 to 8 Name RAMS1, 2 AM06 to 21 Function External DRAM capacity Place of data residual Obsolete commands Command 81H 82H 93H Bit D5 D5 S5 Name UC6OE UC6WD UC6RD Function UC6 input/output settings UC6 output settings UC6 settings status NIPPON PRECISION CIRCUITS-37 SM5902AF Compression mode switching The SM5902AF guarantees correct operation if the compression mode is switched, using the 85H command, during normal operation. However, all other settings should remain unchanged while switching. Attenuation The SM5902AF supports attenuation level adjustments in steps 1/4 of the minimum level for smooth attenuation and soft muting. 16MDRAM The SM5902AF can use with up to 16MDRAM. (in case of SM5856A1F, up to 4M×2.) So you can get a long shock-proof time. Note that acceptable 16MDRAM is 2048-refresh type only. (Can not use with 4096-refresh type.) NIPPON PRECISION CIRCUITS-38 SM5902AF NIPPON PRECISION CIRCUITS-39 SM5902AF NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, FUKUZUMI 2 CHOME, KOTO-KU TOKYO,135-8430, JAPAN Telephon: +81-3-3642-6661 Facsimile: +81-3-3642-6698 NIPPON PRECISION CIRCUITS INC. NC9618BE 1999.8 NIPPON PRECISION CIRCUITS-40