SM5906AF

SM5906AF NIPPON PRECISION CIRCUITS INC. Shock-proof Memory Controller for Video CD Players Overview The SM5906AF is a shock-proof memory controller LSI for video CD players. The operating mode can be set to CD-DA mode, V-CD mode, or Super V-CD mode, and external memory can be selected from 2 options (4M, 16M). It operates from a 2.7 to 3.6 V supply voltage range. Features – 2-channel processing – Serial data input • 2s complement, 16-bit/MSB first • Right-justified format • Wide capture function (up to 4 × speed input rate) • Selectable 16/24/32-bit clock – System clock input • 384fs (16.9344 MHz) – Shock-proof memory controller • Selectable CD-DA/V-CD/SVC mode • 2 external DRAM configurations selectable 1 × 16M DRAM (4M × 4 bits, refresh cycle = 2048 cycle) 1 × 4M DRAM (1M × 4 bits) – Microcontroller interface • Serial command write and status read-out • Data residual detector: 11-bit operation, 16-bit output (Bits 13 to 15 bit are fixed LOW.) • Forced mute – Extension I/O Microcontroller interface for external control using 3 extension I/O pins – +2.7 to +3.6 V operating voltage range – Schmitt inputs All input pins (including I/O pins) except CLK (system clock) – Reset signal noise elimination Approximately 3.8 µs or longer (65 system clock pulses) continuous LOW-level reset - 48-pin QFP package (0.5 mm pin pitch) Pinout (Top View) YMCLK 27 YMDATA 26 NCAS 36 35 34 33 32 31 30 29 28 NRAS NWE VSS3 A10 D1 D0 D3 D2 Ordering Information SM5906AF 48pin QFP VDD4 A9 A8 A7 A6 A5 A4 A0 A1 A2 A3 VSS4 25 VDD3 24 23 22 21 37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 2 3 4 5 6 7 8 9 VSS2 YMLD YDMUTE ZSENSE NRESET YBLKCK YFLAG ZC2PO ZSRDATA ZSCK ZLRCK VDD2 SM5906AF JAPAN 20 19 18 17 16 15 14 13 YSRDATA YLRCK VDD1 NTEST1 NIPPON PRECISION CIRCUITS-1 YC2PO TEST2 YSCK VSS1 UC1 UC2 UC3 CLK SM5906AF Package dimensions (Unit: mm) 48-pin QFP 0.5 0.125 0.02 5 9 0.4 7 0.1 0.5 0.2 9 0.4 1.7max 0.1 0.1 0.18 0.05 7 0.1 1.4 0.1 0.5 Pin description Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin name VDD1 UC1 UC2 UC3 NTEST1 TEST2 CLK YC2PO YSRDATA YLRCK YSCK VSS1 VDD2 ZLRCK ZSCK I/O – Iu/O Iu/O Iu/O Iu Id I I I I I – – O O Function H VDD supply pin Microcontroller interface extension I/O 1 Microcontroller interface extension I/O 2 Microcontroller interface extension I/O 3 Test pin Test pin 16.9344 MHz clock input Serial input C2PO data Serial input data Serial input LR clock Serial input bit clock Ground VDD supply pin Serial output LR clock Serial output bit clock Left channel Right channel Left channel Right channel Test Test Setting L Iu : Input pin with pull-up resistor, Id : Input pin with pull-down resistor Iu/O : Input/Output pin (With pull-up resistor when in input mode) NIPPON PRECISION CIRCUITS-2 SM5906AF Pin description Pin number 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin name ZSRDATA ZC2PO YFLAG YBLKCK NRESET ZSENSE YDMUTE YMLD VSS2 VDD3 YMDATA YMCLK NRAS NCAS D2 D3 D0 D1 NWE A10 VSS3 VDD4 A9 A8 A7 A6 A5 A4 A0 A1 A2 A3 VSS4 I/O O O I I I O I I – – I I O O Iu/O Iu/O Iu/O Iu/O O O – – O O O O O O O O O O – Function H Serial output data Serial output C2PO data Signal processor IC RAM overflow flag Subcode block clock signal System reset pin Microcontroller interface status output Forced mute pin Microcontroller interface latch clock Ground VDD supply pin Microcontroller interface serial data Microcontroller interface shift clock DRAM RAS control DRAM CAS control DRAM data input/output 2 DRAM data input/output 3 DRAM data input/output 0 DRAM data input/output 1 DRAM WE control DRAM address 10 Ground VDD supply pin DRAM address 9 DRAM address 8 DRAM address 7 DRAM address 6 DRAM address 5 DRAM address 4 DRAM address 0 DRAM address 1 DRAM address 2 DRAM address 3 Ground Mute Reset Setting L Iu : Input pin with pull-up resistor, Id : Input pin with pull-down resistor Iu/O : Input/Output pin (With pull-up resistor when in input mode) NIPPON PRECISION CIRCUITS-3 SM5906AF Absolute maximum ratings (VSS1 = VSS2 = VSS3 = VSS4 = 0V, VDD1, VDD2, VDD3, VDD4 pin voltage = VDD) Parameter Supply voltage Input voltage Storage temperature Power dissipation Soldering temperature Soldering time Symbol VDD VI TSTG PD TSLD Rating – 0.3 to 4.0 VSS – 0.3 to VDD + 0.3 – 55 to 125 340 255 10 Unit V V ˚C mW ˚C sec tSLD Note. Refer to pin summary on the next page. Values also apply for supply inrush and switch-off. Electrical characteristics Recommended operating conditions (VSS1 = VSS2 = VSS3 = VSS4 = 0V, VDD1, VDD2, VDD3, VDD4 pin voltage = VDD) Parameter Supply voltage Operating temperature Symbol VDD TOPR Rating 2.7 to 3.6 – 10 to 70 Unit V ˚C DC characteristics Standard voltage:(VDD1 = VDD2 = VDD3 = VDD4 = 2.7 to 3.6V, VSS1 = VSS2 = VSS3 = VSS4 = 0V, Ta = – 10 to 70˚C) Parameter Current consumption Input voltage Pin VDD CLK (*2,3,5) (*4) Output voltage (*5) (*6) Input current Input leakage current (*4) (*3,5) (*1,2,5) (*1,2,4) H level L level H level L level H level L level H level L level H level L level IIH IIL ILH ILL Symbol IDD VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 IOH = – 1.0 mA IOL = 1.0 mA IOH = – 1.0 mA IOL = 1.0 mA VIN = VDD VIN = 0V VIN = VDD VIN = 0V 10 10 25 25 VDD – 0.4 0.4 80 80 1.0 1.0 VDD – 0.4 0.4 0.8VDD 0.2VDD VDD – 0.3 0.6 Condition Min (*A)SHPRF ON (*A)Through mode 0.8VDD 0.2VDD Rating Typ 4.5 1.5 Max 9.0 3.0 mA mA V V V V V V V V V V µA µA µA µA Unit (*A) VDD1 = VDD2 = VDD3 = VDD4 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD1 = VDD2 = VDD3 = VDD4 = 3 V. NIPPON PRECISION CIRCUITS-4 SM5906AF (*1) (*2) Pin function Pin name Pin function Pin name Clock input pin CLK Schmitt input pins YSRDATA, YLRCK, YSCK, YC2PO, YFLAG, NRESET, YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK Schmitt input pin with pull-up NTEST1 Schmitt pin with pull-down TEST2 I/O pins (Schmitt input with pull-up in input state) UC1, UC2, UC3, D0, D1, D2, D3 Outputs ZSCK, ZLRCK, ZSRDATA, ZC2PO, ZSENSE, NCAS, NWE, NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 (*3) (*4) (*5) (*6) Pin function Pin name Pin function Pin name Pin function Pin name Pin function Pin name NIPPON PRECISION CIRCUITS-5 SM5906AF AC characteristics Standard voltage: VDD1 = VDD2 = VDD3 = VDD4 = 2.7 to 3.6V, VSS1 = VSS2 =VSS3 =VSS4 =0V, Ta = –10 to 70 ˚C (*) Typical values are for fs = 44.1 kHz System clock (CLK pin) Parameter Clock pulsewidth (HIGH level) Clock pulsewidth (LOW level) Clock pulse cycle Symbol Condition System clock Min 26 26 384fs 58 Rating Typ 29.5 29.5 59 Max 50 50 100 ns ns ns Unit tCWH tCWL tCY System clock input CLK t CWH t CY t CWL 0.5VDD NIPPON PRECISION CIRCUITS-6 SM5906AF Serial input (YSRDATA, YLRCK, YSCK YC2PO pins) Parameter YSCK pulsewidth (HIGH level) YSCK pulsewidth (LOW level) YSCK pulse cycle YSRDATA setup time YSRDATA hold time Last YSCK rising edge to YLRCK edge YLRCK edge to first YSCK rising edge YLRCK pulse frequency See note below. YC2PO setup time YC2PO hold time fs fs µs µs Symbol Min Rating Typ Max ns ns ns ns ns ns ns 4fs Memory system ON (MSON=H) Memory system OFF (MSON=L) 75 75 150 50 50 50 50 0 Unit Condition tBCWH tBCWL tBCY tDS tDH tBL tLB tES tEH 1 1 Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode operation. t BCWH YSCK t DS YSRDATA t BL YLRCK t DH t BCY t BCWL 0.5 VDD 0.5 VDD t LB 0.5 VDD t LR/2 t LR/4 YLRCK t ES YC2PO t EH t LR/4 t LR/2 t ES t EH NIPPON PRECISION CIRCUITS-7 SM5906AF Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins) Parameter YMCLK LOW-level pulsewidth YMCLK HIGH-level pulsewidth YMDATA setup time YMDATA hold time YMLD LOW-level pulsewidth YMLD setup time YMLD hold time Rise time Fall time ZSENSE output delay Symbol Min Rating Typ Max ns ns ns ns ns ns ns 100 100 100 + 3tCY ns ns ns 30 + 2tCY 30 + 2tCY 30 + tCY 30 + tCY 30 + 2tCY 30 + tCY 30 + tCY Unit tMCWL tMCWH tMDS tMDH tMLWL tMLS tMLH tr tf tPZS Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz YMDATA t MDS YMCLK t MCWL YMLD t MLWL ZSENSE t PZS 0.5VDD t MLS t MCWH t MLH 0.5VDD t MDH 0.5VDD 0.5VDD tf YMCLK YMDATA YMLD 0.7 V DD 0.3 V DD tr 0.7 V DD 0.3 V DD 0.5VDD Reset input (NRESET pin) Parameter First HIGH-level after supply voltage rising edge NRESET pulsewidth Note. tCY is the system clock (CLK) input (384fs) cycle time. Symbol Min Rating Typ Max 0 64 Unit tHNRST tNRST tCY (Note) tCY (Note) tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz VDD NRESET t HNRST t NRST NIPPON PRECISION CIRCUITS-8 SM5906AF Serial output (ZSRDATA, ZLRCK, ZSCK ZC2PO pins) Parameter ZSCK pulsewidth ZSCK pulse cycle ZSRDATA, ZLRCK, ZC2PO output delay time Symbol Condition Min 15 pF load 15 pF load 15 pF load 15 pF load 0 0 Rating Typ 1/96fs 1/48fs 60 60 ns ns Max Unit tSCOW tSCOY tDHL tDLH ZSCK t SCOW t SCOW t SCOY ZSRDATA ZLRCK ZC2PO t DHL t DLH 0.5VDD 0.5VDD DRAM access timing (NRAS, NCAS, NWE, A0 to A10, D0 to D3) Parameter NRAS pulsewidth NRAS falling edge to NCAS falling edge NCAS pulsewidth NRAS falling edge to address NCAS falling edge to address NCAS falling edge to data write NCAS rising edge to data read Setup time Hold time Setup time Hold time Setup time Hold time Input setup Input hold Symbol Condition Min 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 40 0 15 pF load 15 pF load 4M DRAM CD-DA MODE VCD MODE SVC MODE CD-DA MODE VCD MODE SVC MODE Rating Typ 4 2 2 4 2 1 1 1 2 3 2 Max Unit NWE pulsewidth NWE falling edge to NCAS falling edge Refresh cycle (fs = 44.1 kHz playback) tRASL tRASH tRCD tCASH tCASL tRADS tRADH tCADS tCADH tCWDS tCWDH tCRDS tCRDH tWEL tWCS tCY(note) tCY tCY tCY tCY tCY tCY tCY tCY tCY tCY ns ns 5 3 3.0 2.6 1.3 5.9 5.2 2.6 tCY tCY ms ms ms ms ms ms tREF Memory system ON Read sequence operation (RDEN=H) ×1 16M DRAM ×1 Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz NIPPON PRECISION CIRCUITS-9 SM5906AF DRAM access timing t RASL 4 tCY NRAS t RCD 2tCY NCAS t CASL 2 tCY t CASH 4tCY t RASH 2 tCY ,,,,,,, A0 to A10 ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, D0 to D3 (WRITE) t RADS 1tCY t RADH 1tCY t CADS 1tCY t CADH 2tCY t CWDS 3tCY t CWDH 2tCY ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, D0 to D3 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (READ) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, t WCS 3tCY t WEL 5tCY t CRDS t CRDH NWE (WRITE) The NWE terminal output is fixed HIGH during read timing. NIPPON PRECISION CIRCUITS-10 SM5906AF Block diagram ZSRDATA ZLRCK ZC2PO ZSCK SM5906 Output Interface YBLKCK YFLAG Control Input 1 Input Interface YMDATA YMCLK YMLD ZSENSE Microcontroller Interface ESP Mode Through Mode UC1 to UC3 General Port Decoder Encoder YDMUTE NRESET NTEST1 TEST2 Control Input 2 DRAM Interface A0 to A10 NRAS NWE NIPPON PRECISION CIRCUITS-11 D0 to D3 NCAS CLK YSCK YSRDATA YC2PO YLRCK SM5906AF Functional description SM5906AF has two modes of operation; shockproof mode and through mode. The operating sequences are controlled using commands from a microcontroller. Microcontroller interface Command format Commands from the microcontroller are input using 3-wire serial interface inputs; data (YMDATA), bit clock (YMCLK) and load signal (YMLD). Write command format (Commands 80 to 85) DATA 8bit YMDATA D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 COMMAND 8bit B5 B4 B3 B2 B1 B0 In the case of a read command from the microcontroller, bit serial data is output (ZSENSE) synchronized to the bit clock input (YMCLK). YMCLK YMLD Read command format (Commands 90, 91, 93) COMMAND 8bit YMDATA B7 B6 B5 B4 B3 B2 B1 B0 YMCLK YMLD STATUS 8bit ZSENSE S7 S6 S5 S4 S3 S2 S1 S0 Read command format (Command 92 (memory residual read)) COMMAND 8bit YMDATA B7 B6 B5 B4 B3 B2 B1 B0 YMCLK YMLD RESIDUAL DATA 16bit ZSENSE S7 S6 S1 S0 M1 M2 M7 M8 (M4 to M8 are always 0.) NIPPON PRECISION CIRCUITS-12 SM5906AF Command table Write command summary MS command 80 B7 B6 B5 B4 Shock-proof memory system settings Bit D7 D6 D5 D4 D3 D2 D1 D0 ( Name MSWREN MSWACL MSRDEN MSRACL MSDCN2 MSDCN1 WAQV MSON Function Write sequence start/stop Write address reset Read sequence start/stop Read address reset MSDCN2=HIGH, MSDCN1=HIGH: 3-pair comparison start (ASH connect) MSDCN2=HIGH, MSDCN1=LOW: 2-pair comparison start (SH connect) MSDCN2=LOW, MSDCN1=HIGH: Direct-connect start (S connect) MSDCN2=LOW, MSDCN1=LOW: Connect operation stop Q data valid Memory system ON 80hex = 1000 0000 H operation Reset level Start Reset Start Reset Valid ON ) : VCD or SVC mode Extension I/O settings 81 B7 B6 B5 B4 Extension I/O port input/output settings Bit D7 D6 D5 D4 D3 D2 D1 D0 UC3OE UC2OE UC1OE Extension I/O port UC3 input/output setting Extension I/O port UC2 input/output setting Extension I/O port UC1 input/output setting Name Function 81hex = 1000 0001 H operation Reset level Output Output Output Extension I/O output data settings 82 Extension port HIGH/LOW output level A port setting is invalid if that port has already been defined as an input using the 81H command above. Bit D7 D6 D5 D4 D3 D2 D1 D0 UC3WD UC2WD UC1WD Extension I/O port UC3 output data setting Extension I/O port UC2 output data setting Extension I/O port UC1 output data setting Name Function B7 B6 B5 B4 82hex = 1000 0010 H operation Reset level H output H output H output NIPPON PRECISION CIRCUITS-13 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L L L L L L L L L L SM5906AF Function settings 83 B7 B6 B5 B4 83hex = 1000 0011 Bit D7 D6 D5 D4 D3 D2 D1 D0 Refer to "Forced mute", and "SYNC and Header data". Name NMSOFF MUTE REFRESH SCOFF Function Input signals connected directly to the outputs (changes instantaneously) Forced muting (changes instantaneously) DRAM refresh cycle performed during momentary pause to restore data Ignore sync cycle, and update comparison data when sync data is detected. H operation Reset level New through mode Mute ON REFRESH ON SYNCCNT OFF Option settings 85 B7 B6 B5 B4 85hex = 1000 0101 Bit D7 D6 D5 D4 YFLGS FLAG6 set conditions YFLGS = LOW, YFLAG = LOW : FLAG6 active YFLGS = HIGH, YFLAG = HIGH : FLAG6 active D3 D2 IBSEL2 IBSEL1 Bit clock select IBSEL2 = HIGH, IBSEL1 = HIGH : 32-bit mode IBSEL2 = LOW, IBSEL1 = HIGH : 16-bit mode All other cases: 24-bit mode D1 CDMODE2 – When MSON = HIGH CDMODE2 = LOW, CDMODE1 = LOW : CDDAMODE CDMODE2 = LOW, CDMODE1 = HIGH : VCDMODE CDMODE2 = HIGH, CDMODE1 = LOW : SVCMODE CDMODE2 = HIGH, CDMODE1 = HIGH : VCDMODE D0 CDMODE1 – When MSON = LOW CDMODE2 = LOW, CDMODE1 = LOW : CDDAMODE CDMODE2 = LOW, CDMODE1 = HIGH : VCDMODE CDMODE2 = HIGH, CDMODE1 = LOW : CDDAMODE CDMODE2 = HIGH, CDMODE1 = HIGH : VCDMODE L Mode select L L L L Name RAMSEL Function DRAM select (16M/4M) H operation Reset level 16M NIPPON PRECISION CIRCUITS-14 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L SM5906AF Read command summary Shock-proof memory status (1) 90 B7 B6 B5 B4 90hex = 1001 0000 Bit S7 S6 S5 S4 S3 S2 S1 S0 Name FLAG6 MSOVF BOVF SYNCER DCOMP MSWIH MSRIH SYNCWAR Function Signal processor IC jitter margin exceeded Write overflow (Read once only when RA exceeds WA) Input buffer memory overflow because sampling rate of input data is too fast Sync data not verified for ≥ 2 blocks Data compare-connect sequence operating Write sequence stop due to internal factors Read sequence stop due to internal factors Sync data not verified for 1 block Sync data not received Compare-connect sequence operating Writing stopped Reading stopped Sync data not received Refer to "Status flag operation summary". HIGH-level state Exceeded DRAM overflow Input buffer memory overflow Shock-proof memory status (2) 91 B7 B6 B5 B4 91hex = 1001 0001 Bit S7 S6 S5 S4 S3 S2 S1 S0 Refer to "Status flag operation summary". Name MSEMP OVFL WRSQ RDSQ Function Valid data empty state (Always HIGH when RA exceeds VWA) Write overflow state (Always HIGH when WA exceeds RA) WR sequence operating state RD sequence operating state HIGH-level state No valid data Memory full Writing Reading NIPPON PRECISION CIRCUITS-15 B3 B2 B1 B0 B3 B2 B1 B0 SM5906AF Shock-proof memory valid data residual 92 B7 B6 B5 B4 B3 B2 B1 B0 92hex = 1001 0010 Bit S7 S6 S5 S4 S3 S2 S1 S0 M1 M2 M3 M4 M5 M6 M7 M8 Name AM21 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12 AM11 AM10 AM09 AM08 AM07 AM06 Function Valid data accumulated VWA-RA (MSB) 8M bits 4M bits 2M bits 1M bits 512k bits 256k bits 128k bits 64k bits 32k bits 16k bits 8k bits 4k bits 2k bits 1k bits 512 bits 256 bits Output fixed LOW Output fixed LOW Output fixed LOW Output fixed LOW Output fixed LOW Note. The time conversion factor varies depending on the compression bit mode.(M = 1,048,576 K= 1,024) Residual time (sec) = Valid data residual (Mbits) × Time conversion value K where the Time conversion value K (sec/Mbit) ≈ 0.74 (CD-DA), 0.66 (VCD), 0.33 (SVC). Extension I/O inputs 93 Input data entering (or output data from) an extension port terminal is echoed to the microcontroller. (That is, the input data entering an I/O port configured as an input port using the 81H command, OR the output data from a pin configured as an output port using the 82H command.) Bit S7 S6 S5 S4 S3 S2 S1 S0 UC3RD UC2RD UC1RD Name Function B7 B6 B5 B4 93hex = 1001 0011 HIGH-level state NIPPON PRECISION CIRCUITS-16 B3 B2 B1 B0 SM5906AF Status flag operation summary Flag name FLAG6 Read method READ 90H bit 7 Set Meaning – Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a disturbance has exceeded the RAM jitter margin. – Set according to the YFLAG input and the operating state of YFLGS. – FLAG6 set conditions When YFLGS=0, YFLAG=LOW When YFLGS=1, YFLAG=HIGH Reset – By 90H status read – By 80H command when MSON=ON – After external reset – When MSWACL, MSRACL are issued MSOVF READ 90H bit 6 Set Reset Meaning – Indicates once only that a write to external DRAM has caused an overflow. (When reset by the 90H status read command, this flag is reset even if the overflow condition continues.) – When the write address (WA) exceeds the read address (RA) – By 90H status read – After external reset – When MSWACL, MSRACL are issued BOVF READ 90H bit 5 Meaning Set Reset – Indicates input data rate was too fast causing buffer overflow and loss of data – When data is input while the previous data is still being processed. – By 90H status read – After external reset – When MSWACL, MSRACL are issued SYNCER READ 90H bit 4 Meaning Set Reset – Indicates residual is not updated because sync data not verified for ≥ 2 blocks – When sync data is not verified for ≥ 2 blocks (C2PO error etc.) – When sync data is verified – After external reset – When MSWACL, MSRACL are issued DCOMP READ 90H bit 3 Reset Meaning Set – Indicates that a compare-connect sequence is operating – When a (3-pair or 2-pair) compare-connect start command is received (MSDCN2=1) – When a direct connect command is received (MSDCN2=0, MSDCN1=1) – When a (3-pair or 2-pair) comparison detects conforming data – When the connect has been performed after receiving a direct connect command – When a compare-connect stop command (MSDCN2=0, MSDCN1=0) is received – When a MSWREN=1 command is received (However, if a compare-connect command is received at the same time, WREN has priority.) – After external reset MSWIH READ 90H bit 2 Set Meaning – Indicates that the write sequence has stopped due to internal factors (not microcontroller commands) – When FLAG6 (above) is set – When BOVF (above) is set – When MSOVF (above) is set Reset – When conforming data is detected after receiving a compare-connect start command – When the connect has been performed after receiving a direct connect command – When a read address clear (MSRACL) or write address clear (MSWACL) command is received – After external reset NIPPON PRECISION CIRCUITS-17 SM5906AF Flag name MSRIH Read method READ 90H bit 1 Set Reset Meaning – Indicates that the read sequence has stopped due to internal factors (not microcontroller commands) – When the valid data residual becomes 0 – By 90H status read – When a read address clear (MSRACL) or write address clear (MSWACL) command is recieved – After external reset SYNCWAR READ 90H bit 0 Meaning Set Reset – Indicates residual is not updated because sync data not verified for 1 block – When sync data is not verified for 1 block (C2PO error etc.) – When sync data does not occur within a 2352-byte interval – By 90H status read – After external reset – When MSWACL, MSRACL are issued MSEMP READ 91H bit 7 Meaning Set Reset – Indicates that the valid data residual has become 0 – When the VWA (final valid data's next address) = RA (address from which the next read would take place) – Whenever the above does not apply – Indicates a write to external DRAM overflow state – When the write address (WA) exceeds the read address (RA). (Note: This flag is not set when WA=RA through an address initialize or reset operation.) – When the read address (RA) is advanced by the read sequence – When a read address clear (MSRACL) or write address clear (MSWACL) command is issued – After external reset OVFL READ 91H bit 6 Meaning Set Reset WRSQ READ 91H bit 5 Meaning Set – Indicates that the write sequence (input data entry, DRAM write) is operating – By the 80H command when MSWREN=1 – When conforming data is detected during compare-connect operation – When the connect has been performed after receiving a direct connect command Reset – When the FLAG6 flag=1 (above) – When the OVFL flag=1 (above) – When the BOVF flag=1 (above) – By the 80H command when MSWREN=0 – By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command) – By the 80H command when MSON=0 – After external reset Note. Reset conditions have priority over set conditions. However, simultaneous MSWREN = 1 and compare-connect operation has precedence over WRSQ. RDSQ READ 91H bit 4 Meaning Set Reset – Indicates that the read sequence (read from DRAM, data output) is operating – By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above) – Whenever the above does not apply NIPPON PRECISION CIRCUITS-18 SM5906AF Write command supplementary information 80H (MS command) – MSWREN When 1: Write sequence starts Invalid when MSON is not 1 within the same 80H command Invalid when FLAG6=1 Invalid when OVFL=1 If MSWREN = 1 command is issued during compare-connect operation, MSDCN1 and MSDCN2 must be set to 0. Write sequence starts from the point the command is issued as direct-connect (CD-DA) sequence. When 0: Write sequence stops – MSWACL When 1: Initializes the write address (WA) When 0: No operation – MSRDEN When 1: Read sequence starts Does not perform read sequence if MSON=1. If there is no valid data, read sequence temporarily stops. But, because the MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. When 0: Read sequence stops – MSRACL When 1: Initializes the read address (RA) When 0: No operation – MSDCN2, MSDCN1 Refer to compare-connect sequence After MSWACL and MSRACL, set MSWREN = 1 to start the write sequence. If the start occurs in direct-connect mode, a noise may be generated. CDDAMODE When 1 and 1: 3-pair compare-connect sequence starts When 1 and 0: 2-pair compare-connect sequence starts When 0 and 1: Direct connect sequence starts When 0 and 0: Compare-connect sequence stops. No operation if a compare-connect sequence is not operating. VCD, SVCMODE When 1 and 1: Video CD compare-connect sequence, checking C2PO, starts (ASH connect) When 1 and 0: Video CD compare-connect sequence, ignoring C2PO, starts (SH connect) When 0 and 1: Connect sequence, checking sync data only, starts (S connect) When 0 and 0: Compare-connect sequence stops. No operation if a compare-connect sequence is not operating. – WAQV When 1: If a write address (WA) is verified as a valid at the preceding YBLKCK falling edge timing, it becomes a valid write address (VWA). When 0: No operation – MSON When 1: Memory system turns ON and shockproof operation starts When 0: Memory system turns OFF and throughmode playback starts. Even in through mode, the CDDAMODE and VCDMODE settings may become active. VCDMODE settings should be set if using C2PO. (see 85H command) 81H (Extension I/O port settings) 82H (Extension I/O port output data settings) NIPPON PRECISION CIRCUITS-19 SM5906AF 83H ( NMSOFF, MUTE, REFRESH, SCOFF settings) – NMSOFF (new through mode) When 1: Input signals YSCK, YSRDATA, YLRCK, YC2PO are connected directly to outputs ZSCK, ZSRDATA, ZLRCK, ZC2PO as is. When 0: No operation – MUTE (forced muting) When 1: Outputs are instantaneously muted to 0. (note 1) Same effect as taking the YDMUTE pin HIGH. When 0: No muting (note 1) (note1) Effective at the start of left-channel output data. – MUTE, YDMUTE relationship When all mute inputs are 0, mute is released. – REFRESH (refresh mode) When 1: During momentary pause in shock-proof mode operation, DRAM is accessed in a refresh cycle to maintain data written to DRAM. When 0: No operation – SCOFF (SYNC counter off) A sync counter is used to count 588 data samples per sync cycle. The counter starts when sync data is detected, and valid data is updated after each cycle if sync data is verified. If sync data is not detected, the SYNCWAR and SYNCER flags are set. When 1: The counter is off (sync cycle is not involved) and valid data is updated when the sync data is detected and verified. When 0: Counts the sync cycles, and updates valid data. 85H (option settings) – RAMSEL When 0 : 4M DRAMs (1M×4 bits) When 1 : 16M DRAMs (4M×4 bits) – YFLGS When 0 : Sets FLAG6 when YFLAG=0 When 1 : Sets FLAG6 when YFLAG=1 – IBSEL2, IBSEL1 When 0 and 1 : Input bit clock(YSCK)=16-bit mode When 1 and 1 : Input bit clock(YSCK)=32-bit mode In all other cases: Input bit clock(YSCK)=24-bit mode Changing mode without initializing during operation is possible. – CDMODE2, CDMODE1 When 0 and 0 : CDDA mode YSRDATA only is stored as data in DRAM, with output data on ZSRDATA. When 1 and 0 : SVC mode YSRDATA and YC2PO are stored as data in DRAM, with output data at double speed if MSON = 1 only (CD-DA mode if MSON = 0). In all other cases: VCD mode YSRDATA and YC2PO are stored as data in DRAM, with output data on ZSRDATA and ZC2PO. Changing mode without initializing during operation is possible. NIPPON PRECISION CIRCUITS-20 SM5906AF Shock-proof operation overview Shock-proof mode is the mode that realizes shockproof operation using external DRAM. Shock-proof mode is invoked by setting MSON=H in microcontroller command 80H. This mode comprises the following 3 sequences. – Write sequence 1. Input data from a signal processor IC is read in. 2. Data read in is written to external DRAM in the sequence left-channel, (C2PO), and right-channel. (C2PO) is omitted in CDDA mode. – Read sequence 1. Data written to external DRAM is read out at fs rate (rate 2fs in SVC mode). 2. Data is output in sync with the 24-bit bit clock (ZSCK). – Compare-connect sequence 1. Encoding immediately stops when either external buffer RAM overflows or when a CD read error occurs due to shock vibrations. 2. Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. 3. Compares data re-read from the CD with the processed final valid data stored in RAM (confirms its correctness). 4. As soon as the comparison detects conforming data, compare-connect sequence stops and encode sequence re-starts, connecting the data directly behind previous valid data. RAM addresses The SM5906AF uses 4M or 16M DRAMs as external buffers. Three kinds of addresses are used for external RAM control. WA (write address) RA (read address) VWA (valid write address) Among these, VWA is the write address for conforming data whose validity has been confirmed. Determination of the correctness of data read from the CD is delayed relative to the write processing, so VWA is always delayed relative to WA. The region available for valid data is the area between VWA-RA. WA RA VWA Valid data area Fig 1. RAM addresses NIPPON PRECISION CIRCUITS-21 SM5906AF VWA (valid write address) The VWA is determined according to the YBLKCK pin and WAQV command. Refer to the timing chart below. 1.YBLKCK is a 75 Hz clock(HIGH for 136 µs) when used for normal read mode and it is a 150 Hz clock when used for double-speed read mode, synchronized to the CD format block end timing. On the falling edge of this clock, stored compareconnect write address WA1 is promoted to WA2 and stored.(see note 1). 2.The microcontroller checks the subcode and, if confirmed to be correct, generates a WAQV command (80H). 3.When the WAQV command is received, the previously latched WA2 is stored as the VWA. (Note 1) WA1, in VCD and SVC modes, is the DRAM write address of the last sync data input before the YBLKCK falling edge. In CDDA mode, update occurs in the same manner so that WA1 is updated every 588 data samples. 13.3ms YBLKCK Microcontroller data set Refer to Microcontroller interface VWA latch set WAQV set VWA VWA(x) VWA(x + 1) Values shown are for rate fs. The values are 1/2 those shown at rate 2fs. Fig 2. YBLKCK and VWA relationship YFLAG, FLAG6 Correct data demodulation becomes impossible for the CD signal processor IC when a disturbance exceeding the RAM jitter margin occurs. The YFLAG signal input pin is used to indicate when such a condition has occurred. The IC checks the YFLAG input and stops the write sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depending on the YFLGS flag (85H command). (see table1) 85H command YFLGS 0 1 0 1 FLAG6 set conditions When YFLAG = LOW When YFLAG = HIGH FLAG6 reset conditions – By status read (90H command) – When MSON = LOW or after system reset Table 1. YFLAG signal check method NIPPON PRECISION CIRCUITS-22 SM5906AF Compare-connect sequence In compare-connect mode, there are 6 connect modes: CDDA mode 3-pair compare-connect, 2pair compare-connect and direct connect, plus VCD/SVC mode ASH connect (SYNC, HEADER), SH data connect (no C2PO check), and S connect (SYNC) modes. – CD-DA mode In 3-pair compare-connect mode, the final 6 valid data (3 pairs of left- and right-channel) and the most recently input data are compared until three continuous data pairs all conform. At this point, the write sequence is re-started and data is written to VWA. In 2-pair compare-connect mode, comparison occurs just as for 3-pair comparison except that only 2 pairs from the three compared need to conform with the valid data. At this point, the write sequence is re-started and data is written to VWA. In direct-connect mode, comparison is not performed at all, and write sequence starts and data is written to the VWA. This mode is for systems that cannot perform compare-connect operation. – VCD, SVC mode In ASH connect mode, the final 12 bytes of sync data in the valid data, 4 bytes of header data and the corresponding C2PO value are compared with new input data. If the data matches, the write sequence starts from the next data and connect occurs after the header data. In SH connect mode, the compare occurs in the same manner as in ASH connect mode except the C2PO is not checked, even if it contains an error. If the data matches, the write sequence starts from the next data and connect occurs after the header data. In S connect mode, the new data is compared with the sync data. If the data matches, the write sequence starts from the next data and connect occurs after the sync data. S connect mode can be used when other connections are not successful. – Compare-connect preparation time 1. Comparison data preparation time Internally, when the compare-connect start command is issued, a sequence starts to restore the data for comparison. The time required for this preparation after receiving the command is approximately 1 × (1/fs). (approximately 23 µs when fs = 44.1 kHz) 2. After the above preparation is finished, data is input beginning from the left-channel data and comparison starts. 3. The same sequence takes place in direct-connect mode also. However, at the point when 3 words have been input, all data is directly connected as if comparison and conformance had taken place. – Compare-connect sequence stop If a compare-connect stop command (80H with MSDCN1= 1, MSDCN2= 0) is input from the microcontroller, compare-connect sequence stops. If compare-connect sequence was not operating, the compare-connect stop command performs no operation. However, make sure that the other bit settings within the same 80H command are valid. NIPPON PRECISION CIRCUITS-23 SM5906AF Write sequence temporary stop – When RAM becomes full, MSWREN is set LOW using the 80H command and write sequence stops. (For details of the stop conditions, refer to the description of the WASQ flag.) – Then, if MSWREN is set HIGH without issuing a compare-connect start command, the write sequence re-starts. At this time, new input data is written not to VWA, but to WA. In this way, the data already written to the region between VWA and WA is not lost. – But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued. After comparison and conformance are detected, no operation is performed because the write sequence has already been started. However, make sure that the other bit settings within the same 80H command are valid. DRAM refresh – DRAM initialization refresh An 8-cycle RAS-only refresh is carried out for DRAM initialization under the following conditions. When MSON changes from 0 to 1 using command 80H. When from MSON=1, MSRDEN=0 and MSWREN=0 states only MSWREN changes to 1. In this case, write sequence immediately starts and initial data is written (at 2fs rate input) after a delay of 50µs. – Refresh during Shock-proof mode operation In this IC, a data access operation to any address also serves as a data refresh. A data access to DRAM can occur in an write sequence write operation or in a read sequence read operation. Write sequence write operation stops during a connect operation whereas a read sequence read operation always continues while data is output to the D/A. The refresh rate for each DRAM during read sequence is shown in the table below. The read sequence, set by MSON=1 and MSRDEN=1, operates when valid data is in DRAM (when MSEMP=0). – When MSON=0, DRAM is not refreshed because no data is being accessed. Although MSON=1, DRAM is not refreshed if ENCOD=0 and DECOD=0 (both encode and decode sequence are stopped). DRAMs used Data compression mode CDDA mode VCD mode SVC mode 4M (1M×4 bits) 2.91 ms 2.58 ms 1.29 ms 16M(4M×4 bits) 5.81 ms 5.17 ms 2.59 ms Table 2. Read sequence refresh rate NIPPON PRECISION CIRCUITS-24 SM5906AF – REFRESH flag (85H) refresh In shock-proof mode, if operation momentarily stops (WRSQ and RDSQ stop), data in DRAM would be lost. In order to be able to use data in DRAM after such a stop, a refresh mode is provided that can refresh data, even during a momentary pause in operation. 1. In shock-proof mode, with WASQ and RASQ in an operating state, only WASQ stops if a stop command is issued (if WASQ is already in the stop state, then the stop command is not required). 2. Set the REFRESH flag HIGH using the 83H command. The outputs are then muted, and read operation also stops. The last read address RAL is stored. 3. At this point, RDSQ is operating and DRAM is being accessed without updating and DRAM data. The operation is similar to momentary stop operation because the outputs are muted. DRAM is repeatedly accessed using read addresses from RAL to VWA. 4. Set the REFRESH flat LOW using the 83H command to release the momentary stop command. At this point, the read address is restored to RAL and data read out starts from this address. Simultaneously, the output muting is also released. 5. When WRSQ starts, send the compare command, and writing starts from after the VWA. If this operation occurs when MSWREN is HIGH, the WA, VWA, and RA address relationship may be lost, resulting in incorrect operation. Through-mode operation If MSON is set LOW (80H command), an operating mode that does not perform shock-proof functions becomes active. In this case, input data is passed as-is (except Force mute operation) to the output. External DRAM is not accessed. Also, in through mode, the bit clock and CDDA and VCD mode (85H command) settings become valid. Note that SVC mode cannot be used in through mode, reverting to CDDA mode instead. – In this case, input data needs to be at a rate fs and the input word clock must be synchronized to the CLK input (384fs). However, short-range jitter can be tolerated (jitter-free system). – Jitter-free system timing starts from the first YLRCK rising edge after either (A) a reset (NRESET= 0) release by taking the reset input from LOW to HIGH or (B) by taking MSON from HIGH to LOW. Accordingly, to provide for the largest possible jitter margin, it is necessary that the YLRCK clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs (80 clock cycles). This jitter margin is the allowable difference between the system clock (CLK) divided by 384 (fs rate clock) and the YLRCK input clock. If the timing difference exceeds the jitter margin, irregular operation like data being output twice or, conversely, incomplete data output may occur. In the worst case, a click noise may also be generated. When switching from shock-proof mode to through mode, an output noise may be generated, and it is therefore recommended to use the YDMUTE setting to mute ZSRDATA until just before data output. – When NMSOFF = 1 (83H command), the YSCK, YSRDATA, YLRCK, YC2PO inputs are connected directly to the ZSCK, ZSRDATA, ZLRCK, ZC2PO outputs, respectively. When the connection is switched, the input clock and data pins are switched instantaneously to the output clock and data pins, so the outputs should be muted just prior to switching. NIPPON PRECISION CIRCUITS-25 SM5906AF Force mute Serial output data is muted by setting the YDMUTE pin input HIGH or by setting the MUTE flag to 1. Mute starts and finishes on the leading left-channel bit. When MSON is HIGH and valid data is empty (MSEMP=H), the output is automatically forced into the mute state. SYNC and Header data Note that video CD sync and header data formats are appended. Lch MSByte FF FF FF Minutes Successive data (1 cycle = 2352 bytes) LSByte 00 FF FF Seconds Successive data MSByte FF FF 00 Frames Successive data Rch LSByte FF FF FF Mode Successive data Table 3. NIPPON PRECISION CIRCUITS-26 SM5906AF Timing charts Input timing (YSCK, YSRDATA, YLRCK, YC2PO) 16-bit mode 16 16 YSCK Lch16 MSB LSB MSB LSB Rch16 MSB LSB YSRDATA YLRCK YC2PO 24-bit mode Upper Lch Lower Lch Upper Rch Lower Rch 24 24 YSCK Lch16 MSB MSB LSB Rch16 LSB YSRDATA YLRCK YC2PO 32-bit mode Upper Lch Lower Lch Upper Lch Lower Lch 32 32 YSCK Lch16 MSB MSB LSB Rch16 LSB YSRDATA YLRCK YC2PO Upper Lch Lower Rch Upper Lch Lower Rch Output timing (ZSCK, ZSRDATA, ZLRCK, ZC2PO) 1 9 24 33 48 ZSCK Lch MSB MSB LSB Rch LSB ZSRDATA ZLRCK 13 1/fs or 1/2fs Lower Rch Upper Lch 37 Lower Rch ZC2PO Upper Lch NIPPON PRECISION CIRCUITS-27 SM5906AF DRAM write timing (NRAS, NCAS, NWE, A0 to A10, D0 to D3) t RASL NRAS t RDC NCAS t RADS A0 to A10 t RADH t CADS t CADH t CASL t CASH t RASH ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t CWDS t CWDH ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, D0 to D3 (WRITE) t WEL NWE DRAM read timing (NRAS, NCAS, NWE, A0 to A10, D0 to D3) t RASL NRAS t RCD NCAS t CASL t CASH t RASH A0 to A10 ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t RADS t RADH t CADS t CADH D0 to D3 (READ) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, t OEL t CRDS t CRDH ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, NWE NIPPON PRECISION CIRCUITS-28 SM5906AF Connection example SM5906 Microcontroller YMDATA YMCLK YMLD ZSENSE UC1 to UC3 DRAM NRAS NWE A0 to A10 D0 to D3 NCAS RAS WE A0 to A10 D0 to D3 CAS OE YBLKCK YFLAG DSP YLRCK YSCK YSRDATA YC2PO ZSCK ZLRCK ZSRDATA ZC2PO Decoder CLK NRESET YDMUTE note1 - When 2 DRAMs are used, the DRAM OE pins should be tied LOW. NIPPON PRECISION CIRCUITS-29 SM5906AF NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, FUKUZUMI 2 CHOME, KOTO-KU TOKYO,135-8430, JAPAN Telephon: +81-3-3642-6661 Facsimile: +81-3-3642-6698 NIPPON PRECISION CIRCUITS INC. NC9901AE 1999.7 NIPPON PRECISION CIRCUITS-30