SM5921A 8-channel Lip Sync Delay
OVERVIEW
The SM5921A is an SDRAM controller LSI for audio applications. It stores 64-fs slot 3-wire serial format audio data input at sampling frequency fs in SDRAM, and can access data at an arbitrary address to add a delay to each channel data. It also has a direct mute function to mute the audio data.
FEATURES
Functions
I
PINOUT
(Top view)
CASN RASN WEN CSN VDD
33
I I
I I I
I
I
I
System clock input 64fs (fs = 32 to 192kHz) bit clock Sampling frequency: fs = 32 to 192kHz support Data input/output 3-wire serial, 8-channel PCM 64 clock/slot, word clock polarity inversion Direct mute function MCU interface: 3-wire serial Delay settings: sum of intrinsic delay and individual delay • Intrinsic delay (common to all channels, default = 0 samples, 16-sample units) • Individual delay (independent for each channel, default = 0 samples, 1-sample units) Maximum delay values 1365.3ms @ fs = 48kHz 682.7ms @ fs = 96kHz 341.3ms @ fs = 192kHz Address shift function: ×1, ×2, ×4 support Delay time can be multiplied between ×1, ×2, or ×4 times without changing the delay set value. SDRAM interface: 16M/64M/128M (×16 devices supported) Package: 64-pin QFP
DQ4
DQ5
DQ6
DQ7
VSS
A10
BA
A0
A1
A2
35
48
47
46
45
44
43
42
41
40
39
38
37
36
34
A3
VDD DQ3 DQ2 DQ1 DQ0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WPOLN OEN VSS
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS DQM CLKO CKE A9 A8 A7 A6 A5 A4 DOD DOC DOB DOA TEST VDD
TEST3 13
DMUTEN 14
RSTN 15
PACKAGE DIMENSIONS
(Unit: mm) Weight: 0.35g
12 ± 0.4 10 ± 0.1
+ 0. 0.125 − 0 075 .025
Structure
I
Silicon-gate CMOS
Applications
10 ± 0.1
I
Audio delay for multi-channel PCM signals
12 ± 0.4
TEST2 12
BCKI
SCLK
WCKI
VDD
XCS
ORDERING INFORMATION
Device SM5921AF Package 64-pin QFP
1.4 ± 0.1 0.08 S + 0.09 0.18 − 0.05 0.1
0 to 10
S
Note. Dimensions without tolerance are reference values.
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1.7 MAX
0.5
0.5 ± 0.2
VSS 16
SI 10
DIC
DID
SIO 11
1
2
3
4
5
6
7
8
DIA
DIB
9
SM5921A
BLOCK DIAGRAM
WPOLN WCKI BCKI DIA DIB DIC DID
Input data interface
TEST TEST2 Sequencer block TEST3 RSTN Arithmetic operation block Address controller CKE CLKO DQM A0 to A10 BA DQ0 to DQ15 CSN SDRAM interface XCS SCLK SI SIO Output data interface OEN DMUTEN MCU interface CASN RASN WEN
DOA
DOB
DOC
DOD
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name VDD WCKI BCKI DIA DIB DIC DID XCS SCLK SI SIO TEST2 TEST3 DMUTEN RSTN VSS VDD TEST DOA DOB DOC DOD I/O*1 – I I I I I I I I I Ot Id Id Ip Ip – – Id Ot Ot Ot Ot Supply pin Word clock input Bit clock input (64fs) Serial data input A Serial data input B Serial data input C Serial data input D MCU latch enable input MCU clock input MCU data input MCU data output Test input pin Test input pin Direct mute control Reset input pin Ground pin Supply pin Test input pin Serial data output A Serial data output B Serial data output C Serial data output D SEIKO NPC CORPORATION —2 Test Test Test Mute Reset Function Setting HIGH LOW
SM5921A
Setting HIGH LOW
Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Name A4 A5 A6 A7 A8 A9 CKE CLKO DQM VSS VDD A3 A2 A1 A0 A10 BA CSN RASN CASN WEN DQ7 DQ6 DQ5 DQ4 VSS VDD DQ3 DQ2 DQ1 DQ0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WPOLEN OEN VSS
I/O*1 O O O O O O O O O – – O O O O O O O O O O I/O I/O I/O I/O – – I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Ip Id – Address output A4 Address output A5 Address output A6 Address output A7 Address output A8 Address output A9 SDRAM clock enable output SDRAM clock output (64fs) DQM output Ground pin Supply pin Address output A3 Address output A2 Address output A1 Address output A0 Address output A10 Bank address output BA CS output RAS output CAS output WE output Data input/output DQ7 Data input/output DQ6 Data input/output DQ5 Data input/output DQ4 Ground pin Supply pin Data input/output DQ3 Data input/output DQ2 Data input/output DQ1 Data input/output DQ0 Data input/output DQ15 Data input/output DQ14 Data input/output DQ13 Data input/output DQ12 Data input/output DQ11 Data input/output DQ10 Data input/output DQ9 Data input/output DQ8 Word clock polarity control Data output enable control Ground pin
Function
Inverted Hi-Z Output
*1. I: Input, I/O: Input/Output, O: Output, Ip: Input with pull-up resistor, Id: Input with pull-down resistor, Ot: Three-state output
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SM5921A
ABSOLUTE MAXIMUM RATINGS
VSS = 0V, VDD pin voltage = VDD
Parameter Supply voltage Input voltage Output voltage Storage temperature Power dissipation Symbol VDD VI VO TSTG PW Conditions Rating −0.3 to 4.6 −0.3 to 5.5 −0.3 to VDD + 0.3 −55 to 125 120 Unit V V V °C mW
Note. Supply ratings apply both when switching power ON or OFF.
RECOMMENDED OPERATING CONDITIONS
VSS = 0V, VDD pin voltage = VDD
Rating Parameter Supply voltage Operating temperature Symbol VDD TOPR Conditions min 3.0 −40 typ 3.3 25 max 3.6 85 V °C Unit
ELECTRICAL CHARACTERISTICS
DC Characteristics
VSS = 0V, VDD = 3.0 to 3.6V, Ta = −40 to 85°C
Rating Parameter Current consumption Input voltage Pins VDD (*1) (*2) (*3) (*5) (*4) (*5) Symbol IDD VIH VIL VOH VOL Input leakage current (*1) (*5) ILH ILL (*2) Input current (*3) IIH1 IIL1 IIH2 IIL2 IOH = −2.0mA IOL = 2.0mA VIN = VDD VIN = 0V VIN = VDD VIN = 0V VIN = VDD VIN = 0V (*A) 2.0 0 VDD − 0.4 0 −1.0 −1.0 −1.0 −90.0 12.5 −1.0 −33.0 33.0 Conditions min typ 18 max 30 VDD 0.8 VDD 0.4 1.0 µA 1.0 1.0 −12.5 90.0 1.0 µA V mA V Unit
Output voltage
(*A) All output pins no load, system clock frequency fBCKI = 12.288MHz, input sampling frequency fs = 192kHz, supply voltage VDD = 3.6V Note. See “Pin Classification” below for description of pins.
Pin classification
Symbol (*1) (*2) (*3) (*4) (*5) Pin type Inputs Inputs Inputs Outputs Input/Outputs Pin name WCKI, BCKI, DIA, DIB, DIC, DID, XCS, SCLK, SI DMUTEN, WPOLN, RSTN OEN, TEST, TEST2, TEST3 DOA, DOB, DOC, DOD, RASN, CASN, CSN, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, BA, WEN, CLKO, CKE, DQM, SIO DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15
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SM5921A
AC Characteristics
Serial inputs (WCKI, BCKI, DI* pins)
Rating Parameter WCKI cycle time BCKI pulse cycle time BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth DI* setup time DI* hold time Last BCKI rising edge → WCKI edge WCKI edge → first BCKI rising edge Symbol tWCCY tBICY tBICWH tBICWL tDIS tDIH tBWI tWBI Conditions min 5.2 81.25 32.5 32.5 20.0 20.0 32.5 32.5 typ 20.8 325.5 130.2 130.2 max 32 500 320 320 µs ns ns ns ns ns ns ns Unit
VIH
WCKI
0.5VDD
tBWI
BCKI
tWBI
VIL VIH
0.5VDD
tBICWH tBICY
tBICWL
VIL
VIH
DI*
0.5VDD
tDIS
tDIH
VIL
Note. DI*: DIA, DIB, DIC, DID pins
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SM5921A Serial outputs (DO* pins)
Rating Parameter BCKI to output delay DI* to output delay Word boundary to enable time Word boundary to disable time Symbol tBDL tDDL tODL tOEZ Conditions min CL = 15pF Data-through (THROU = 1), CL = 15pF OEN = H → L, CL = 15pF OEN = L → H, CL = 15pF 0 0 0 0 typ max 20 20 30 30 ns ns ns ns Unit
VIH
BCKI
0.5VDD
VIL
VIH
DI*
0.5VDD
tDDL
VIL
VOH
DO*
0.5VDD
tBDL
VOL
VIH
WCKI
0.5VDD
VIL
VOH
DO*
0.5VDD
tODL
tOEZ
VOL
Note. DI*: DIA, DIB, DIC, DID pins DO*: DOA, DOB, DOC, DOD pins
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SM5921A SDRAM interface (CLKO, RASN, CASN, WEN, CSN, A0 to A10, DQ0 to DQ15 pins)
Rating Parameter CLKO pulse cycle time CLKO HIGH-level pulsewidth CLKO LOW-level pulsewidth RASN pulsewidth Symbol tCLKCY tCLKOH tCLKOL tRASNH tRASNL CASN pulsewidth tCASNH tCASNL WEN pulsewidth Setup time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Hold time Setup time Hold time tWENH tWENL CLKO ↑ – CSN CLKO ↑ – RASN CLKO ↑ – CASN CLKO ↑ – WEN CLKO ↑ – A0 to A10 CLKO ↑ – DQ0 to DQ15 Refresh command interval CLKO propagation delay tCSNS tCSNH tRASNS tRASNHO tCASNS tCASNHO tWENS tWENHO tADS tADH tDQS tDQH tREF tDLY Conditions min CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF CL = 15pF 0 1 1 1 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 3 15 typ 1 1/2 1/2 max tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY tBICY times/fs ns Unit
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SM5921A
VOH
CLKO
1.5V
tCLKOH tCLKOL tCLKCY
CSN
VOL
VOH 1.5V
tDLY
tDLY
VOL
VOH
RASN
1.5V
tRASNL
tDLY
tRASNH
VOL
VOH
CASN
1.5V
tCASNH
tDLY
tCASNL
VOL
VOH
WEN
1.5V
tWENH
tDLY
tWENL
VOL
VOH
A0 to A10
1.5V
tDLY
VOL VOH
DQ0 to DQ15
1.5V
tDLY
VOL
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SM5921A MCU interface input/outputs (SCLK, SI, XCS, SIO pins)
Rating Parameter XCS HIGH-level pulsewidth XCS LOW-level pulsewidth SCLK setup time SCLK hold time SCLK pulse cycle time SCLK HIGH-level pulsewidth SCLK LOW-level pulsewidth SI setup time SI hold time SCLK to output propagation delay Symbol tXCSWH tXCSWL tXCSS tXCSH tSCLKCY tSCLKH tSCLKL tSIS tSIH tDSIO CL = 15pF Conditions min 30 + tBICY 30 + 17tBICY 30 + tBICY/2 30 + tBICY/2 60 + tBICY 30 + tBICY 30 + tBICY 30 + tBICY/2 30 + tBICY/2 0 20 typ max ns ns ns ns ns ns ns ns ns ns Unit
tXCSWL
XCS
tXCSWH
VIH
0.5VDD
VIL
tXCSS
tXCSH
VIH
SCLK
0.5VDD
tSCLKH tSCLKL tSCLKCY
SI
VIL
VIH
0.5VDD
tSIS
tSIH
VIL
VIH
SIO
0.5VDD
tDSIO
VIL
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SM5921A
FUNCTIONAL DESCRIPTION
Delay Settings
The SM5921A sets the delay value set using an MCU interface and adds that delay to the input data. The total delay value for each channel data is given by the following equation. ( nSample-system + ( nSample-intrinsic + nSample-individual ) × nMp ) t Delay ( sec ) = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------fs nSample-system: nSample-intrinsic: nSample-individual: nMp: fs: Number of system delay samples (fixed 2 samples) Number of intrinsic delay samples (16-sample units) Number of individual delay samples (1-sample units) Address shift coefficient Sampling frequency
Note that even when the intrinsic delay and individual delay are both set to 0 samples, a 2-sample delay is applied. Address shift coefficient The address shift coefficient is determined by the settings of the MP0N and MP1N flags. These enable the time delay to be multiplied by ×1, ×2, or ×4 without changing the delay value setting. For example, if the sampling frequency fs is switched from 48kHz to 192kHz and the address shift is set to ×4, then the same delay time is added.
MP0N LOW LOW HIGH HIGH
I I
MP1N LOW HIGH LOW HIGH
nMp 1 2 4 1
Data setting values cannot exceed the upper limit. Calculation examples • If fs = 48kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 1, then the delay value is: tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec] = (2 + (8192 + 2048) × 1) ÷ 48000 = 213.3ms • If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 1, then the delay value is: tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec] = (2 + (8192 + 2048) × 1) ÷ 192000 = 53.3ms • If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 2, then the delay value is: tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec] = (2 + (8192 + 2048) × 2) ÷ 192000 = 106.6ms • If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 4, then the delay value is: tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec] = (2 + (8192 + 2048) × 4) ÷ 192000 = 213.3ms
From the examples, it can be seen that switching the sampling frequency from 48kHz to 192kHz and changing nMp from 1 to 4 results in an identical time delay. Note, however, that the memory size physical limit cannot be exceeded. So, for example, the physical limit is reached with a sum (nSample-intrinsic + nSample-individual) of 16384 samples when nMp = 4, or the equivalent of 65535 samples at nMp = 1.
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SM5921A Intrinsic delay The intrinsic delay is the common delay applied to each channel group, and is used to add the same delay value to the channel group data. The default value is 0 samples. The intrinsic delay is set by the values of REG 0/H (DIA/DOA and DIB/DOB groups) and REG 1/H (DIC/DOC and DID/DOD groups), with the values measured in 16-sample units (333.2µs @ fs = 48kHz). When the TRACKT flag in REG A/H is set to HIGH, the same delay value is added to all the channel groups (DIA/DOA, DIB/DOB, DIC/DOC, DID/DOD). See the “MCU Interface” section. Individual delay The individual delay is the delay applied to each channel individually, and is used to add a delay offset for each channel data. The default value is 0 samples. The individual delay is set by the values of REG 2/H, REG 3/H, REG 4/H, REG 5/H, REG 6/H, REG 7/H, REG 8/H, and REG 9/H, with the values measured in 1-sample units (20.8µs @ fs = 48kHz). When the TRACKD flag in REG A/H is set to HIGH, the delay value set in REG 2/H (DIA/DOA left-channel) is also applied to the DIA/DOA right-channel, DIB/DOB left-channel, and DIB/DOB right-channel data. Similarly, the delay value set in REG 6/H (DIC/DOC left-channel) is also applied to the DIC/DOC right-channel, DID/DOD left-channel, and DID/DOD right-channel data. The minimum parameter settings required to apply the same delay to all channels is to set delay values in REG 0/H, REG 2/H, REG 6/H, and to set the TRACKT and TRACKD flags to HIGH. The relationship between the intrinsic delay, individual delay, and the registers is shown in the following table.
Channel DIA/DOA left-channel DIA/DOA right-channel REG 0/H DIB/DOB left-channel DIB/DOB right-channel DIC/DOC left-channel DIC/DOC right-channel REG 1/H DID/DOD left-channel DID/DOD right-channel REG 8/H REG 9/H REG 4/H REG 5/H REG 6/H REG 7/H Intrinsic delay Individual delay REG 2/H REG 3/H
Delay time examples The total delay value is defined by the equation described earlier. The following table shows some examples.
Sampling frequency (fs) nSample-intrinsic + nSample-individual setting 32kHz 0*1 1000 10000 20000 36863 65535 62.5 31.3 312.5 625 1152 2048 44.1kHz 45.4 22.7 226.8 453.5 835.9 1486.1 48kHz 41.7 20.8 208.3 416.7 768 1365.3 96kHz 20.8 10.4 104.2 208.3 384 682.7 192kHz 10.4 5.2 52.1 104.2 192 341.3 µs ms ms ms ms ms Unit
*1. Even when the set value is 0 samples, a fixed 2-sample system delay is applied.
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SM5921A Delay set value upper limit The upper limit for the delay set value input {(nSample-intrinsic + nSample-individual) × nMp} for each channel is 65535 samples. If a delay value input exceeding 65536 is incorrectly set, an internal limiter treats the channel delay set value as 65535 samples. The following table shows some delay value setting examples.
Delay set value input nMp 1 1 2 2 4 4 REG 0/H FFF/H FFF/H 7FF/H 7FF/H 3FF/H 3FF/H REG 2/H 00F/H 010/H 00F/H 010/H 00F/H 010/H nSample-intrinsic + nSample-individual × nMp [samples] (65520 + 15) × 1 = 65535 (65520 + 16) × 1 = 65536 (32752 + 15) × 2 = 65534 (32752 + 16) × 2 = 65536 (16368 + 15) × 4 = 65532 (16368 + 16) × 4 = 65536 Limiter delay set value [samples] 65535 65535 65534 65535 65532 65535
System Reset (RSTN, WPOLN pins, INIT flag)
The SM5921A must be reset when power is applied. The system is reset by applying a LOW-level pulse on the RSTN pin. When the system is reset, all registers are cleared and the sequencer is also reset. The system reset is released by a LOW-to-HIGH transition on RSTN when the supply voltage has stabilized and the WCKI and BCKI clocks have stabilized. If the WCKI or BCKI clocks stop during operation, the system should be reset again after the clocks have stabilized. After the system reset is released, the SM5921A enters the initialization sequence and starts SDRAM initialization. The initialization requires an interval of 1/fs × 64. During the initialization sequence, input data on DIA, DIB, DIC, or DID is ignored. The system can also be reset without applying a LOW-level pulse on RSTN under the following conditions. When switching WPOLN pin or INIT flag The SDRAM initialization sequence also begins when the WPOLN pin is switched or the INIT flag is set. During SDRAM initialization, each output is muted by the direct mute function.
Word Clock Polarity (WPOLN pin)
The SM5921A handles 64fs slot data as 1 word, enabling the word boundary polarity to be specified. The WPOLN pin has pull-up resistor built-in. When WPOLN is open circuit (or HIGH), data is handled as leftchannel data when WCKI is HIGH. The data-through (bypass), output enable, and direct mute functions operate on the word boundary set by the WPOLN pin. Refer to the “TIMING DIAGRAMS” section for more information.
WPOLN LOW HIGH Function Data is handled as left-channel data during the LOW-level pulse on WCKI. The word boundary is a falling edge on WCKI. Data is handled as left-channel data during the HIGH-level pulse on WCKI. The word boundary is a rising edge on WCKI.
Data Through (THROU flag)
The SM5921A applies a fixed 2-sample system delay when exchanging with the SDRAM, even if the delay setting is 0 (see the “Delay Settings” section). The THROU flag in REG A/H can be set to 1 when a completely zero delay is required. When the THROU flag is set to 1, the DIA, DIB, DIC, DID input data bypasses the delay processing and is passed directly to the DOA, DOB, DOC, DOD outputs, respectively. The default setting of the THROU flag is 0, so if not set specifically, delayed data is output on the DOA, DOB, DOC, DOD pins. The THROU flag is detected on the WCKI boundary edge, which means that there is a maximum 1-word delay before the change is reflected at the output.
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SM5921A
Output Enable (OEN pin)
The SM5921A has an output enable control for the DOA, DOB, DOC, DOD outputs. When OEN is HIGH, the output pins are disabled. The OEN pin has a pull-down resistor built-in. When the OEN pin is open-circuit (or LOW), the output pins are enabled and delay data is output. The OEN pin is detected on the WCKI boundary edge, which means that there is a maximum 1-word delay before the change is reflected at the output.
Direct Mute (DMUTEN pin)
Direct mute ON/OFF
DMUTEN LOW HIGH Function 0 data output from the next output word after writing the setting. Normal delay data output from the next output word after writing the setting.
Other mute operations The outputs are also muted (direct mute) when a reset pulse is applied.
RSTN LOW HIGH Function 0 data output from the next output word after writing the setting. Normal delay data output after 64 output words after writing the setting.
The outputs are also muted (direct mute) when the INIT flag is set.
INIT LOW HIGH Normal output operation. Normal delay data output after a 64-word mute interval after writing the setting. Function
The outputs are also muted (direct mute) when the PDW flag is set.
PDW LOW (HIGH → LOW) HIGH Function 0 data output from the next output word after writing to the register. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output. 0 data output from the next output word after writing data to the register.
The outputs are also muted (direct mute) setting the delay data values.
Delay setting Intrinsic delay Individual delay Function 0 data output from the next output word after writing to registers REG 0/H and 1/H. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output. 0 data output from the next output word after writing to registers REG 3/H to 9/H. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output.
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SM5921A The outputs are also muted (direct mute) when changing the setting of the MP0n and MP1N flags.
MP0N, MP1N (L,L) → (H,L) (L,L) → (L,H) (H,H) → (H,L) (H,H) → (L,H) (H,L) → (L,L) (H,L) → (L,H) (H,L) → (H,H) (L,H) → (L,L) (L,H) → (H,L) (L,H) → (H,H) (L,L) → (H,H) (H,H) → (L,L) Function 0 data output from the next output word after changing the setting of the flags. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output.
0 data output from the next output word after changing the setting of the flags. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output. 0 data output from the next output word after changing the setting of the flags. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output. Normal output operation.
The outputs are also muted (direct mute) when setting the TRACKT and TRACKD flags.
TRACKT LOW (HIGH → LOW) HIGH (LOW → HIGH) Function 0 data output from the next output word after writing to the register. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output. 0 data output from the next output word after writing to the register. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output. Function 0 data output from the next output word after writing to the register. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output. 0 data output from the next output word after writing to the register. The outputs are muted during the interval until the initialization data write point, and then mute is released for delay data output.
TRACKD LOW (HIGH → LOW) HIGH (LOW → HIGH)
I
I
If the delay value is set during the 64-word direct mute interval after reset is released, the output muting is extended until the initialization data write point after the direct mute interval. If the delay value is updated during mute operation, and the extended mute interval determined by a previous delay setting is longer than that due to the updated value, muting continues until the previously set delay value setting. If that mute interval is smaller than that due to the updated value, muting continues until the point determined by the updated value. In other words, muting continues until a point determined by the larger of the two values.
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SM5921A Intrinsic delay timing example (TRACKT = LOW)
After writing, the first data writing point
WCKI
DIA, DIB
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIC, DID
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DOUTA, DOUTB
Lch
Rch
DMUTE
Lch
Rch
Lch
Rch
DOUTC, DOUTD
Lch
Rch
0/H writing
DMUTE
Lch
Rch
Lch
Rch
Individual delay timing example (TRACKD = LOW)
I
Mute interval determined by REG 2/H is larger than that determined by REG 4/H
After 2/H writing, the first data writing point
WCKI
After 4/H writing, the first data writing point
DIA
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIB
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIC
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DID
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DOUTA
Lch
Rch
DMUTE
Lch
Rch
DOUTB
Lch
Rch
DMUTE
Lch
Rch
DOUTC
Lch
Rch
DMUTE
Lch
Rch
DOUTD
Lch
Rch
DMUTE
4/H writing
Lch
Rch
2/H writing
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SM5921A Individual delay timing example (TRACKD = LOW)
I
Mute interval determined by REG 2/H is smaller than that determined by REG 4/H
Movement After 2/H writing, the first data writing point
WCKI
After 4/H writing, the first data writing point
DIA
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIB
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIC
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DID
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DOUTA
Lch
Rch
DMUTE
Lch
Rch
DOUTB
Lch
Rch
DMUTE
Lch
Rch
DOUTC
Lch
Rch
DMUTE
Lch
Rch
DOUTD
Lch
Rch
DMUTE
4/H writing
Lch
Rch
2/H writing
SEIKO NPC CORPORATION —16
SM5921A
MCU Interface
The MCU interface is comprised by a 4-wire serial interface.
SCLK XCS
RD/ A3 WR "0"
SI WRITE SIO SI READ SIO
A2
A1
A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
RD/ A3 WR "1"
A2
A1
A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
I
I
I
I
I
The SCLK clock may trace the dotted line path or not, as long as there is 17 SCLK pulses during the XCS LOW-level pulse interval. When the RD/WR bit is set to 1 the device enters register read mode, and the register contents addressed by bits A3 to A0 are output as serial data on the SIO pin. In read mode, the SI input data bits D11 to D0 are ignored. When the RD/WR bit is set to 0 the device enters register write mode, and the SI input data bits D11 to D0 are written to the register addressed by bits A3 to A0. Systems that hold the serial input high-impedance during the D11 to D0 data interval in read mode can bind the SI and SIO pins and function as a 3-wire serial interface. In read mode, the output for non-assigned addresses is 0 data.
SEIKO NPC CORPORATION —17
SM5921A
REG 0/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Intrinsic delay (DIA, DIB) 0 0 × × × × × × × × × × × × 333.2µs/step @ fs = 48kHz 1365ms/step @ fs = 48kHz 83.3µs/step @ fs = 192kHz 341.2ms/step @ fs = 192kHz Minimum unit setting: 16 samples 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 16 samples 0000 0000 1000 → 128 samples 0000 0001 0000 → 256 samples 0000 1000 0000 → 2048 samples 0001 0000 0000 → 4096 samples 1000 0000 0000 → 32768 samples 1111 1111 1111 → 65520 samples
REG 1/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Intrinsic delay (DIC, DID) 0 1 × × × × × × × × × × × × 333.2µs/step @ fs = 48kHz 1365ms/step @ fs = 48kHz 83.3µs/step @ fs = 192kHz 341.2ms/step @ fs = 192kHz Minimum unit setting: 16 samples 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 16 samples 0000 0000 1000 → 128 samples 0000 0001 0000 → 256 samples 0000 1000 0000 → 2048 samples 0001 0000 0000 → 4096 samples 1000 0000 0000 → 32768 samples 1111 1111 1111 → 65520 samples
SEIKO NPC CORPORATION —18
SM5921A
REG 2/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Individual delay (DIA left-channel) 1 0 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
REG 3/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Individual delay (DIA right-channel) 1 1 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
SEIKO NPC CORPORATION —19
SM5921A
REG 4/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 Individual delay (DIB left-channel) 0 0 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
REG 5/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 Individual delay (DIB right-channel) 0 1 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
SEIKO NPC CORPORATION —20
SM5921A
REG 6/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 Individual delay (DIC left-channel) 1 0 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
REG 7/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 Individual delay (DIC right-channel) 1 1 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
SEIKO NPC CORPORATION —21
SM5921A
REG 8/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 Individual delay (DID left-channel) 0 0 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
REG 9/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 Individual delay (DID right-channel) 0 1 × × × × × × × × × × × × 20.8µs/step @ fs = 48kHz 85.3ms/step @ fs = 48kHz 5.2µs/step @ fs = 192kHz 21.3ms/step @ fs = 192kHz Minimum unit setting: 1 sample 0000 0000 0000 → 0 samples (default) 0000 0000 0001 → 1 samples 0000 0000 1000 → 8 samples 0000 0001 0000 → 16 samples 0000 1000 0000 → 128 samples 0001 0000 0000 → 256 samples 1000 0000 0000 → 2048 samples 1111 1111 1111 → 4095 samples
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SM5921A
REG A/H
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 1 0 Miscellaneous settings 1 0 L L L L L L Do not use Do not use Do not use Do not use Do not use MP0N address shift setting 0 MP1N address shift setting 1 (MP0N, MP1N) = (L,L) → × 1 multiplication (MP0N, MP1N) = (L,H) → × 2 multiplication (MP0N, MP1N) = (H,L) → × 4 multiplication (MP0N, MP1N) = (H,H) → × 1 multiplication THROU flag THROU = H: Input data is passed through to the output bypassing delay processing. THROU = L: Normal operating mode (default) TRACKD flag TRACKD = H: REG 3/H to REG5/H follow the REG 2/H contents. REG 7/H to REG9/H follow the REG 6/H contents. TRACKD = L: Normal operating mode (default) TRACKT flag TRACKT = H: REG 1/H follows the REG 0/H contents. TRACKT = L: Normal operating mode (default) PDW flag PDW = H: PDW = L: INIT flag INIT = H: INIT = L: Issues the power-down command to the SDRAM. Normal operating mode (default) Starts the SDRAM initialization process. INIT is set to L when the initialization process ends. Normal operating mode (default)
D5
L
D4
L
D3
L
D2
L
D1
L
D0
L
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SM5921A
SDRAM
SDRAM compatibility The SM5921A transfers data when the SDRAM mode register (MRS) has the following settings. SDRAM devices that support these settings are compatible. CL (CAS latency) : 2 BL (Burst length) : 2, 8 WT (Wrap type) : Sequential Connecting to SDRAM The SM5921A supports 16M/64M/128M (×16 devices) SDRAM. The SDRAM interface is connected as described in the following table.
SM5921A pins SDRAM pins 16M SDRAM connection CS CLK CKE BA1 BA0 (BA) A11 A10 to A0 RAS CAS WE HDQM LDQM DQ15 to DQ0 CSN CLKO CKE – BA – A10 to A0 RASN CASN WEN DQM DQM DQ15 to DQ0 64M SDRAM connection CSN CLKO CKE LOW-level BA LOW-level A10 to A0 RASN CASN WEN DQM DQM DQ15 to DQ0 128M SDRAM connection CSN CLKO CKE LOW-level BA LOW-level A10 to A0 RASN CASN WEN DQM DQM DQ15 to DQ0
SEIKO NPC CORPORATION —24
SM5921A
TIMING DIAGRAMS
Input Timing (WCKI, BCKI, DIA, DIB, DIC, DID pins)
WCKI (fs) BCKI (64fs)
Lch
Rch
DI*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 1. 64fs/slot, WPOLN = H DI*: DIA, DIB, DIC, DID pins
WCKI (fs) BCKI (64fs)
Lch
Rch
DI*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 2. 64fs/slot, WPOLN = L DI*: DIA, DIB, DIC, DID pins
Output Timing (WCKI, BCKI, DOUTA, DOUTB, DOUTC, DOUTD pins)
WCKI (fs) BCKI (64fs)
Lch
Rch
DOUT*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 3. 64fs/slot, WPOLN = H DOUT*: DOUTA, DOUTB, DOUTC, DOUTD pins
WCKI (fs) BCKI (64fs)
Lch
Rch
DOUT*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 4. 64fs/slot, WPOLN = L DOUT*: DOUTA, DOUTB, DOUTC, DOUTD pins
SEIKO NPC CORPORATION —25
SM5921A
TYPICAL APPLICATION CIRCUITS
16M SDRAM (MSM56V16160) Connection Example
XCS SCLK SI SIO CSN CLKO CLE BA A10 to A0 RASN CASN WEN
MCU
SM5921A
WCKI BCKI
16M SDRAM MSM56V16160 OKI
DQM
HDQM LDQM
Digital signal processor
DIA DIB DIC DID WPOLN OEN DMUTEN
DQ15 to DQ0
64M SDRAM (MD56V62160) Connection Example
XCS SCLK SI SIO CSN CLKO CLE BA A10 to A0 RASN CASN WEN BA0 BA1 A11
MCU
SM5921A
WCKI BCKI
64M SDRAM MD56V62160 OKI
DQM
HDQM LDQM
Digital signal processor
DIA DIB DIC DID WPOLN OEN DMUTEN
DQ15 to DQ0
SEIKO NPC CORPORATION —26
SM5921A
Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC0514CE 2007.07
SEIKO NPC CORPORATION —27
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