SM6451

SM6451BV NIPPON PRECISION CIRCUITS INC. Audio Variable Volume IC OVERVIEW The SM6451BV is a 3-wire serial-controlled electronic variable volume IC for audio applications. It provides electronic volume control for a stereo system (left and right channels), and independent channel attenuation and muting, with greatly enhanced digital zip noise suppression. The chip address function allows up to four SM6451BV devices to be connected and individually controlled over the 3-wire control interface from a single CPU. It is available in 16-pin VSOP packages. FEATURES s s PINOUT (Top View) s s s s s s Stereo inputs and outputs Attenuation function • 2-channel independent control • 1.0 dB/step over 80 steps • 0 to −80 dB range Mute function 3-wire serial data control (MDT, MCK, MLEN) Chip addressing (up to 4 devices can be connected in parallel) Low noise • 0.003 % THD + noise • 12 µVrms residual noise 2.5 to 3.6 V single power supply Silicon-gate CMOS process RSTN ADRS1 ADRS2 DVDD LOUT LIN AVDD VRL 1 16 MDT MCK MLEN DVSS ROUT RIN AVSS 6451BV 8 9 VRR APPLICATIONS s Audio equipment PACKAGE DIMENSIONS (Unit: mm) 16 pin VSOP ORDERING INFORMATION D e vice SM6451BV P ackag e 16-pin V S O P 4.4 0.2 6.4 0.2 0.275TYP 5.1 0.2 0.15 - + 0.1 5 0.0 0 10 0.10 0.22 - 0.05 + 0.10 0.10 0.05 1.15 0.1 0.65 0.12 M 0.5 0.2 NIPPON PRECISION CIRCUITS—1 S M6451BV BLOCK DIAGRAM DVDD DVSS Attenuation Control 1/2VDD LIN LOUT MLEN MCK MDT RSTN Chip Address Decoder ADRS1 ADRS2 VRL Reference Voltage Circuits Attenuation Decoder Attenuation Control Interface Control VRR 1/2VDD RIN ROUT AVDD AVSS PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. Name RSTN ADRS1 ADRS2 DV D D LOUT LIN AV D D VRL VRR AV S S RIN ROUT DV S S MLEN MCK MDT I/O 1 Ip Ip Ip – O I – O O – I O – Ip Ip Ip A/D1 D D D D A A A A A A A A D D D D D escription System reset input (LOW -level reset) Chip address set 1 Chip address set 2 Digital supply Left-channel audio output Left-channel audio input Analog supply Left-channel reference voltage (0.5V D D ). Connect a 10 µF capacitor between VRL and AV S S . Right-channel reference voltage (0.5V D D ). Connect a 10 µF capacitor between VRR and AV S S . Analog ground Right-channel audio input Right-channel audio output Digital ground Microcontroller latch enable input Microcontroller clock input Microcontroller data input Ip = input pin with pull-up, A = analog, D= digital NIPPON PRECISION CIRCUITS—2 S M6451BV SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSS = 0 V, DVDD = AVDD = VDD P arameter S upply voltage Input voltage Pow er dissipation Storage temperature Soldering temperature Soldering time Symbol VDD V IN PD T s tg T s ld ts ld Rating −0 .3 to 7.0 V S S − 0 .3 to V D D + 0 .3 1 50 −5 5 to 125 2 55 10 Unit V V mW °C °C s Recommended Operating Conditions DVSS = AVSS = 0 V, DVDD = AVDD = VDD P arameter S upply voltage Supply voltage deviation Operating temperature Symbol VDD DV D D − AV D D , DV S S − AV S S T o pr Rating 2 .5 to 3.6 ± 0.1 −4 0 to 85 Unit V V °C DC Characteristics DVDD = AVDD = VDD = 2.5 to 3.6 V, VSS = 0 V, Ta = −40 to 85 °C Rating P arameter Symbol Condition min ID D D 1 ID D D 2 AVDD Current consumption HIGH-level input voltage 1 L O W -level input Input current 1 current 1 voltage 1 ID D A V IH V IL II L II H V IN = 0 V V IN = V D D D ata transfer stopped, MDT, MCK, MLEN, RSTN, ADRS1, ADRS2 = V D D A D R S 1 = A D R S 2 = 0 V, 0.8 Vr ms analog input, ATT = 0 d B , data transfer active – – – 0 .7V D D – – – typ 0.2 0.4 1.9 – – 70 – max 1.0 1.0 5.5 – 0.3V D D 150 1.0 µA mA mA V V µA µA Unit D VDD Current consumption Input leakage 1. M D T, MCK, MLEN, RSTN, ADRS1, ADRS2 NIPPON PRECISION CIRCUITS—3 S M6451BV AC Digital Characteristics DVDD = AVDD = VDD = 2.5 to 3.6 V, VSS = 0 V, Ta = −40 to 85 °C Serial inputs (MDT, MCK, MLEN) Rating P arameter M C K , M L E N r ise time MCK, MLEN fall time MDT setup time MDT hold time MLEN setup time MLEN hold time M L E N L OW -level pulsewidth MLEN HIGH-level pulsewidth Symbol min tr tf tM D S tM D H tM C S tM C H tM E W L tM E W H – – 50 50 50 50 50 50 typ – – – – – – – – max 100 100 – – – – – – ns ns ns ns ns ns ns ns Unit MDT tMDS MCK tMCS MLEN tMEWL tf MCK MLEN 0.9VDD 0.1VDD 0.5VDD tMDH 0.5VDD tMCH 0.5VDD tMEWH tr 0.9VDD 0.1VDD 0.5VDD Reset input (RSTN) Rating P arameter R S T N L OW -level pulsewidth Symbol min tR S T N 1 00 typ – max – ns Unit NIPPON PRECISION CIRCUITS—4 S M6451BV AC Analog Characteristics VDD = 3.0 V, 0.8 Vrms amplitude, 1 kHz input frequency, 100 kΩ output load resistance, Ta = 25 °C, AC-coupled inputs Analog inputs (LIN, RIN) Rating P arameter R eference input amplitude Input resistance I nput clipping voltage Symbol V AI R IN VCLP T HD + N = 1%, ATT = 0 dB Condition min – 40 – typ 0.8 50 1.1 max – 60 – Vr m s kΩ Vr m s Unit Analog outputs (LOUT, ROUT) Rating P arameter R esidual noise voltage Signal-to-noise ratio Total harmonic distortion + noise Gain control range Step size Attenuation error (1k to 20kHz) Symbol VNS SNR THD + N RCNT Step ERR1 ERR2 AT 0 AT 2 Absolute attenuation (1 kHz) AT 4 AT 6 AT 8 Mute attenuation (1 kHz) Channel crosstalk Frequency response Quiescent output zip noise voltage (while ATT value adjusting) Minimum driver load resistance Mute CT FR NJ RML 0 t o −6 0 dB −6 1 to −8 0 dB A TT = 0 dB A TT = −2 0 dB A TT = −4 0 dB A TT = −6 0 dB A TT = −8 0 dB ATT = Mute ATT = 0 dB ATT = 0 dB, f = 200 kHz 0 V r ms input A TT = 0 dB, THD + N = 1% Condition min I nput signal: 0 Vr m s , A - weight filter, 0 dBr = 0.8 Vr m s , ATT = 0 dB ATT = 0 dB, 20 kHz lowpass filter – 92 – – 80 0.8 –2 –6 – – – – – – 85.0 – 103 – 10 – – typ 12 96 0.0025 – 1.0 – – – 0.0 – 20.0 – 40.0 – 60.4 – 84.2 – 88.0 – 105 –8 – 8 max 20 – 0.005 0 1.8 1 0 – – – – – – – – 3 12 µV r m s dBr % dB dB dB dB dB dB dB dB dB dB dB dB mV kΩ Unit Reference voltage (VRL, VRR) Rating P arameter R eference voltage output Symbol VREF Condition min 0 .45V D D typ 0 .5V D D max 0 .55V D D V Unit NIPPON PRECISION CIRCUITS—5 S M6451BV MEASUREMENT CIRCUIT Chip address: ADRS1 = LOW, ADRS2 = LOW 0.001µF 1 RSTN 2 ADRS1 3 ADRS2 4 DVDD MDT 16 MCK 15 MLEN 14 DVSS 13 ROUT 12 RIN 11 AVSS 10 VRR 9 0.022µF + 10µF + 1µF + 1µF 100kΩ CPU SM6451 + 10µF 0.022µF 5 LOUT 6 LIN + 1µF + 1µF 7 AVDD + 10µF 8 VRL 0.022µF + 10µF 0.022µF 100kΩ Generator Analyzer Audio Precision System Two SYS − 2322A NIPPON PRECISION CIRCUITS—6 S M6451BV MICROCONTROLLER INTERFACE The SM6451BV uses a 3-wire serial interface comprising MDT (data), MCK (clock) and MLEN (latch enable) to select channels and attenuation levels for the addressed device. Input Timing The microcontroller data input timing is shown in figure 1. MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCK MLEN Figure 1. Microcontroller data input timing Data is shifted into the internal shift register on the rising edge of MCK, and the attenuation value is updated on the rising edge of MLEN. Accordingly, data on MDT should be changed on the falling edge of MCK. The dotted lines for MCK and MLEN also indicate valid timing. Note, however, a minimum of 16 MCK input pulses are required. Data Format The format of microcontroller input data is shown in figure 2. Attenuation Data 7 Attenuation Data 6 Attenuation Data 5 Attenuation Data 4 Attenuation Data 3 Attenuation Data 2 Attenuation Data 1 MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Figure 2. Microcontroller data format D15, D14 Don’t care. D13, D12 Chip address bits. D13 corresponds to ADRS1 and D12 corresponds to ADRS2. The device is addressed only when ADRS1:ADRS2 matches D13:D12. Example 1: If D13 = LOW, D12 = HIGH and ADRS1 = LOW, ADRS2 = LOW, then the device is not addressed since ADRS2 and D12 do not match. Example 2: If D13/D12 = LOW and ADRS1/ADRS2 = LOW, then the device is addressed and all input data is read and the attenuation settings updated. D11, D10 Don’t care. NIPPON PRECISION CIRCUITS—7 Attenuation Data 0 Chip Address 1 Chip Address 2 Channel Select Channel Select Don't Care Don't Care Don't Care Don't Care D0 S M6451BV D9, D8 Channel select bits. The selected channel(s) are shown in table 1. Table 1. Channel select D9 LOW LOW HIGH HIGH D8 LOW HIGH LOW HIGH Selected channel Both left and right channels Left channel Right channel No change D7 to D0 Attenuation register (ATT) set bits. Table 2. Attenuation setting1 A ttenuation 0 dB −1 d B −2 d B : −1 5 dB −1 6 dB −1 7 dB : −6 3 dB −6 4 dB −6 5 dB : −7 9 dB −80 dB Mute Mute : Mute Mute 1. AT T H 00 01 02 : 0F 10 11 : 3F 40 41 : 4F 50 51 52 : FE FF D7 LOW LOW LOW : LOW LOW LOW : LOW LOW LOW : LOW LOW LOW LOW : HIGH HIGH D6 LOW LOW LOW : LOW LOW LOW : LOW HIGH HIGH : HIGH HIGH HIGH HIGH : HIGH HIGH D5 LOW LOW LOW : LOW LOW LOW : HIGH LOW LOW : LOW LOW LOW LOW : HIGH HIGH D4 LOW LOW LOW : LOW HIGH HIGH : HIGH LOW LOW : LOW HIGH HIGH HIGH : HIGH HIGH D3 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D2 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D1 LOW LOW HIGH : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW HIGH : HIGH HIGH D0 LOW HIGH LOW : HIGH LOW HIGH : HIGH LOW HIGH : HIGH LOW HIGH LOW : LOW HIGH Outputs are muted after system reset. Attenuation error is changed dependent on the supply voltage when attenuation level is under – 60dB. In the case of the supply voltage being under 2.6V, mute level inverses up to the same level of – 80dB setting or more. (see Figure 6) NIPPON PRECISION CIRCUITS—8 S M6451BV ANALOG PERFORMANCE CHARACTERISTICS DVDD = AVDD = 3.0 V, 100 kΩ output load resistance, Ta = 25 °C 1 f=1kHz ATT=0dB 20kHz LPF 0.1 ATT=0dB 20kHz LPF THD+N(%) VDD=3.3V VDD=3.0V VDD=2.7V THD+N(%) 0.1 VIN=0.2Vrms 0.01 VIN=0.5Vrms 0.01 VIN=0.8Vrms 0.001 .1 .2 .5 1 1.2 VIN(Vrms) 0.001 20 100 1k 10k 20k Frequency(Hz) Figure 3. THD + N vs. input amplitude Figure 4. THD + N vs. input frequency 2 1 0 VIN=0.8Vrms f=1kHz -64 -68 -72 Ideal Gain Error(dB) -1 -2 -3 -4 -5 0 -10 -20 -30 -40 -50 -60 -70 -80 Gain(dB) -76 -80 -84 -88 -92 -64 -68 -72 -76 -80 Mute VDD=3V VDD=2.7V VDD=2.5V ATT(dB) ATT(dB) Figure 5. Attenuation error Figure 6. Attenuation characteristic (– 64dB to MUTE) 20 +10 VIN=0Vrms A-Weight Filter +0 -10 -20 ATT=0dB VIN=0.8Vrms Residual Noise(µVrms) 16 ATT=-20dB 12 Gain(dB) -30 -40 -50 -60 -70 -80 -90 ATT=MUTE ATT=-60dB ATT=-40dB 8 4 ATT=-80dB 0 0 -10 -20 -30 -40 -50 -60 -70 -80 -100 20 100 1k 10k 100k 200k ATT(dB) Frequency(Hz) Figure 7. Residual noise vs. ATT Figure 8. Frequency response NIPPON PRECISION CIRCUITS—9 S M6451BV -40 +0 VIN=0.8Vrms ATT=0dB -60 -20 FFT Spectrum(dBr) Cross Talk(dB) VIN=0.8Vrms=0dBr f=1kHz ATT=0dB BH Window -40 -60 -80 -100 -120 -80 -100 -120 -140 20 100 1k 10k 100k 200k -140 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Frequency(Hz) Frequency(Hz) Figure 9. Crosstalk frequency response Figure 10. FFT spectrum 100 6 10 Current Consumption(mA) VIN=0.8Vrms f=1kHz ATT=0dB 20kHz LPF 5 AVDD+DVDD ADRS1=ADRS2=0V THD+N(%) 4 3 2 1 0 2.4 1 0.1 0.01 0.001 1 10 Load Resistance(kΩ) 100 2.7 3 3.3 3.6 Power Supply(V) Figure 11. THD + N vs. load resistance Figure 12. Current consumption vs. supply voltage 6 Current Consumption(mA) 5 AVDD+DVDD ADRS1=ADRS2=0V 4 3 2 VDD=2.7V VDD=3.3V VDD=3.0V 1 0 -50 -25 0 25 50 75 100 Operating Temperature(°C) Figure 13. Current consumption vs. operating temperature NIPPON PRECISION CIRCUITS—10 S M6451BV TYPICAL APPLICATIONS Connection Guidelines Decoupling capacitors of approximately 10 µF should be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS. In addition, approximately 0.01 µF capacitors should also be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS to suppress digital switch noise. An approximately 0.001 µF capacitor connected from RSTN to DVSS will force a system reset when power is applied. Connection 1 (to DAC) CPU MDT MCK MLEN LPF DAC LPF 2.5 to 3.6V RIN ROUT R-ch OUT LIN LOUT L-ch OUT SM6451 DVDD AVDD ADRS1 DVSS AVSS ADRS2 Connection 2 When there is a possibility that the input peak-to-peak amplitude will exceed the supply voltage, input protection diodes should be connected to prevent device breakdown. AVDD L-ch Input LIN LOUT L-ch Output SM6451 R-ch Input RIN ROUT R-ch Output AVSS NIPPON PRECISION CIRCUITS—11 S M6451BV NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9925AE 2000.02 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—12