SM8222BP

SM8222A/B NIPPON PRECISION CIRCUITS INC. Caller ID Service IC with Call Waiting The SM8222A/B is a calling number identification (caller ID) and call waiting signal (dual tone signal) receiver decoder IC that conforms with the TRNWT-000030 and SR-TSV-002476 (Bellcore) dialer FEATURES s s s s s s s Conforms to TR-NWT-000030 and SR-TSV002476 (Bellcore) standards Call waiting FSK demodulator Ring signal detect circuit built-in High input sensitivity Input gain adjust circuit built-in Power-down mode APPLICATIONS s s Telephones that display dialer number before and during conversation Adapters to display dialer number before and during conversation ORDERING INFORMATION D e vice S M8222AS SM8222AP SM8222BS SM8222BP lim s s s P ackag e 24-pin SOP 24-pin DIP pre 24-pin DIP 24-pin SOP ina ry s s s s s s s OVERVIEW telephone number display standards. It is implemented in CMOS and incorporates a power-down function for low power operation. Crystal oscillator circuit built-in Single supply operation Microcontroller I/O interface Molybdenum-gate CMOS process 24-pin SOP and 24-pin DIP packages SM8222A : 2.7 to 3.3V operation SM8222B : 4.5 to 5.5V operation Answering machines Facsimile machines Computer peripheral devices PINOUT (Top View) TIP RING GS AGND CAP RDIN RDRC RDET MODE OSCIN 1 24 VDD STGT EST STD INT CDET DR DOUT DCLK FSKEN PDWN OSCOUT GND 12 13 IC NIPPON PRECISION CIRCUITS—1 S M8222A/B PACKAGE DIMENSIONS (Unit: mm) 24-pin SOP 24-pin DIP 0.05min 2.80max 1.27 0.45 0.10 0.10 0.13 M 0.50 0.20 3.00min 2.54 0.45 0.08 BLOCK DIAGRAM lim Amplifier Filter Carrier Detector Filter (2130Hz) Filter Bias Generator Filter (2750Hz) Oscillator OSCIN OSCOUT RDIN RDRC RDET FSKEN MODE 0.51min 1.50 − 0 + 0.50 DOUT Data Timing Control DCLK DR TIP RING GS FSK Demodulator CDET Interrupt Generator INT Data Detector (2130Hz) pre CAP AGND Level Detector Guard Time Control Data Detector (2750Hz) STD STGT EST Level Detector PDWN VDD GND NIPPON PRECISION CIRCUITS—2 0.25 0 .05 + 0.25 15.24 − 0.20 4.96max 0.15 − 0.0 ina ry 30.20 − 0.30 + 0.20 7.60 0.30 10.20 0.40 13.55 0.25 + 0.05 2 15.24 15 max S M8222A/B PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name TIP RING GS AGND CAP RDIN RDRC RDET MODE OSCIN OSCOUT GND IC PDWN I/O I I O O I I I/O O I I O – I I Description Tip input: Connected to the telephone through a protection circuit. Ring input: Connected to the telephone through a protection circuit. Input stage amplifier output: Used to select the input amplifier gain Analog ground: Internal reference voltage (VD D /2) output. Reference voltage capacitor connection. C = 0.1 µF Ring detect input: Line reversal and ring signal detect input. Connect to detect attenuated ring signals. Schmitt-trigger input. Ring detect RC connection: RC network connection to set the ring detect delay time. Open-drain output and schmitt-trigger input. Ring detect output: RDRC schmitt-trigger buffer output. LOW when a ring signal is detected. FSK interface mode select: Demodulated FSK signal output method select. LOW [Mode = 0]: Demodulated data output and data sync clock output. HIGH [Mode = 1]: Data output in sync with an external clock. Crystal oscillator element input: Oscillator element connection between OSCIN and OSCOUT. Crystal oscillator element output: Oscillator element connection between OSCIN and OSCOUT. Ground: Connect to system ground. Test input: Tie LOW for normal operation. Power-down control: LOW for normal operation. HIGH for device power-down state. When device is powered-down, AGND, OSCOUT, DCLK, DOUT, INT, CDET are all HIGH. DR also goes HIGH in mode 0 output. Schmitt-trigger input. FSK signal output control: Demodulated FSK signal output and carrier detect output control. Mode 0: DCLK, DOUT, DR , CDET control Mode 1: DCLK, DOUT, CDET control FSK signal reception enabled when HIGH. Signal pins (above) go HIGH when FSKEN is LOW. FSK interface clock: Demodulated FSK signal output clock. Mode 0: Clock output in sync with data Mode 1: Data read clock input Data output: Demodulated FSK signal output. HIGH-level output when PDWN is HIGH or FSKEN is LOW, or when CDET is HIGH in receive state. 15 FSKEN 16 DCLK 17 18 19 20 DOUT DR pre INT O 21 22 23 STD EST O O STGT VDD I/O – 24 CDET lim I I/O O O O Supply voltage Data output trigger: Demodulated FSK data timing output. Active-LOW. Becomes active when 8 bits of data are completed. Carrier (FSK signal) detect output: Goes LOW when a valid carrier signal is detected. Interrupt signal output: Goes LOW when either RDET is LOW, DR is LOW or STD is HIGH. Dual tone indicator output: Goes HIGH if the dual tone detect signal is recognized after the external RC circuit time delay has elapsed. Dual tone detect output: Goes HIGH when the dual tone is detected. Dual tone RC time constant circuit connection: External RC network connection for dual tone signal detection processing. Sets STD output. ina ry NIPPON PRECISION CIRCUITS—3 S M8222A/B SPECIFICATIONS Absolute Maximum Ratings GND = 0 V P arameter Supply voltage range Input voltage range Input current Power dissipation Storage temperature range Symbol VDD V IN IIN PD Tstg Condition S M8222A Rating −0.5 to 5.0 −0.5 to 7.0 Unit V Recommended Operating Conditions GND = 0 V P arameter Symbol Supply voltage range Clock frequency Clock frequency accuracy Operating temperature VDD fC LK ∆fC lim Topr pre NIPPON PRECISION CIRCUITS—4 ina ry SM8222B −0.3 to V D D + 0.3 10 44 V mA mW °C −40 to 125 Rating typ – – Condition Unit min 2.7 4.5 – max 3.3 5.5 – S M8222A SM8222B V 3.579545 – MHz % −0.1 −20 +0.1 85 – °C S M8222A/B DC Electrical Characteristics s SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol Condition min OSCIN = PWDN = RDIN = RDRC = MODE = 0 V, FSKEN = V D D, all other inputs open typ max Unit Current consumption ID D Power-down current consumption ID PD LOW-level input voltage 1 HIGH-level input voltage 1 LOW-level input voltage 2 HIGH-level input voltage 2 LOW-level input voltage 3 HIGH-level input voltage 3 LOW-level output current HIGH-level output current Input leakage current Output leakage current s V IL1 V IH1 V IL2 V IH2 V IL3 V IH3 IO L IO H IIN lim OSCIN, PWDN, RDIN R DRC, INT IO FF Symbol Condition ID D ID PD V IL1 PWDN, MODE, FSKEN V IH1 V IL2 PWDN, MODE, FSKEN RDIN, RDRC RDIN, RDRC O SCIN O SCIN D OUT, EST, STD, STGT, DCLK, DR , RDET, CDET D OUT, EST, STD, STGT, DCLK, DR , RDET, CDET OSCIN, PWDN, RDIN R DRC, INT V IH2 V IL3 V IH3 IO L IO H IIN IO FF SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating Unit min typ max P arameter Current consumption pre Power-down current consumption LOW-level input voltage 1 HIGH-level input voltage 1 LOW-level input voltage 2 HIGH-level input voltage 2 LOW-level input voltage 3 HIGH-level input voltage 3 LOW-level output current HIGH-level output current Input leakage current Output leakage current ina ry – 2.5 4.5 mA OSCIN = RDIN = RDRC = MODE = 0 V, PWDN = FSKEN = V D D, all other inputs open PWDN, MODE, FSKEN – – 15 µA – – 0.3VD D – V PWDN, MODE, FSKEN RDIN, RDRC RDIN, RDRC 0.7VD D – – V – 0.3VD D – V 0.7VD D – – V O SCIN O SCIN – – TBD – V V TBD 2 – D OUT, EST, STD, STGT, DCLK, DR , RDET, CDET – – – mA D OUT, EST, STD, STGT, DCLK, DR , RDET, CDET −0.8 1 1 mA µA µA −1 – – – OSCIN = PWDN = RDIN = RDRC = MODE = 0 V, FSKEN = V D D, all other inputs open – 4.5 8.0 mA OSCIN = RDIN = RDRC = MODE = 0 V, PWDN = FSKEN = V D D, all other inputs open – – 15 µA – 0.7VD D – 0.7VD D – TBD 2 – −1 – – – – – – – – – – – 0.3VD D – 0.3VD D – TBD – – −0.8 1 1 V V V V V V mA mA µA µA NIPPON PRECISION CIRCUITS—5 S M8222A/B AC Electrical Characteristics FSK decoder s SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter Input sensitivity Symbol Bandpass filter frequency response (relative gain for 1700 Hz sine wave input) Carrier detect sensitivity No-carrier detect sensitivity Oscillator frequency s CD O N CD O FF fC LK SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter Input sensitivity lim Symbol Condition 60 Hz 1200 Hz 2200 Hz 4000 Hz ≥ 10,000 Hz CD O N CD OFF fCLK Bandpass filter frequency response (relative gain for 1700 Hz sine wave input) Carrier detect sensitivity No-carrier detect sensitivity Oscillator frequency pre ina ry Condition Unit min – typ max −48 CD O N – d Bm 60 Hz – −80 −1 0 1200 Hz – – – – 2200 Hz 4000 Hz – dB −43 – ≥ 10,000 Hz – −54 – – −48 −51 −44 – dBm −55 dBm −0.1% 3.579545 +0.1% MHz Rating typ −48 −80 −1 0 −43 −54 −48 −51 3.579545 Unit min – – – – – – – −55 −0.1% max CD O N – – – – – −44 – +0.1% dBm dBm MHz dB d Bm NIPPON PRECISION CIRCUITS—6 Rating SM8222A/B Dual tone detector s SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Low tone frequency High tone frequency Detection frequency deviation No-detection frequency deviation Detection sensitivity No-detection sensitivity Signal level difference s Symbol fL fH Condition min – – typ 2130 2750 – max – – Unit Hz Hz % SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter Low tone frequency High tone frequency Detection frequency deviation Symbol fL fH Condition lim No-detection frequency deviation Detection sensitivity No-detection sensitivity Signal level difference pre NIPPON PRECISION CIRCUITS—7 ina ry 1.1 – 3.5 – – % −37.78 – – – dBm – −43.78 6 dBm dB – – Rating typ Unit Hz Hz % % dBm dBm dB min – – max – – 2130 2750 – – – – – 1.1 3.5 −37.78 – – – – – −43.78 6 SM8222A/B Input Stage Amplifier Characteristics s SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Input leakage current Input resistance DC open loop voltage gain Unity gain frequency Maximum load capacitance Maximum load resistance s Symbol IIN R IN AVOL fC CL RL Condition min – – typ – max 1 – Unit µA SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter Input leakage current Input resistance DC open loop voltage gain Unity gain frequency Symbol IIN R IN AVOL fC Condition lim CL RL Symbol Condition tDOSC tDAQ tDCH Symbol Condition tDOSC tDAQ tDCH Maximum load capacitance Maximum load resistance Timing Characteristics FSK decoder s SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating Unit min – 2.5 3.75 typ 5 – – max – 10 11.25 ms ms ms pre Power-down release to oscillator start time Carrier detect ON time Final data to carrier detect OFF time s P arameter SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating Unit min – 2.5 3.75 typ 5 – – max – 10 11.25 ms ms ms P arameter Power-down release to oscillator start time Carrier detect ON time Final data to carrier detect OFF time ina ry TBD – MΩ dB TBD – TBD – – – MHz pF – TBD – 50 – kΩ Rating typ – Unit µA min – – max 1 – TBD – MΩ dB TBD – TBD – 50 – – – – TBD – MHz pF kΩ NIPPON PRECISION CIRCUITS—8 SM8222A/B Output timing circuit: mode 0 s SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Rise time Fall time LOW-level pulsewidth HIGH-level pulsewidth DCLK frequency Input/output delay DOUT to DCLK delay DCLK to DOUT delay DCLK to DR delay Data rate s Symbol tr0 tf0 tPWL tPWH fDCLK0 tIDD tDCD tCDD tCRD Condition min DR , DCLK, DOUT DR , DCLK, DOUT DR , DCLK DCLK – – typ – – max TBD TBD 417 Unit ns ns SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter Rise time Fall time LOW-level pulsewidth HIGH-level pulsewidth DCLK frequency Input/output delay DOUT to DCLK delay DCLK to DOUT delay DCLK to DR delay Data rate Symbol tr0 tf0 Condition lim DR , DCLK, DOUT DR , DCLK, DOUT DR , DCLK DCLK tPWL tPWH fDCLK0 tIDD DCLK Input → DOUT tDCD DOUT → DCLK DCLK → DOUT DCLK → D R DOUT tCDD tCRD pre ina ry 415 416 µs 415 416 417 µs DCLK 1201.6 – 1202.8 – 1204 TBD – Hz Input → DOUT ms µs DOUT → DCLK DCLK → DOUT DCLK → D R DOUT TBD 416 TBD 415 416 – µs 416 417 µs 1188 1200 1212 baud Rating typ – – 416 416 1202.8 – 416 416 416 1200 Unit ns ns µs µs Hz ms µs µs µs baud min – – 415 415 1201.6 – TBD TBD 415 1188 max TBD TBD 417 417 1204 TBD – – 417 1212 NIPPON PRECISION CIRCUITS—9 SM8222A/B Output timing circuit: mode 1 s SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter DCLK rise time DCLK fall time Duty Frequency DCLK to DR setup time DR to DCLK hold time s Symbol tr1 tf1 DCLK DCLK DCLK Condition min – – typ – – max TBD TBD 70 1 Unit ns ns % fDCLK1 tDDS tDDH SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter DCLK rise time DCLK fall time Duty Frequency DCLK to DR setup time DR to DCLK hold time Symbol tr1 tf1 Condition lim fDCLK1 tDDS DCLK DCLK → D R tDDH DR → DCLK pre NIPPON PRECISION CIRCUITS—10 ina ry 30 – – DCLK – MHz ns DCLK → D R 500 – – DR → DCLK 500 – – ns Rating typ – – Unit ns ns % min – – max DCLK DCLK DCLK TBD TBD 70 1 – – 30 – 500 500 – – – – MHz ns ns SM8222A/B FUNCTIONAL DESCRIPTION The SM8222A/B conforms with the SR-TSV002476 (Bellcore) dialer telephone number display standards. It supports the following functions. s s s Mode 0 Using these functions enables systems with the following features to be easily constructed. s s s Ring signal and polarity reversal signal detection dialer telephone number display before telephone off-hook dialer telephone number display after telephone off-hook (during conversation) Ring Signal Detection FSK Demodulation pre s s s s s s The SM8222A/B incorporates an FSK demodulator to recover the dialer telephone number and other information which is sent as an FSK signal. It supports two demodulator output modes to facilitate various circuit design approaches. The FSK signal (Bellcore) standard is described as follows. Modulation type: Continuous-phase binary frequency-shift-keying Logic 1 data (mark): 1200 ± 12 Hz Logic 0 data (space): 2200 ± 22 Hz Input level (mark): −32 to −12 dBm Input level (space): −36 to −12 dBm Transmission speed: 1200 ± 12 baud The FSK output is controlled by the FSKEN pin. When FSKEN is HIGH, the signal pins DOUT, DCLK, DR and CDET are all HIGH. The decoded FSK signal is output on DOUT. The mode of the output timing circuit, mode 0 or mode 1, is set by the input on MODE. NIPPON PRECISION CIRCUITS—11 lim The telephone line input signals L1 and L2 pass through surge protection circuits and are input to a capacitor, resistor and diode bridge, as shown in the typical application circuit example. The signal is full-wave rectified by the diode bridge and the bridge output is level shifted by the resistor voltage divider for input to RDIN. A ring signal input on RDIN causes RDRC to become active, driving an RC time constant circuit formed by an external capacitor and resistor, before the detection signal is output on RDET. If the ring signal supplied by the inputs L1 and L2 is above the level set by the resistor divider, then the detect output RDET goes LOW. When a ring signal is detected, INT also goes LOW. ina ry Mode 1 Ring signal detection FSK demodulation Dual tone detection In mode 0, the received data and the clock that the data is synchronized to are both output. In addition, an output pulse occurs on DR with the same timing as each stop bit in the input data stream. In mode 1, DR goes LOW when data is received. From that point on, the data is read out with timing set by an external clock input on DCLK. In this mode, data can be read out at a different speed to the input data rate. Dual Tone Detection After a conversation has been initiated (after telephone is off-hook), the dialer telephone number service information is sent by mixing two signals, 2130 and 2750 Hz, on the line inputs L1 and L2. The SM8222A/B incorporates detectors to recover these two signals from the conversation “noise” signal. The two signals are recovered using two high-order filters with center frequencies of 2130 and 2750 Hz, respectively, in the final stage. The SM8222A/B uses a detection circuit with time delay built-in so that detection is maintained for an input signal where the input level temporarily rises above the rated value or falls below the rated value to a level of non-detection. When the 2130 and 2750 Hz signals are simultaneously detected, EST goes HIGH and starts charging the time constant circuit formed by an external capacitor and resistor. When the time constant circuit voltage STGT rises above a threshold voltage, STD goes HIGH to indicate the dual tone signal has been detected. When a dual tone signal is detected, INT also becomes active and goes LOW. SM8222A/B TIMING DIAGRAMS Ring Detector and FSK Demodulator 1st Ring L1/L2 101010... 1 Data 2nd Ring RDRC RDET PDWN CDET DOUT OSCOUT pre NIPPON PRECISION CIRCUITS—12 lim tDOSC ina ry tDAQ tDCH 101010...1 Data SM8222A/B Output Mode 0 tDCD DOUT tCDD 90% tr0 DCLK tf0 tPWL DR tf0 lim b6 b7 1 STOP START TIP/RING 0 b0 b1 b2 b3 b4 b5 b6 b7 1 tIDD START DOUT b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 STOP STOP DCLK tPWL pre NIPPON PRECISION CIRCUITS—13 DR ina ry tf0 90% 10% 10% tPWH tr0 tPWL 90% 10% tr0 STOP START 0 b0 b1 b2 b3 b4 b5 b6 START b0 b1 b2 b3 b4 1/fDCLK0 tCRD SM8222A/B Output Mode 1 DCLK 0.7VDD 0.3VDD tf1 N Input Data b7 STOP START b0 DR tDDS tDDH DCLK DATA b7 b0 b1 b2 b3 b4 b5 b6 b7 pre NIPPON PRECISION CIRCUITS—14 lim ina ry tr1 N+1 b1 b2 b3 b4 b5 b6 b7 STOP 1/fDCLK1 N SM8222A/B TYPICAL APPLICATION CIRCUIT VDD Surge Protection L1 430K 22nF (240k) 5% 1% VDD 34k 1% TIP VDD VDD 0.1µF 20% L2 22nF 430K 5% (240k) 1% 34k 1% 53.6k 1% VDD 100nF 499k 5% 5% 200k 150k 5% 5% VDD 100nF 499k 5% 5% 301k 5% All circuit component values are shown for reference only. These values are not guaranteed for mass production specification. pre NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 lim ( ) = when SM8222B 220nF 100nF 20% 20% ina ry 464k 1% RING GS STGT VDD EST 100k 20% 60.4k 1% AGND CAP STD INT RDIN CDET DR RDRC RDET DOUT DCLK MODE OSCIN FSKEN OSCOUT GND PDWN IC NC9811BE 1999.1 NIPPON PRECISION CIRCUITS—15