SM8223A

SM8223A NIPPON PRECISION CIRCUITS INC. FSK Decoder and DTMF Receiver IC OVERVIEW The SM8223A is a FSK (Frequency shift keying) decoder and DTMF (Dual tone multi-frequency) receiver IC. It is fabricated using a CMOS process and features a power-down function for low power dissipation operation. The FSK decoder and DTMF receiver have the same performance characteristics as dedicated ICs that perform the same functions, with the added benefit of an FSK decoder/DTMF receiver auto-select function1 using the telephone tip/ring input signal. It also features a ring (call signal) signal detection circuit, making for easy construction of low power dissipation, high-performance analog telephone-related applications. FEATURES s PINOUT (Top view) s s s s s s s s Both FSK signal caller-ID information services and DTMF signal caller-ID information services supported FSK decoder/DTMF receiver auto-select function Ring (call signal) signal detection circuit built-in Serial I/O Input gain adjustment circuit built-in Power-down mode Single supply operation: 3.0V ± 10% 3.579545MHz external crystal oscillator frequency Molybdenum-gate CMOS process TIP RING GS AGND RDIN RDRC RDET PDWN 1 16 VDD DV DOUT FSK/DTMF IC OSCIN OSCOUT SM8223AP 8 9 GND APPLICATIONS s s s Telephones, fax machines and modems that support caller-ID information services Adapters for caller-ID information service functions Telephones, fax machines and modems that support remote operation functions PINOUT (Unit: µm) RING TIP VDD DV (2810, 3160) ORDERING INFORMATION D e vice SM8223A CF8223A P ackag e 16-pin DIP Chip GS DOUT AGND FSK/DTMF RDIN IC RDRC OSCIN (0, 0) RDET PDWN GND OSCOUT P ad size : 90 µm × 9 0 µm 1. Auto-select function operates if the FSK signal conforms to the Bellcore GR-30-CORE standard. NIPPON PRECISION CIRCUITS—1 S M8223A PACKAGE DIMENSIONS (Unit: mm) 7.49 to 8.13 3.18 3.30 2.54 0.46 1.52 BLOCK DIAGRAM FSK/DTMF Differential Amplifier TIP RING GS FSK Decoder DV Band Pass Filter FSK Decoder Logic DOUT FSK/DTMF Discriminator Logic High Group Filter Dial Tone Filter Low Group Filter DTMF Decoder Logic DTMF Receiver AGND Bias Circuit OSC 0.38 to 1.02 3.68 to 4.32 Ring Detect VDD GND PDWN OSCIN OSCOUT RDIN RDRC NIPPON PRECISION CIRCUITS—2 0.25 19.05 RDET 8.13 to 9.40 6.35 S M8223A PIN DESCRIPTION Number 1 2 3 4 5 6 7 Name TIP RING GS AG N D RDIN RDRC RDET I/O I I O O I I/O O Function Tip input. Connected to the telephone line through a protection circuit Ring input. Connected to the telephone line through a protection circuit Input-stage amplifier gain-select output. Used to adjust the gain of the inputstage amplifier. Analog ground output. Internal reference voltage (V D D / 2) output level Ring detector input. Used for line reversal and ring signal detection. Connected for ring detection of attenuated ring signals. Ring detector RC terminal. Connected to an RC network which sets the ring detector delay time. Ring detector output. R D R C -input Schmitt-trigger buffer output. LOW -level output when ring signal is detected. Pow er-down control input. LOW -level for normal operation. HIGH-level for pow er-down state. In the pow er-down state, pins AG N D , O S C O U T, D O U T, and D V a re HIGH. Ground. Connected to the system ground potential. Cr ystal oscillator output. The crystal oscillator element is connected between this pin and OSCIN. Cr ystal oscillator input. The crystal oscillator element is connected between this pin and OSCOUT. Test input. Tied LOW for normal operation. FSK/DTMF discr iminator output. HIGH-level output when receiving FSK signal, and LOW -level output when receiving DTMF signal. Demodulator output. Demodulated FSK or DTMF signal output. HIGH-level output in pow er-down state. Data trigger output. Data is output on DOUT when this pin goes LOW . Supply P ad dimensions ( µm ) X 1046 638 176 176 176 176 596 Y 2934 2934 2665 1954 1534 492 226 8 9 10 11 12 13 14 15 16 PDW N GND OSCOUT OSCIN IC FSK/D T M F DOUT DV VDD I – O I I O O O – 1063 1634 2053 2634 2634 2634 2634 2211 1612 226 226 226 506 1550 1942 2623 2934 2934 NIPPON PRECISION CIRCUITS—3 S M8223A SPECIFICATIONS Absolute Maximum Ratings GND = 0V P arameter S upply voltage range Input voltage range DC input current Storage temperature range Symbol VDD V IN II N T s tg Rating −0 .5 to 5.0 − 0 .3 to V D D + 0 .3 ± 10 −4 0 to 125 Unit V V mA °C Recommended Operating Conditions GND = 0V Rating P arameter S upply voltage Clock frequency Clock frequency accuracy Operating temperature Symbol VDD fC L K ∆f C Ta Condition min 2 .7 – −0 .1 −2 0 typ – 3.579545 – – max 3.3 – +0.1 85 V MHz % °C Unit DC Electrical Characteristics VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted. Rating P arameter Symbol Condition min S upply current consumption ID D P D W N = 0 V, RDIN = 0 V, R D R C = 0 V, all other inputs open P D W N = V D D , R DIN = 0 V, R D R C = 0 V, all other inputs open – typ – max 4.5 mA Unit Pow er-down state current P D WN, RDIN, R D R C L OW -level input voltage P D WN, RDIN, R D R C H IGH-level input voltage O S C I N L OW -level input voltage OSCIN HIGH-level input voltage D O U T, D V , R D E T , FSK/D T M F L OW level output current D O U T, D V , R D E T , FSK/D T M F H IGHlevel output current P D WN, RDIN input leakage current R D R C o utput leakage current ID P D – – 15 µA V I L1 V I H1 V I L2 V I H2 IO L IO H II N IO F F W h e n external clock input W h e n external clock input – 0 .7V D D – 0.7V D D 2 – −1 – – – – – – – – – 0.3V D D – 0.3V D D – – −0 .8 1 1 V V V V mA mA µA µA NIPPON PRECISION CIRCUITS—4 S M8223A AC Electrical Characteristics FSK decoder VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted. Rating P arameter D etection sensitivity Symbol Condition min Typical application circuit M a r k signal and SPA CE signal are same level. Noise: Random noise from 200Hz to 3400Hz. −4 0 typ −3 7.5 max 0 dBm Unit Noise reduction ratio 20 – – dB DTMF receiver VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted. Rating P arameter D etection frequency deviation Non-detection frequency deviation Typical application circuit Detection sensitivity Non-detection sensitivity Signal level error High-frequency rejection ratio Noise rejection ratio Dial tone rejection ratio 1 . Input signal is up to V D D l evel. Typical application circuit 1 Symbol Condition min ±1.5% ± 2 ±3.5 −3 2.0 – – – – – typ – – – – – 18 12 20 max – – 0.0 −5 0.0 6 – – – Hz % dBm dBm dB dB dB dB Unit Input-stage amplifier Characteristics VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted. Rating P arameter I nput leakage current Input resistance D C open-loop voltage gain Unity gain frequency Load capacitance Load resistance Symbol II N R IN AVOL fC CL RL Condition min – – 30 80 – 50 typ – 1 – – – – max 1 – – – 100 – µA MΩ dB kHz pF kΩ Unit NIPPON PRECISION CIRCUITS—5 S M8223A Timing Characteristics Oscillator VDD = 3.0V ± 0.3V, GND = 0V, Ta = −20 to 85°C unless otherwise noted. Rating P arameter C lock HIGH-level pulsewidth Clock LOW -level pulsewidth Clock rise time Clock fall time Symbol tW H tW L tr tf Condition min 1 10 1 10 – – typ – – – – max – – 30 30 ns ns ns ns Unit FSK decoder VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted. Rating P arameter P ow er-down release time Oscillator start-up time M a r k signal to D V O N time FSK flag setup time FSK flag hold time Input to DOUT delay time D O U T r ise time D O U T fall time DOUT data rate Symbol tD P D tD O S C tD E D tA F tA H tA D D tD r0 tD f0 tD W L / H D V = L OW Condition min – – – – – – – – 1 188 typ 8 5 – – – 1 – – 1200 max – – 3.75 833 (1/1.2kHz) 10 5 20 20 1212 ms ms ms µs ns ms ns ns baud Unit DTMF receiver VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted. Rating P arameter D O U T, D V rise time D O U T, D V fall time Signal detection time Received signal non-detection time P ause detection time P ause non-detection time D V o utput data delay time Pow er-down release time Oscillator start-up time DOUT data rate D T M F fl ag setup time Symbol tD r0 tD f0 tR E tR E tPA tP R tB D D tD P D tD O S C tD W L / H tA F DV DV DV DV Condition min – – – 20 – 20 – – – 1188 – typ – – – – – – – 8 5 1200 – max 20 20 45 – 25 – 5 – – 1212 833 (1/1.2kHz) ns ns ms ms ms ms ms ms ms baud µs Unit NIPPON PRECISION CIRCUITS—6 S M8223A OSCIN input timing (when external input) tWL VDD tWH OSCIN VSS tf tr FSK receive timing (1) 1st Ring Tip/Ring Ch. seizure Mark Data packet 1010101... 111... Data 2nd Ring RDET tDED DV tAF FSK/DTMF tHF tADD DOUT Data Data output has no Ch.seizure signal. tDPD PDWN tDOSC OSCOUT FSK receive timing (2) Start bit LSB MSB Stop bit Tip/Ring b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 tADD DOUT b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 NIPPON PRECISION CIRCUITS—7 S M8223A DTMF receive timing (1) tPR Tip/Ring DTMF Data #1 #1 tPA tRE DTMF Data #2 tRE DV tAF FSK/DTMF tBDD DOUT Data #1 Data #2 tDPD PDWN tDOSC OSCOUT DTMF receive timing (2) DV tBDD DOUT 0 Q0 Q1 Q2 Q3 S0 S1 S2 S3 1 Start bit DTMF data Checksum (2'mod16) Stop bit (FSK/DTMF) DOUT output timing tDWL DOUT tDWH 90% tDf0 tDr0 10% NIPPON PRECISION CIRCUITS—8 S M8223A FUNCTIONAL DESCRIPTION Ring Signal Detector The telephone tip and ring signals pass through a protection circuit and are input to a resistor, capacitor and diode bridge network, shown in figure 1. C2 TIP R3 a D1 R2 R4 R1 b RDIN RDRC RDET C2 RING R3 Db C1 c d Figure 1. Ring signal detector circuit The diode bridge full-wave rectified output signal (point a) is reduced in level by a resistor voltage divider comprising R1 and R2 (point b), and then input on RDIN. When the ring signal input on RDIN exceeds the Schmitt buffer trigger voltage (0.7VDD), the output switches the open-drain RDRC pin. The signal at RDRC (point c) drives a time-constant circuit comprised by resistor R4 and capacitor C1 connected to the input of a second Schmitt buffer to generate the detector signal output on RDET (point d). Thus, RDET goes LOW when the ring or tip signal exceeds the level set by the resistor voltage divider. NIPPON PRECISION CIRCUITS—9 S M8223A VRIG VDD VSS 0.7VDD 0.3VDD Point a Signal VRIG VDD VSS VDD VSS VDD VSS 0.7VDD 0.3VDD Point b Signal 0.7VDD 0.3VDD Point c Signal 0.7VDD 0.3VDD Point d Signal Figure 2. Ring signal detector circuit waveform transitions The voltage divider level and RC time constant are given by the following equations, respectively. R1 0.7 V DD = -------------------------------- ⋅ V RIG R1 + R2 + R3 t C 1 R 4 = ----------------------------------- V DD  In  -------------------------  V DD – V T  where t is the guard time, and the trigger level satisfies the expression 0.3VDD ≤ VT ≤ 0.7VDD. NIPPON PRECISION CIRCUITS—10 S M8223A Input Differential Amplifier The SM8223A uses an input differential amplifier for input gain adjustment of the tip/ring signal input to the FSK detector or DTMF receiver. Differential input configuration and single-ended input configuration circuits are shown in figure 3. A bypass capacitor should be connected between GND and AGND in both circuit configurations. C1 C1 R1 R1 R2 R3 R4 C TIP RING GS C1 R1 R2 TIP RING GS AGND Differntial Input C AGND Single-Ended Input Figure 3. Input circuits The gain for single-ended configurations is given by the following equation. R2 A V = ----R1 The gain for differential configurations is given by the following equation, R2 R2 R4 A V = ----- where R 3 = -----------------R1 R2 + R4 and the input impedance is given by the following equation. 2 12 Z i = 2 R 1 +  ----------   ωC  1 FSK/DTMF Auto-discriminator The SM8223A examines the tip/ring input signal and determines the nature of the signal, FSK or DTMF, and invokes the corresponding circuits, FSK decoder or DTMF receiver, respectively. It determines whether the input signal is an FSK signal or DTMF signal by the presence or otherwise of the channel seizure information in the FSK signal header. This function automatically discriminates between the input signals if the FSK signal conforms to the Bellcore GR-30-CORE standard. NIPPON PRECISION CIRCUITS—11 S M8223A FSK Demodulator When an FSK signal is received, the FSK/DTMF signal discriminator circuit sets the FSK/DTMF pin HIGH and connects the input signal to the FSK demodulator circuit. Demodulated data is output on DOUT with the format shown in figure 4. The FSK signal conforms to the following Bellcore standard. Table 1. FSK signal P arameter Modulation type Logic “1” data (mark) Logic “0” data (space) Signal level (mark) Signal level (space) Data transfer rate Description Continuous-phase binar y frequency-shiftkeying 1200 ± 12 Hz 2200 ± 22 Hz −32 to −1 2 d B m −36 to −1 2 d B m 1200 ± 12 baud Start bit LSB MSB Stop bit FSK signal b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 DOUT b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 Figure 4. FSK signal to DOUT output DTMF Demodulator When a DTMF signal is received, the FSK/DTMF signal discriminator circuit sets the FSK/DTMF pin LOW and connects the input signal to the DTMF demodulator circuit. The DTMF signal is comprised by a high-group frequency and a low-group frequency which, in combination, represent a point in the DTMF matrix. Table 2. DTMF matrix L o w gro u p 697Hz 770Hz 852Hz 941Hz High gro u p 1209Hz 1 4 7 * 1336Hz 2 5 8 0 1477Hz 3 6 9 # 1633Hz A B C D Table 3. DTMF signal output (DOUT) DTMF Matrix input 1 2 3 4 5 6 7 8 9 0 D0 Q0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D1 Q1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D2 Q2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D3 Q3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D4 S0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Checksum D5 S1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D6 S2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D7 S3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 The DTMF receiver demodulates the received DTMF signal and outputs data bits Q0 to Q3 and a 4bit (2-mod-16) checksum S0 to S3 in serial format on DOUT. * # A B C D NIPPON PRECISION CIRCUITS—12 S M8223A DTMF signal DTMF DATA DOUT 0 Q0 Q1 Q2 Q3 S0 S1 S2 S3 1 Start bit DTMF data (LSB first) Checksum (2'mod16) (LSB first) Stop bit Figure 5. DTMF signal to DOUT output The DTMF receiver determines whether the received data (DTMF signal) is valid after an interval of tREC ≥ 40ms stable reception. If valid, DV goes LOW and data is output on DOUT. If DTMF data is not detected after an interval tSPA ≥ 20ms, a data pause is activated and the next DTMF signal is in a wait state (see timing diagrams in AC Electrical Characteristics). The SM8223A DTMF receiver can be used as a general-purpose DTMF receiver without the need for the external time constant circuit, in which case the resistor/capacitor/diode network can be omitted. NIPPON PRECISION CIRCUITS—13 S M8223A TYPICAL APPLICATION CIRCUIT D1 C1 TIP D1 R3 VS D1 C1 RING D1 C3 R6 D2 D2 R7 R9 D1 RDET OSCOUT PDWN GND X'tal R1 R2 C2 RDIN RDRC R4 R5 GS AGND DOUT FSK/ DTMF IC OSCIN R1 R2 TIP RING VDD DV C5 C3 R6 D2 D2 R8 C4 Symbol R1 R2 R3 R4 R5 1 1 1 1 1 Rating 240 34 464 53.6 60.4 1N4003 22 0.1 430 270 27 270 22 470 1N4004 0.1 – 3.579545 Unit kΩ kΩ kΩ kΩ kΩ – nF µF kΩ kΩ kΩ kΩ nF nF – µF – MHz D1 C1 C2 R6 R7 R8 R9 2 2 2 2 C3 C4 2 D2 C5 VS X’tal 1. Refer to the Input Differential Amplifier. 2. Refer to the Ring Signal Detector. NIPPON PRECISION CIRCUITS—14 S M8223A NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9909AE 2000.02 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—15