SM8577BS

SM8577B NIPPON PRECISION CIRCUITS INC. Real-time Clock IC OVERVIEW The SM8577B is a CMOS serial-interface type realtime clock IC that operates at 32.768 kHz. It employs a 3-line serial interface to transfer time and date data. It incorporates a supply-voltage detect function to determine data validity/invalidity. It features an output interrupt with 32 kHz or 1 Hz output frequency. It is available in 8-pin SOPs. PINOUT CE DATA CLK FOUT 1 8 VDD XTN XT VSS 8577B FEATURES s s s s s 4 5 s s s s s 2.5 to 5.5 V operating voltage range 1.0 µA at 3.0 V (typ) current consumption 3-line serial interface 1.7 ± 0.3 V supply voltage detection threshold Timer counters for second, minute, hour, day, day of the week, month, and year Automatic leap-year calendar adjustment 32.768 kHz and 1 Hz output interrupt selectable Crystal oscillator circuit built-in (CD built-in) 24-hour time mode 8-pin SOP PACKAGE DIMENSIONS Unit: mm 8-pin SOP 0.15− 0.05 + 0.10 4.4 0.2 6.2 0.3 5.2 0.3 0 to 10∞ ORDERING INFOMATION Device SM8577BS Package 8pin SOP 0.4 0.1 NIPPON PRECISION CIRCUITS—1 0.05 0.05 1.5 0.1 1.27 4.4 0.2 S M8577B BLOCK DIAGRAM VDD VSS XT XTN OSC Divider Timer Counter FOUT Output Controller Voltage Detect Shift Register DATA CLK CE I/O Controller Controll Circuit PIN DESCRIPTION Number 1 2 3 Name CE DATA CLK I/O I I/O I Description Chip enable. With pull-down resistor built-in. HIGH: Enable LOW: DATA goes high impedance; input on CLK and DATA stops; and the TM bit is cleared. Data read and write input/output Serial clock input. Data is input (write mode) and output (read mode) on the rising edge of CLK. Frequency output (controlled by the 4th data bit of the ‘week’ data, FSEL). 1 Hz output when FSEL is 0, and 32.768 kHz output when FSEL is 1. In 1 Hz output mode, the 1 Hz signal is synchronized to the internal 1 second signal. FOUT output is not affected by the CE signal. Ground Crystal oscillator element connection pin Crystal oscillator element connection pin. Oscillator capacitor CD is built-in. Supply voltage. Connect a ≥ 0.1 µF capacitor between VDD and VSS. 4 FOUT O 5 6 7 8 VSS XT XTN VDD – I O – NIPPON PRECISION CIRCUITS—2 S M8577B SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V P arameter Supply voltage range Input voltage range Output voltage range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol VDD V IN VO UT Tstg PD Tsld tsld Condition Rating −0.3 to 7.0 V S S − 0.3 to V D D + 0.3 V S S − 0.3 to V D D + 0.3 −55 to 125 150 255 10 Unit V V V °C mW °C s Recommended Operating Conditions VSS = 0 V P arameter Supply voltage range Operating temperature range Symbol VDD Topr Condition Rating 2.5 to 5.5 −40 to 85 Unit V °C Oscillator Characteristics VSS = 0 V, Ta = 25 °C, CG = 12 pF, Seiko Epson C-002SH crystal (CI = 30 kΩ, CL = 6 pF) unless otherwise noted Rating P arameter Oscillator start time Oscillator start voltage Oscillator stop voltage Frequency voltage characteristic Frequency accuracy Output capacitance Symbol tSTA VSTA V STO f/V ε CD V D D = 2.0 to 5.5 V V D D = 5.0 V V D D = 5.0 V Condition min V D D = 2.5 V – 1.5 – −2 −10 – typ – – – – – 12 max 3 – 1.5 +2 +10 – s V V ppm/V ppm pF Unit NIPPON PRECISION CIRCUITS—3 S M8577B DC Electrical Characteristics VSS = 0 V, VDD = 5.0 V ± 10%, Ta = −40 to 85 °C unless otherwise noted Rating P arameter Symbol ID D1 ID D2 HIGH-level input voltage LOW-level input voltage Input resistance Input OFF leakage current V IH V IL R IN Ileak VO H1 VO H2 LOW-level output voltage VOL1 VOL2 Output leakage current Supply voltage detect threshold voltage IO ZH IO ZL V D ET Condition min Current consumption V D D = 5.0 V V D D = 3.0 V CE, CLK, DATA CE, CLK, DATA CE: V IN = 5.0 V CLK: V IN = V D D or V S S CE: V IN = V S S V D D = 5.0 V V D D = 3.0 V V D D = 5.0 V V D D = 3.0 V DATA, FOUT: IO H = −1.0 mA DATA, FOUT: IO L = 1.0 mA – CE = V S S – 0.8VD D – – – 4.5 2.0 – – −1.0 −1.0 1.4 typ 1.5 1.0 – – – – – – – – – – 1.7 max 3.0 2.0 – 0.2VD D 800 0.5 – – V S S + 0.5 V S S + 0.8 1.0 1.0 2.0 µA µA V V kΩ µA V V V V µA µA V Unit HIGH-level output voltage DATA, FOUT: VO UT = 5.5 V DATA, FOUT: VO UT = 0 V NIPPON PRECISION CIRCUITS—4 S M8577B AC Characteristics VDD = 5 V ± 10%, VSS = 0 V, Ta = −40 to 85 °C, CL = 50 pF unless otherwise noted Rating P arameter CLK clock period CLK LOW-level pulsewidth CLK HIGH-level pulsewidth CE setup time CE hold time CE enable time Write data setup time Write data hold time DATA output delay time DATA output floating time Clock rise time Clock fall time FOUT rise time FOUT fall time FOUT duty cycle Wait time Symbol tC LK tCLKL tC LKH tC ES tC EH tC E tS D tH D tDATD tD Z tr1 tf1 tr2 tf2 Duty tR CV C L = 30 pF C L = 30 pF C L = 30 pF, 32 kHz output See measurement circuit. Condition min 0.75 0.375 0.375 0.375 0.375 – 0.1 0.1 – – – – – – 40 0.95 max – – – – – – – – – – – – – – – – min 7800 3900 3900 3900 – 0.9 – – 0.2 0.1 50 50 100 100 60 – µs µs µs µs µs s µs µs µs µs ns ns ns ns % µs Unit VDD = 3 V ± 10%, VSS = 0 V, Ta = −40 to 85 °C, CL = 50 pF unless otherwise noted Rating P arameter CLK clock period CLK LOW-level pulsewidth CLK HIGH-level pulsewidth CE setup time CE hold time CE enable time Write data setup time Write data hold time DATA output delay time DATA output floating time Clock rise time Clock fall time FOUT rise time FOUT fall time FOUT duty cycle Wait time Symbol tC LK tCLKL tC LKH tC ES tC EH tC E tS D tH D tDATD tD Z tr1 tf1 tr2 tf2 Duty tR CV C L = 30 pF C L = 30 pF C L = 30 pF, 32 kHz output See measurement circuit. Condition min 1.5 0.75 0.75 0.75 0.75 – 0.2 0.1 – – – – – – 40 1.9 max – – – – – – – – – – – – – – – – min 7800 3900 3900 3900 – 0.9 – – 0.4 0.2 100 100 200 200 60 – µs µs µs µs µs s µs µs µs µs ns ns ns ns % µs Unit NIPPON PRECISION CIRCUITS—5 S M8577B Measurement Circuit SW2 10kΩ VDD DATA 10kΩ SW1 VSS CE P.G 50pF Output DATA Output Floating Timing tDHZ CE 50% DATE 90% tDLZ CE 50% DATA 10% NIPPON PRECISION CIRCUITS—6 S M8577B Timing Diagrams Data read tCE CE tCES CLK tCLKH tCLKL DATA tDATD tf1 tr1 tDZ tCLK tCEH tRCV Data write tCE CE tCES CLK tCLKH tCLKL tHD tCLK tr1 tf1 tCEH tRCV tsD DATA FOUT output tr2 90% tH 50% FOUT 10% tr2 t H Duty= tt X 100(%) Note that the 1 Hz and 32 kHz oscillators are not synchronized to each other, so switching between 1 Hz and 32 kHz output temporarily shortens the duty cycle. Accordingly, a wait time (≥ output frequency period) should be incorporated when switching during normal operation. NIPPON PRECISION CIRCUITS—7 S M8577B FUNCTIONAL DESCRIPTION Timer Data Configuration Counter data is stored in BCD format. The IC performs long/short month and leap-year adjustment automatically. Leap-year adjustment occurs: • when the decade digit is odd and the year digit is a 2 or 6, and MSB • when the decade digit is even and the year digit is a 0, 4 or 8. The time display is 24-hour mode. All data is written and read with the LSB first. LSB s40 s20 s10 s8 s4 s2 s1 Second ( 0 to 59 ) FDT Minute ( 0 to 59 ) ∗ mi40 mi20 mi10 mi8 mi4 mi2 mi1 Hour ( 0 to 23 ) ∗ ∗ h20 h10 h8 h4 h2 h1 Week ( 1 to 7 ) FSEL W4 W2 W1 Day ( 1 to 31 ) ∗ ∗ d20 d10 d8 d4 d2 d1 Month ( 1 to 12 ) TM ∗ ∗ mo10 mo8 mo4 mo2 mo1 Year ( 0 to 99 ) y80 y40 y20 y10 y8 y4 y2 y1 * bits are don’t care write bits. FDT is the supply voltage detect bit. FDT is set to 1 when the voltage between VDD and VSS falls below 1.7 ± 0.3 V. It is reset to 0 for data reads longer than 56 bits. Note that the FDT bit is not reset to 0 for data reads of 55 bits or less. The read/write data bits should initially be set to 0. After the supply voltage is first applied, the FDT bit should also be set to 0. FSEL is the FOUT output frequency switch control bit. 1 Hz output is selected when FSEL is 0, and 32 kHz output is selected when FSEL is 1. After power is first applied, 1 Hz default mode is selected. TM is the factory test bit. It should be set to 0 for normal use. NIPPON PRECISION CIRCUITS—8 S M8577B Data Read CE 1 2 3 8 9 10 11 58 59 60 60+n CLK Output data not change DATA Don't Care Control Bits Data Input Mode When CE is HIGH, data read mode starts from the first rising edge of CLK for which DATA is LOW. Valid data is then output on DATA from the 9th rising edge of CLK. Time and date data is loaded into the shift register on the 8th falling edge of CLK and then output on DATA in sync with the rising edge of CLK, starting with the seconds’ digit LSB. Data is loaded and shifted in the sequence second, minute, hour, week, day, and month. The output data is valid for the first 60 rising edges of CLK. Output data does not change after the 60th rising edge, even if clock input continues. Within the 60 cycles of valid data output, partial data output can be obtained by taking CE LOW after the s1 s2 s4 y20 y40 y80 Second Year Data Output Mode corresponding number of cycles. For example, if only the ‘second’ to ‘week’ data output is required, then that data only is output if CE goes LOW after 36 clock cycles. For continuous data reads, a wait time (tRCV) is required before the next data cycle after CE goes LOW. Note that if a timer counter update operation (a 1 s carry) occurs during a data read cycle, the data in the shift register is not updated and, as a result, the output data contains an error of −1 s. The data read cycle should be completed within tCE ≤ 0.9 s. Data Write CE 1 2 3 8 9 10 11 58 59 60 60+n CLK DATA Dont Care ′ Control Bits Data Input Mode s1 s2 s4 y20 y40 y80 Second Year Data Input Mode NIPPON PRECISION CIRCUITS—9 S M8577B When CE is HIGH, data write mode starts from the first rising edge of CLK for which DATA is HIGH. Valid data is then input on DATA from the 9th rising edge of CLK. Time and date data is loaded into the shift register in sync with the rising edge of CLK, starting with the seconds’ digit LSB. Data is loaded and shifted in the sequence second, minute, hour, week, day, and month. After 60 rising edges of CLK, the shift register contents are then transferred to the timer counters. Note that a data write cycle must contain 60 bits of input data. If CE goes LOW before 60 bits are input, the input data is invalid. If the input data exceeds 60 bits, data from the 61st bit is ignored (the first 60 bits remain valid). During a data write cycle, timer counter operation stops on the first falling edge of CLK, and the 1 Hz to 128 Hz frequency divider step counters are reset. The 1 s counter increment signal is stopped and does not restart until CE goes LOW. The divider step counters are reset during the interval between the first falling edge of CLK and the 2nd rising edge of CLK. The data write cycle should be completed within tCE ≤ 0.9 s. If a data read cycle occurs immediately after a data write cycle, a wait time (tRCV) is required after CE goes LOW. Note that activating a read cycle when no valid data is present will cause incorrect operation. All bits must be valid data bits. Supply Voltage Detection The supply voltage detector tests the level of the supply voltage once every 0.5 seconds. If the supply voltage falls below the detector threshold, the FDT bit is set to 1. The FDT bit is reset to 0 after a data read cycle that contains at least 56 data bits. The FDT bit is not reset for data read cycles of 55 bits or less. VDD VDET 0.5 second 0.5 second Detected Pulse CE (READ MODE) FDT bit NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9617AE 1997.04 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—10