SM8578BV

SM8578BV Real-time Clock IC OVERVIEW The SM8578BV is a serial interface, real-time clock IC that uses a 32.768 kHz crystal oscillator for its reference timing. It comprises second-counter to year-counter clock and calendar circuits that feature automatic leap-year adjustment, alarm and timer interrupt functions, as well as oscillator stop, timer reloading, and other detection functions. Data is transferred to and from an external controller using a 3-wire serial interface. It is available in compact 8-pin VSOP packages, making it ideal for use in all types of portable, hand-held equipment. FEATURES I I PINOUT (Top view) I I I I I I I I I 1.6 to 5.5V wide operating voltage range 0.5µA (typ.) current consumption (VDD = 3.0V, CE = Low) 3-wire serial interface control Day, day-of-week, hour, and minute alarm interrupt function 1/4096 seconds to 255 minutes presettable interval timer interrupt function Time update detection function Abnormal oscillation detection function Automatic leap-year adjustment function (Western and Japanese calendars) Oscillator capacitor CD built-in Molybdenum-gate CMOS process Miniature 8-pin VSOP package INTN XTN XT VSS 1 8 VDD DATA CLK 4 5 CE ORDERING INFORMATION, Device SM8578BV Package 8-pin VSOP PACKAGE DIMENSIONS (Unit: mm) 0 to 10° 4.4 ± 0.2 6.4 ± 0.3 0.585typ 1.15 ± 0.05 3.12 ± 0.3 + 0.1 0.05 0.15 − 0.22 ± 0.1 NIPPON PRECISION CIRCUITS INC.—1 0.05 ± 0.05 0.65 1.30MAX 0.5 ± 0.2 SM8578BV BLOCK DIAGRAM VDD VSS Control Line CD XTN OSC XT Divider Clock and Calendar Register Divider and Timer Counter OSC Detect Control Register INTN Interrupt and FOUT Controller Alarm Register Shift Register CLK DATA CE Input Controller Control Circuit Internal Bus PIN DESCRIPTION Number 1 2 3 4 5 6 Name INTN XTN XT VSS CE CLK I/O O O I – I I Function Timer interrupt/alarm interrupt output, determined by internal mode setting, or frequency output, with frequency value given in the frequency set register (N-channel open-drain output) Oscillator output. Oscillator capacitor CD built-in. Oscillator input Negative supply voltage connection Chip enable input with pull-down resistance built-in. Internal registers can be accessed when CE is HIGH. Serial data transfer clock input. In write mode, data is read in from DATA on the rising edge of CLK. In read mode, data is read out from DATA on the rising edge of CLK. Serial data transfer data input/output. When CE goes HIGH, the first four bits of write data determine the operating mode (read mode/write mode). Positive supply voltage connection. A 0.1µF bypass capacitor should be connected between VDD and VSS. 7 8 DATA VDD I/O – NIPPON PRECISION CIRCUITS INC.—2 SM8578BV SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Supply voltage range Input voltage range Output voltage range 1 Output voltage range 2 Power dissipation Storage temperature range Symbol VDD VIN VOUT1 VOUT2 PD TSTG Input pins INTN DATA Condition Rating −0.3 to +7.0 VSS − 0.3 to VDD + 0.3 VSS − 0.3 to +8.0 VSS − 0.3 to VDD + 0.3 150 −55 to +125 Unit V V V V mW °C Recommended Operating Conditions VSS = 0V Parameter Supply voltage range Operating temperature range Symbol VDD Topr Condition Rating 1.6 to 5.5 −40 to +85 Unit V °C DC Characteristics VSS = 0V, VDD = 1.6 to 5.5V, CG = 10pF, Ta = −40 to +85°C unless otherwise noted. Rating Parameter Current consumption 1 Current consumption 2 HIGH-level input voltage LOW-level input voltage Input leakage current Input resistance 1 Input resistance 2 Symbol IDD1 IDD2 VIH VIL ILEAK RDWN1 RDWN2 VOH1 Output voltage 1 VOH2 VOL1 VOL2 Output voltage 2 VOL3 VOL4 Output leakage current IOZ VIN = VDD or VSS, CE, CLK pins VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VIN = VDD, CE pin IOH = −1mA, DATA pin IOL = 1mA, DATA pin IOL = 1mA, INTN pin VDD = 5V VDD = 3V Condition min CE = VSS, DATA, INTN = VDD – – 0.8VDD 0 −0.5 75 150 4.5 2.0 – – – – −0.5 typ 1.0 0.5 – – – 150 300 – – – – – – – max 2.0 1.0 VDD 0.2VDD 0.5 300 600 5.0 3.0 VSS + 0.5 VSS + 0.8 VSS + 0.25 VSS + 0.4 0.5 µA µA V V µA kΩ kΩ V V V V V V µA Unit CE, CLK, DATA pins VOUT = VDD or VSS, DATA, INTN pins NIPPON PRECISION CIRCUITS INC.—3 SM8578BV Oscillator Characteristics Ta = 25°C, CG = 10pF, X’tal = NPC reference crystal (CI = 30kΩ, CL = 6pF) unless otherwise noted. Rating Parameter Oscillator startup time Oscillator stop voltage Frequency voltage characteristic Frequency accuracy Output capacitance Symbol TSTA VSTO f/V εIC CD VDD = 1.6 to 5.5V VDD = 5.0V VDD = 5.0V VDD = 1.6V Condition min – – −2 −10 – typ – – – – 15 max 5.0 1.5 2 10 – s V ppm/V ppm pF Unit AC Characteristics VSS = 0V, Ta = −40 to +85°C unless otherwise noted. Parameter CLK clock cycle CLK HIGH-level pulsewidth CLK LOW-level pulsewidth CE setup time CE hold time CE recovery time CLK hold time Write data setup time Write data hold time Read data output delay time Output disable delay time Input rise and fall time Abnormal oscillation detection time Symbol tCLK tWH tWL tCS tCH tCR tCKH tDS tDH tRD tRZ tRF tOSC CL = 50pF CL = 50pF RL = 10kΩ Condition min 600 300 300 150 200 300 50 50 50 – – – 10 VDD = 5.0V ± 10% typ – – – – – – – – – – – – – max – – – – – – – – – 200 100 20 – min 1200 600 600 300 400 600 100 100 100 – – – 10 VDD = 3.0V ± 10% typ – – – – – – – – – – – – – max – – – – – – – – – 400 200 40 – ns ns ns ns ns ns ns ns ns ns ns ns ms Unit NIPPON PRECISION CIRCUITS INC.—4 SM8578BV Timing Diagrams tCLK tCS 50% tWL tWH tCH tCKH CLK tCR CE 50% Data write CLK 50% t DH DATA 50% t DS CE 50% t CS Data read t RF t RF 90% CLK 50% t RD 10% 90% DATA 50% 10% t RZ Hi−Z CE 50% NIPPON PRECISION CIRCUITS INC.—5 SM8578BV FUNCTIONAL DESCRIPTION Register Table Address 0 1 2 3 4 5 6 7 8 9 A B C D E F Function Second Minute Hour Day-of-week Day Month Year Minute alarm Hour alarm Day-of-week alarm Day alarm Frequency Fixed cycle Fixed-cycle counter Control 1 Control 2 Bit7 FOS fr fr fr fr fr 80 AE AE AE AE FE TE 128 * * Bit6 40 40 * 6 * * 40 40 * 6 * * * 64 * TEST Bit5 20 20 20 5 20 * 20 20 20 5 20 FD4 TD1 32 * * Bit4 10 10 10 4 10 10 10 10 10 4 10 FD3 TD0 16 TI/TP RESET Bit3 8 8 8 3 8 8 8 8 8 3 8 * * 8 AF HOLD Bit2 4 4 4 2 4 4 4 4 4 2 4 FD2 * 4 TF * Bit1 2 2 2 1 2 2 2 2 2 1 2 FD1 * 2 AIE * Bit0 1 1 1 0 1 1 1 1 1 0 1 FD0 * 1 TIE * Read Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Write Yes Excl. bit 7 Excl. bit 7 Excl. bit 7 Excl. bit 7 Excl. bit 7 Yes Yes Yes Yes Yes Yes Yes Yes Yes*1 Yes *1. The AF and TF bits have “0” only valid write data values. Note 1. When power is applied, all register values are undefined, hence they must be initialized. Note 2. When Register D is read, the previously preset data value written to the register is read. NIPPON PRECISION CIRCUITS INC.—6 SM8578BV Clock and Calendar Registers (Registers 0 to 6) I I I I Data is in BCD format. For example, register 0 data “0101 1001” represents the value 59 seconds. Also, “*”entries in the register table represent read/write locations that can be used as RAM. Clock timing is in 24-hour mode. Year register and leap year: The year register represents years as 2 digits, with 00 following year 99. Leap years are automatically identified for years up to 2099. Day-of-week register: The day-of-week register is a 7-bit register (bits 0 to 6) with valid values shown in the following table. Note that a register setting with a multiple number of “1” bits is invalid. Bit6 0 0 0 0 0 0 1 Bit5 0 0 0 0 0 1 0 Bit4 0 0 0 0 1 0 0 Bit3 0 0 0 1 0 0 0 Bit2 0 0 1 0 0 0 0 Bit1 0 1 0 0 0 0 0 Bit0 1 0 0 0 0 0 0 Day-of-week Sunday Monday Tuesday Wednesday Thursday Friday Saturday I I FOS (Abnormal Oscillation Detection Bit) This flag reports oscillation abnormalities during normal operation, such as may occur when the supply voltage falls too low, for example. It is set to “1” to indicate abnormal oscillation, and maintains this value until a “0” bit is written. It is not affected by the function of any other bits. fr (Read Flags) When CE is HIGH, these flags are set to “1” when the 1s seconds digit is incremented. They are set to “0” when CE goes LOW. This makes it possible to determine whether the 1s seconds digit has been incremented during a clock register read-out operation (when CE is HIGH). If the fr bits are set to “1”, all the clock timing registers should be read again. The seconds and year registers do not have fr flags. Instead, bits 6 and 5 in the seconds register and bits 7 and 6 in the year register are logically-Ored with data “1” (example: year register 00101001 → 11101001). When CE goes LOW, the register values are restored (example: year register 11101001 → 00101001). NIPPON PRECISION CIRCUITS INC.—7 SM8578BV Alarm Registers (Registers 7 to A) I I I I I I These registers contain the alarm interrupt time setting. When the alarm matches the clock registers, the INTN output goes LOW (if the alarm interrupt enable AIE bit is set to 1). The alarm can be set for day-of-week, day, hour and minute. Bit 7 of each of the alarm registers is an enable alarm AE bit. These bits can be used to implement repetitive alarms, such as for every hour or every day. The day-of-week alarm can optionally be set for multiple alarms. Correct alarm output may not occur if the only alarm setting is a day-of-week alarm. When the AE bit is set to 0, the alarm registers are compared with the corresponding clock registers. When set to “1”, the data is ignored as don’t care bits and is always deemed to match. When the AIE bit in register E is set to “0”, output on pin INTN is disabled. The TIE and FE bits must be set to “1” and the AIE bit must be set to “0” to enable alarm interrupts. Day-of-week alarm bit relationship. Bit Day-of-week Bit6 Saturday Bit5 Friday Bit4 Thursday Bit3 Wednesday Bit2 Tuesday Bit1 Monday Bit0 Sunday Timer Registers (Registers C to E) I I I I I I These registers control the 8-bit presettable down-counters used for timer interrupts. The counter source clock is assigned by register C, and the counter frequency divider is assigned by register D. When the timer count register counts down to zero, with source clock cycle timing, the INTN output goes LOW (if the timer interrupt enable TIE bit is set to “1”). When the TI/TP bit is set to “1”, the fixed-cycle counter register data is reloaded and the count down starts again. Accordingly, this bit can be used to implement an interval timer (periodic mode). When the TIE bit in register E is set to “0”, output on INTN is disabled. The TI/TP, FE, AIE, and TIE bits must be set for normal timer operation (with the FE and AIE bits set to “0”). When data is written to register D, the presettable down counters are updated. The data written to register D is maintained until a subsequent data write is performed, hence this register can be used as RAM, similar to the “*”- entries in the register table, when timer interrupt mode is not used (when TIE is “0”). When the TE bit is set to “0”, the counter loads the fixed-cycle counter contents and the count stops. When the TE bit is set to “1”, the count starts. Note that when the TE bit is set to “0”, fixed-cycle interrupts from output INTN are not generated even when the fixed-cycle counter (register D) is loaded with zero data. TD1 0 0 1 1 TD0 0 1 0 1 Source clock 4096Hz 64Hz 1Hz 1/60Hz NIPPON PRECISION CIRCUITS INC.—8 SM8578BV Frequency Setting Register (Register B) I I This register contains the arbitrary frequency setting for output on INTN. The FD4 and FD3 bits set the frequency divider source clock, and the FD2 to FD0 bits set the frequency divider ratio of the source clock (output frequency = source clock frequency × frequency divider ratio). The FE bit must be set to “1” to enable frequency output on INTN, with frequency given by the frequency set register (with the AIE and TIE bits set to “0”). When the FE bit is set to “0”, the output is disabled and is high impedance (Hi-Z). FD4 0 0 1 1 FD3 0 1 0 1 Source clock 32768Hz 1024Hz 32Hz 1Hz FD2 0 0 0 0 1 1 1 1 FD1 0 0 1 1 0 0 1 1 FD0 0 1 0 1 0 1 0 1 Frequency divider ratio 1/1 1/2 1/3 1/6 1/5 1/10 1/15 1/30 Control Register 1 (Register E) This register controls alarm interrupts and timer interrupts. Address E I Bit7 * Bit6 * Bit5 * Bit4 TI/TP Bit3 AF Bit2 TF Bit1 AIE Bit0 TIE TI/TP bit: Interrupt Signal Output Mode Select. Interrupt/Periodic This selects the timer interrupt signal output mode (with the FE and AIE bits set to “0”). TI/TP 0 INTN goes LOW immediately when a timer interrupt occurs. INTN remains LOW until the TF bit is set to “0” (with TIE = “1”). 1 INTN goes LOW immediately when a timer interrupt occurs (with TIE = “1”), the TF bit is set to “1”, and then INTN becomes high impedance until “0” data is written to the TF bit. Mode I I AF, TF bits: Alarm Flag, Timer Flag The AF bit is set to “1” when an alarm occurs, and the TF bit is set to “1” when the timer is zero. The data bits are maintained until “0” data is written to both bits. Note that “1” data cannot be written to both bits. AIE, TIE bits: Alarm, Timer Interrupt Enable These bits determine the output on INTN when alarm or timer interrupt events occur. AIE is the alarm interrupt enable flag, and TIE is the timer interrupt enable flag. The alarm or timer interrupt is enabled when the corresponding enable bit is set to “1” (both interrupts are output if both bits are set to “1”, so setting both bits to “1” should be avoided). NIPPON PRECISION CIRCUITS INC.—9 SM8578BV Control Register 2 (Register F) This register controls the clock timing frequency divider. Address F I Bit7 * Bit6 TEST Bit5 * Bit4 RESET Bit3 HOLD Bit2 * Bit1 * Bit0 * I I I TEST bit: NPC Test Bit This bit should be set to “0” when power is applied and when writing to register F. RESET bit When this bit is set to “1”, the 2kHz to 1Hz frequency divider counters are reset and clock timing stops. After “1” data is written, test mode is cancelled by writing “0” data or by setting the CE input LOW. It is not affected by the state of any other bits. HOLD bit When this bit is set to “1”, the seconds digit increment operation is disabled. However, if an increment operation occurs when this bit is “1” and the bit is subsequently set to “0” within 1 second, the automatic correction function forces a 1-second correction. Therefore, it is recommended that the HOLD bit should be used for less than 1 second. Functional operation table The function of the RESET and HOLD bits is shown in the following table. Bit RESET 0 0 1 1 HOLD 0 1 0 1 Clock timing Operating *1 Function Timer interrupt output Operating *2 *3 *3 Alarm interrupt output Operating Stopped Stopped Stopped Arbitrary frequency output Operating Operating *4 *4 Stopped Stopped *1. The automatic correction function operates if the HOLD bit is set for less than 1 second. *2. Normal operation for source clocks other than 1/60Hz (1 minute). *3. Normal operation for 4096Hz source clock only. *4. Normal operation for 32768Hz source clock only. NIPPON PRECISION CIRCUITS INC.—10 SM8578BV INTERRUPT HANDLING Alarm Interrupt I I If AIE = 1 when the alarm occurs, output INTN goes LOW. If AIE = 0, INTN is in high impedance state. The alarm interrupt is output when the 10s seconds digit carries over to the minutes digit. "1" AIE bit No output while AIE is "0" Hi−Z INTN output LOW−level "1" AF bit "0" Alarm interrupt timing "0" Data 0 written to AF Timer Interrupt I The TI/TP bit setting selects either level interrupt mode or periodic interrupt mode output (with the AIE and FE bits set to “0”). (1) Level interrupt mode (TI/TP = “0”) I If TIE = “1” when the interrupt occurs, output INTN goes LOW. If TIE = “0”, INTN is in high impedance state. "1" TIE bit No output while TIE is "0" INTN output "0" Hi−Z LOW−level "1" TF bit "0" Timer interrupt timing Data 0 written to TF NIPPON PRECISION CIRCUITS INC.—11 SM8578BV (2) Periodic mode (TI/TP = “1”) I I If TIE = “1” when the interrupt occurs, output INTN goes LOW. If TIE = “0” when the interrupt occurs, output INTN stays high impedance and the TF bit is set to “1”, and this condition is maintained. "1" TIE bit tRTN INTN output Auto-return "1" TF bit "0" Timer interrupt timing "0" Hi−Z LOW−level Data 0 written to TF * Auto-return: The auto-return time (tRTN) is determined by the source clock set by register C. Source clock 4096Hz 64Hz 1Hz 1/60Hz Auto-return time (tRTN) 0.122ms 7.81ms 0.5s 0.122ms NIPPON PRECISION CIRCUITS INC.—12 SM8578BV USAGE NOTES Data Read/Write I I I I For both writing and reading data, the first 4 bits after CE goes HIGH are mode select bits, the next 4 bits assign the address, and subsequent bits are read/write data in 8-bit units. When writing data, the data must be input in 8-bit units. If CE goes LOW before an 8-bit unit data word is input, the 8-bit data being written when CE goes LOW will not be written correctly. Write data and read data are in LSB-first format. [Write mode] 1) If the first 4 bits after CE goes HIGH have value “3”, write mode is selected. The next 4 bits determine the write address. 2) The next 8-bit data unit is written to the write address, and subsequent 8-bit data units are written to consecutive locations addressed using an automatic address increment function. 3) The address automatic increment function is cyclical, with address 0 following after address F. CE CLK DATA D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Write mode select code (3H) Adress select (N) Data write (adress N) Data write (adress N+1) [Read mode] 1) If the first 4 bits after CE goes HIGH have value “C”, read mode is selected. The next 4 bits determine the read address. 2) The next 8-bit data unit is read from the read address, and subsequent 8-bit data units are read from consecutive locations addressed using an automatic address increment function. 3) The address automatic increment function is cyclical, with address 0 following after address F. CE CLK DATA D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Read mode select code (CH) Adress select (N) Data read (adress N) Data read (adress N+1) From the point DATA is in output mode. Note. If the mode set code is neither “C” nor “3”, all subsequent data is ignored and the DATA pin input state is maintained. NIPPON PRECISION CIRCUITS INC.—13 SM8578BV Alarm Interrupt Alarms can be set for day, day-of-week, hour, and minute. Also, multiple day-of-week alarms can be set. It is recommended that the AF bit and AIE bit be initialized to “0” to avoid unexpected hardware interrupts during the alarm setting procedure. Subsequent alarm data can be set and then the AF flag can be reset to zero for reliable initialization. Then the AIE bit should be set to “1”. If hardware interrupts are never used, the AIE should be set to “0” and the AF bit should be monitored using software as necessary. Example 1) Alarm output for 6pm tomorrow: • Write “0” to AIE bit, and “0” to AF bit. • Write “1” to day alarm AE bit. • Write register 3’s current day-of-week data left-shifted by 1 bit into the day-of-week alarm register. If bit 6 in register 3 is “1”, left shift into the fr bit is not allowed. Instead, write “01h” (Sunday). • Write “18h” to the hour alarm register. • Write “00h” to the minute alarm register. • Reset the AF bit to zero. • Write “1” to the AIE bit. Example 2) Alarm output for 6am every day excluding Saturday and Sunday: • • • • • • • Write “0” to AIE bit, and “0” to AF bit. Write “1” to day alarm AE bit. Write “3Eh” to the day-of-week alarm register. Write “06h” to the hour alarm register. Write “00h” to the minute alarm register. Reset the AF bit to zero. Write “1” to the AIE bit. Interrupt Output (INTN) I I The INTN output mode can be selected, by internal mode setting, for timer interrupt output, alarm interrupt output, or arbitrary frequency output. The output mode setting is set by the TIE, AIE, and FE bits as shown in the following table. Note that multiple “1” bits are invalid. Bit Mode TIE AIE 0 1 0 0 FE 0 0 1 0 Timer interrupt output Alarm interrupt output Arbitrary frequency output Output disabled 1 0 0 0 NIPPON PRECISION CIRCUITS INC.—14 SM8578BV Monitoring Oscillator Frequency A 1Hz signal is output from INTN when input CE is biased to 1/2VDD. By monitoring this output, the oscillator frequency can be adjusted by tuning an external capacitor (CG). XTN R3 XT CG VDD R1 SW C1 R2 VSS CE INTN INTN output (1Hz) R1 = R2 ( ≈ 10kΩ) R3 ≈ 10kΩ C1 ≈ 0.1µF TYPICAL APPLICATION CIRCUIT VCC SM8578BV VDD VCC INTN XT CE CLK Micro controller XTN VSS DATA GND NIPPON PRECISION CIRCUITS INC.—15 SM8578BV Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: sales@npc.co.jp NC9619DE 2004.10 NIPPON PRECISION CIRCUITS INC.—16