SM8580AM

NIPPON PRECISION CIRCUITS INC. SM8580AM Real-time Clock IC with 4-bit Interface and Built-in Temperature Sensor OVERVIEW The SM8580AM is a real-time clock IC based on a 32.768 kHz crystal oscillator, which features a 4-bit parallel interface for communication with an external microcontroller. It comprises second-counter to year-counter clock and calendar circuits that feature automatic leap-year adjustment up to year 2099, alarm and timer interrupt functions, clock counter change detect functions, ±30-second correction function, time error correction function, and built-in temperature sensor. The 4-bit parallel interface is compatible with general-purpose SRAM over a high-speed bus. FEATURES s s PINOUT (Top view) s s s s s s s s s s s High-speed bus 4-bit parallel interface Date, day, hour, minute, and second-counter presettable alarm interrupt 1/4096 seconds to 255 minutes presettable interval timer interrupt function 2 software-maskable alarm and timer interrupt outputs Clock counter change detect functions 4-digit western calendar display Automatic leap year correction up to year 2099 ±30-second adjust function −195 to +192ppm time error correction range Built-in temperature sensor (analog voltage output) 2.4 to 5.5V interface voltage range 1.6 to 5.5V clock voltage range 0.6µA/3V (typ) current consumption CE0N FCON FOUT VTEMP AIRQN TIRQN A0 A1 A2 A3 RDN VSS 1 24 VDD XT XTN N.C. N.C. N.C. CE1 D0 D1 D2 D3 SM8580AM 12 13 ORDERING INFORMATION D e vice SM8580AM P ackag e 24-pin SSOP WRN NIPPON PRECISION CIRCUITS—1 S M8580AM PACKAGE DIMENSIONS (Unit: mm) 24-pin SSOP 5.40 0.20 7.80 0.30 10.05 0.20 10.20 0.30 0.15 − 0.0 + 0.1 5 0.12 M 0.10 0.10 0.20 1.90 0.10 0.8 0.36 0.10 0.10 1.80 0.50 0.20 0 to 10 BLOCK DIAGRAM Control line CG XT CD OSC XTN Divider Digital Trimming Controller Clock and Calendar Counter Alarm Register AIRQN TIRQN FOUT FCON A0 to A3 D0 to D3 WRN RDN Temperature Sensor CE0N CE1 BUS Interface Interrupt Control FOUT Control Timer Register FOUT Register Control Register VDD VSS VTEMP NIPPON PRECISION CIRCUITS—2 S M8580AM PIN DESCRIPTION Number 1 Name CE0N I/O I Function 1 Chip enable 0 input with built-in pull-up resistor. The SM8580AM can be accessed when CE0N is LOW and CE1 is HIGH. FOUT output frequency select control input (when CE1 is HIGH). 32.768kHz fixed frequency output when FCON is LOW . Output frequency determined by bit FD when FCON is HIGH (when FE bit is 1). Note that a HIGH-level voltage should be applied to FCON to avoid unwanted 32.768kHz output during backup. Frequency set register, frequency output (CMOS output) Te m p e rature voltage output (analog output) Alarm interrupt output (N-channel open-drain output) Timer interrupt output (N-channel open-drain output) 2 FCON I 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FOUT VTEMP AIRQN TIRQN A0 A1 A2 A3 RDN VSS WRN D3 D2 D1 D0 O O O O I I I I I – I I/O I/O I/O I/O Address inputs. Connect to the microcontroller address bus. The selected register address is input on this bus when accessing the SM8580AM (positive logic). Read strobe input. Data can be read from S M 8 5 8 0 A M when RDN is LOW and WRN is HIGH. An error will occur if both RDN and WRN are simultaneously LOW . Ground W r ite strobe input. Data can be written to S M 8 5 8 0 A M when RDN is HIGH and WRN is LOW . An error will occur if both RDN and WRN are simultaneously LOW . Data bus input/outputs. Connect to the microcontroller data bus. 18 CE1 I Chip enable 1 input with built-in pull-down resistor. The SM8580AM can be accessed when CE0N is LOW and CE1 is HIGH. FOUT is in output mode when CE1 is HIGH, regardless of the state of CE0N. FOUT is high impedance when CE1 is LOW . No connection No connection No connection Oscillator output, with built-in oscillator capacitance C D Oscillator output, with built-in oscillator capacitance C G Supply 19 20 21 22 23 24 NC NC NC XTN XT VDD – – – O I – 1 . Connect a 0.1µF capacitor between VDD and V S S . NIPPON PRECISION CIRCUITS—3 S M8580AM FOUT Output and SM8580AM Access Relationship CE0N HIGH LOW CE1 LOW LOW FCON × × LOW LOW HIGH HIGH HIGH HIGH LOW LOW LOW HIGH HIGH HIGH 0 1 High impedance FD bit select frequency output Yes Yes 0 1 0 1 High impedance FD bit select frequency output 32.768kHz output 32.768kHz output No No Yes Yes FE bit × × 0 1 FOUT output H igh impedance H igh impedance 32.768kHz output 32.768kHz output S M 8 5 8 0 A M accessible No No No No SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V P arameter S upply voltage range Input voltage range Output voltage range Storage temperature range Symbol VDD V IN VOUT1 VOUT2 T s tg A ll inputs, D0 to D3 TIRQN, AIRQN F O U T, D0 to D3, V T E M P Condition Rating −0 .3 to 7.0 V S S − 0 .3 to V D D + 0 .3 V S S − 0 .3 to 8.0 V S S − 0 .3 to V D D + 0 .3 −5 5 to 125 Unit V V V V °C Recommended Operating Conditions VSS = 0 V P arameter S upply voltage range Clock supply voltage range Operating temperature range Symbol VDD VCLK T o pr Condition Rating 2 .4 to 5.5 1 .6 to 5.5 −4 0 to 85 Unit V V °C NIPPON PRECISION CIRCUITS—4 S M8580AM DC Electrical Characteristics VSS = 0V, VDD = 1.6 to 5.5V, Ta = −40 to 85°C unless otherwise noted Rating P arameter C urrent consumption 1 Current consumption 2 Current consumption 3 Symbol ID D 1 ID D 2 ID D 3 V D D = 5V V D D = 3V V D D = 5V Condition min CE0N = RDN = W R N = V D D , A0 to A3 = D0 to D3 = V D D o r V S S , CE1 = FCON = V S S , AIRQN = TIRQN = FOUT = V D D , VTEMP output OFF (TEMP bit = 0) Ta = 25 °C , CE0N = RDN = W R N = V D D , A0 to A3 = D0 to D3 = V D D o r V S S , CE1 = FCON = V S S , AIRQN = TIRQN = FOUT = V D D , VTEMP output ON (TEMP bit = 1) CE0N = CE1 = RDN = W R N = V D D , A0 to A3 = D0 to D3 = V S S , FCON = V SS, AIRQN = TIRQN = FOUT = VTEMP = Hi-Z, VTEMP output OFF (TEMP bit = 0), FOUT = 32kHz output, C L = 0 pF CE0N = CE1 = RDN = W R N = V D D , A0 to A3 = D0 to D3 = V S S , FCON = V SS, AIRQN = TIRQN = FOUT = VTEMP = Hi-Z, VTEMP output OFF (TEMP bit = 0), FOUT = 32kHz output, C L = 3 0pF – – – typ 1.0 0.6 50 max 2.0 1.0 75 µA µA µA Unit Current consumption 4 ID D 4 V D D = 3V – 40 60 µA Current consumption 5 ID D 5 V D D = 5V – 3.0 7.5 µA Current consumption 6 ID D 6 V D D = 3V – 1.7 4.5 µA Current consumption 7 ID D 7 V D D = 5V – 8.0 20 µA Current consumption 8 ID D 8 V D D = 3V – 5.0 12 µA HIGH-level input voltage 1 L O W -level input voltage 1 HIGH-level input voltage 2 L O W -level input voltage 2 HIGH-level input voltage 3 L O W -level input voltage 3 Input leakage current Pull-up resistance 1 P ull-up resistance 2 P ull-down resistance 1 P ull-down resistance 2 P ull-down resistance 3 P ull-down resistance 4 H IGH-level output voltage 1 HIGH-level output voltage 2 HIGH-level output voltage 3 L O W -level output voltage 1 L O W -level output voltage 2 L O W -level output voltage 3 L O W -level output voltage 4 L O W -level output voltage 5 Output leakage current V I H1 V I L1 V I H2 V I L2 V I H3 V I L3 IL E A K RUP1 RUP2 R DW N 1 R DW N 2 R DW N 3 R DW N 4 VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 VOL4 VOL5 IO Z V D D = 4 .5 to 5.5V, CE0N, FCON, RDN, WRN, A0 to A3, D0 to D3 V D D = 2 .4 to 3.6V, CE0N, FCON, RDN, WRN, A0 to A3, D0 to D3 V D D = 1 .6 to 5.5V, CE1 C E0N = V D D , C E1 = V S S , F C O N = R D N = WRN = A0 to A3 = V D D o r V S S V D D = 5V V D D = 3V V D D = 5V V D D = 3V V D D = 5V V D D = 3V V D D = 5V V D D = 3V V D D = 3V V D D = 5V V D D = 3V V D D = 3V V D D = 5V V D D = 3V IO H = −1 mA, D0 to D3, FOUT IO H = −1 00µA, D0 to D3, FOUT IO L = 1 mA, D0 to D3, FOUT IO L = 1 00µA, D0 to D3, FOUT IO L = 1 mA, AIRQN, T I R Q N CE0N = V S S 2.2 V S S − 0 .3 0.8V D D V S S − 0 .3 0.8V D D V S S − 0 .3 −0 .5 75 150 20 – – – – – – – 150 300 40 85 60 110 – – – – – – – – – V D D + 0 .3 0.8 V D D + 0 .3 0.2V D D V D D + 0 .3 0.2V D D 0.5 300 600 80 170 120 220 5.0 3.0 3.0 0.5 0.8 0.1 0.25 0.4 0.5 V V V V V V µA kΩ kΩ MΩ MΩ kΩ kΩ V V V V V V V V µA CE1 = V D D 42.5 30 CE1 = 0.5V 55 4.5 2.0 2.9 0 0 0 0 0 −0 .5 D 0 to D3, AIRQN, T I R Q N , F O U T, V O U T = V D D o r V S S NIPPON PRECISION CIRCUITS—5 S M8580AM Terminal Capacitance Characteristics Ta = 25°C, f = 1MHz Rating P arameter Address input capacitance Data output capacitance Symbol CADD C D ATA A0 to A3 D0 to D3 Condition min – – typ – – max 8 15 pF pF Unit Oscillator Characteristics Ta = 25°C, Seiko Epson C-002SH crystal (CI = 30kΩ, CL = 10pF) unless otherwise noted Rating P arameter Oscillator start time Oscillator stop voltage Frequency voltage characteristic Frequency accuracy Input capacitance Output capacitance Symbol tS TA V S TO f/V εIC CG CD V D D = 1 .6 to 5.5V V D D = 3 .0V V D D = 3 .0V V D D = 3 .0V Condition min V D D = 1 .6 V – – −2 −2 0 – – typ – – – – 15 10 max 3.0 1.5 +2 +20 – – s V ppm/V ppm pF pF Unit AC Characteristics (1) VSS = 0V, Ta = −40 to 85°C unless otherwise noted Rating P arameter Symbol Condition min FOUT duty Duty V D D = 5 V ± 10% V D D = 3 V ± 10% Oscillator failure detection time tO S C V D D = 5 V ± 10% V D D = 3 V ± 10% 40 40 10 10 max – – – – min 60 60 – – % % ms ms Unit NIPPON PRECISION CIRCUITS—6 S M8580AM AC Characteristics (2) VDD = 2.4 to 3.6V, VSS = 0V, Ta = −40 to 85°C, inputs VI = 0.5VDD, outputs VO = 0.5VDD output load capacitance CL = 100pF (tACC, tACS, tARD) Rating P arameter Read cycle time Address access time CE access time RD access time CE output set time CE output floating RD output set time RD output floating Output hold time W r ite cycle time Chip select time Address valid to end-of-write Address setup time Address hold time W r ite pulsewidth Input data set time Input data hold time Symbol min tR C tA C C tA C S tA R D tC L Z tC H Z tO L Z tO H Z tO H tW C tC W tA W tA S tW R tW P tD W tD H 150 – – – 5 – 5 – 10 150 140 140 0 0 130 80 0 max – 150 150 100 – 60 – 60 – – – – – – – – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit VDD = 4.5 to 5.5V, VSS = 0V, Ta = −40 to 85°C, inputs VI = 0.5VDD, outputs VO = 0.5VDD output load capacitance CL = 100pF (tACC, tACS, tARD) Rating P arameter Read cycle time Address access time CE access time RD access time CE output set time CE output floating RD output set time RD output floating Output hold time W r ite cycle time Chip select time Address valid to end-of-write Address setup time Address hold time W r ite pulsewidth Input data set time Input data hold time Symbol min tR C tA C C tA C S tA R D tC L Z tC H Z tO L Z tO H Z tO H tW C tC W tA W tA S tW R tW P tD W tD H 85 – – – 3 – 3 – 5 85 70 70 0 0 65 35 0 max – 85 85 45 – 30 – 30 – – – – – – – – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit NIPPON PRECISION CIRCUITS—7 S M8580AM Data read t RC A0 to A3 t ACC t ACS CE0N t OH t CLZ CE1 t CHZ t ACS t CLZ t ARD t CHZ RDN t OLZ D0 to D3 t OHZ Data write CE control t WC A0 to A3 t AW t CW CE0N t WR t AS CE1 WRN t DW D0 to D3 t DH WR control t WC A0 to A3 t AW CE0N t WR t AS CE1 t WP WRN t DW D0 to D3 t DH NIPPON PRECISION CIRCUITS—8 S M8580AM Temperature Sensor VSS = 0V, Ta = −40 to 85°C unless otherwise noted Rating P arameter Symbol Condition min Te m p e rature sensor output voltage Output accuracy Te m p e rature Linearity2 Te m p e rature detection range Output resistance 3 sensitivity 1 VOUT TA C R VSE ∆N L TO P R RO CL RL tR S P Ta = 25 °C , VSS reference output voltage, V D D = 2 .7 to 5.5V, V T E M P Ta = 25 °C –40 °C ≤ Ta ≤ 8 5 °C , V D D = 2 .7 to 5.5V –40 °C ≤ Ta ≤ 8 5 °C , V D D = 2 .7 to 5.5V ∆NL ≤ ± 2.0%, V D D = 2 .7 to 5.5V Ta = 25 °C , V D D = 2 .7 to 5.5V, V T E M P V D D = 2 .7 to 5.5V V D D = 2 .7 to 5.5V V D D = 3 .0V, R L = 5 00k Ω , C L = 1 00pF – – −7.3 – −40 – – 500 – max 1.470 – −7.8 – – 1.0 – – – min – ±5 −8.3 ±2.0 85 3.0 100 – 200 V °C m V / °C % °C kΩ pF kΩ µs Unit Output load capacitance Output load resistance Response time 1. Te m p e rature sensitivity V S E = ( V(85 °C) − V ( −40 °C) ) ÷ 125 [mV/ °C] 2. Linearity ∆NL = a ÷ b × 1 00 [%], where a = maximum deviation between the measured value and the approximated value of V T E M P, and b = difference between the measured values at temperatures of −40 and 85 °C VTEMP(V) a V (−40 C) a b Approximate value Measured value a −40 C V (85 C) Ta 0C 85 C 3. Output resistance R O = ∆V 1 ÷ ∆I1 [Ω ] SM8580A VTEMP 1MΩ I1 OP AMP V1 NIPPON PRECISION CIRCUITS—9 S M8580AM Backup Transfer and Return P arameter 1 Supply voltage falling edge CE setup time Supply voltage fall time Supply voltage rise time Supply voltage rising edge CE hold time Rating Symbol tC D tF tR tC U (V D D − V C L K ) ≤ 2 .0V (V D D − V C L K ) > 2.0V Condition min 0 2 50 1 0 max – – – – – min – – – – – µs µs/V µs/V µs/V µs Unit 1. Before switching the supply, confirm that the chip enable CE1 is LOW and that S M 8 5 8 0 A M is deselected. VDD VCLK tCD CE1 VIL tF tCU tR VIL Backup mode NIPPON PRECISION CIRCUITS—10 S M8580AM FUNCTIONAL DESCRIPTION Register Tables Bank 0 (clock, calendar registers) A d dress 0 Second registers 1 2 Minute registers 3 4 Hour registers 5 6 7 Date registers 8 9 Month registers A B C Year registers D E F Control register 800 TEST Bank SEL1 400 TEMP Bank SEL0 200 2000 S TO P 100 1000 BUSY/ ADJ s Bank 2 (digital correction, timer registers) Bit 0 1 10 1 10 1 10 1 1 10 1 10 1 10 A d dress 0 1 2 3 4 5 6 7 Register Digital correction registers – – Timer counter set registers Timer counter output registers Timer setting – – – – – Timer control Control register Bit 3 DT3 DT_ON # # 8 128 8 128 TE # # * * * TEST Bank SEL1 Bit 2 DT2 DT6 # # 4 64 4 64 TI/TP # # * * * TEMP Bank SEL0 Bit 1 DT1 DT5 # # 2 32 2 32 TD1 # # * * * TF S TO P Bit 0 DT0 DT4 # # 1 16 1 16 TD0 # # * * * TIE BUSY/ ADJ Register Bit 3 8 FOS 8 # 8 # Bit 2 4 40 4 40 4 # 4 4 # 4 # 4 40 Bit 1 2 20 2 20 2 20 2 2 20 2 # 2 20 D a y of week register # 8 # 8 # 8 80 8 9 A B C D E F Bank 1 (alarm, FOUT registers) A d dress 0 Second registers 1 2 Minute registers 3 4 Hour registers 5 6 7 Date registers 8 9 A B C D E F – – CE1 control FOUT divider set register FOUT frequency set register Alarm control Control register AE * * * * * 20 * * * FD1 FD4 AF S TO P 10 * * * FD0 FD3 AIE BUSY/ ADJ D a y of week register AE AE 8 * 4 4 20 2 2 10 AE 8 40 4 20 2 10 1 AE 8 40 4 20 2 10 1 Register Bit 3 8 Bit 2 4 Bit 1 2 Bit 0 1 s s s s s 1 s 1 s C T E M P CDT_ON # FE TEST Bank SEL1 FD2 # TEMP Bank SEL0 s s All bits in register F and bits 2 to 3 in register E are common to all register banks. When alarm interrupts are not used, registers 0 to 8 in bank 1 can be used as RAM (total 36 bits). When timer interrupts are not used, registers 4 to 5 in bank 2 can be used as RAM (total 8 bits). When digital correction is not used, registers 0 to 1 in bank 2 can be used as RAM, excluding bit 3 (DT_ON) in register 1 (total 7 bits). The BUSY/ADJ bit function is BUSY when reading, and ADJ when writing. The BUSY flag is set to 1 an interval of 244µs before clock counter update timing. Registers 6 and 7 in bank 2 are read-only registers, and cannot be written to. When power is applied, all register bits are undefined, with the exception of bits FOS, TEST and TEMP. Accordingly, these bits need to be initialized. TEST and TEMP are automatically reset to 0 and FOS is automatically reset to 1 when power is applied. Bits marked # are all read-only bits fixed to 0. These bits cannot be written to. Bits marked * can be used as RAM bits. NIPPON PRECISION CIRCUITS—11 S M8580AM Control Registers (All Banks, Register E (bits 2, 3) and F) Bank 0, 1, 2 F s A d dress E Bit 3 TEST Bank SEL1 s Bit 2 TEMP Bank SEL0 Bit 1 Bit 0 S TO P BUSY/ADJ s s TEST bit Factory test bit. This bit should be set to 0. Take care when writing to other E register bits not to accidentally write 1 to the TEST bit. Automatically resets to 0 when power (VDD) is applied. TEMP bit When set to 1, it enables the temperature sensor voltage output on pin VTEMP. When set to 0, VTEMP is high impedance. Automatically resets to 0 when power is applied. Bank SEL bits Bank select bits for read/write operations. Bank SEL1 0 0 1 1 Bank SEL0 0 1 0 1 Accessed bank Bank 0 Bank 1 Bank 2 Bank 1 s STOP bit When set to 1, the clock 32Hz frequency divider counter stops and is reset. When set to 0, the clock restarts. BUSY/ADJ bit This bit functions as a BUSY function in read mode, and as an ADJ function in write mode. • ADJ function (±30 seconds adjust bit) Second registers are reset to 00 and minute registers not incremented when the clock counter is reset and the second registers are currently 00 to 29. Second registers are reset to 00 and minute registers are incremented when the clock counter is reset and the second registers are currently 30 to 59. The ADJ bit is automatically reset to 0 a maximum of 244µs after it is set to 1, and thus the register should not be written to during this 244µs interval. • BUSY function (second registers increment or ±30 seconds adjust busy indicator bit) When BUSY is 1, the counters are being updated (incremented or reset). To read or write to clock and calendar registers, the BUSY flag has to be 0. If reading data when BUSY is set to 1, there is a possibility that incorrect (intermediate) data will be output. BUSY is set to 1 under the following two circumstances. Normal seconds digit carry 244µs Carry complete ±30 seconds digit adjust (when ADJ is set to 1) max 244µs Setting ADJ bit to "1" Adjust function complete NIPPON PRECISION CIRCUITS—12 S M8580AM s Function operation table Bit S TO P 0 0 1 1 ADJ 0 1 0 1 Clock Operating Adjust 1 Stopped Stopped/adjust 2 Timer Operating 3 Operating 4 Operating/stopped 5 Operating/stopped 5 Function Alarm Operating Operating Stopped Stopped FOUT Operating 6 Operating 7 Operating/stopped 8 Operating/stopped 8 1. ±30 seconds adjust function 2. The clock stops, and the ±30 seconds adjust function operates. 3. If the timer source clock frequency is ≤ 1 Hz, the timer cycle changes when the digital correction function is used. If the timer source clock frequency is ≥ 6 4Hz, the timer cycle is not affected when the digital correction function is used. 4. If the timer source clock frequency is ≤ 1 Hz, the timer cycle changes. If the timer source clock frequency is ≥ 6 4Hz, the timer cycle does not change. 5. If the timer source clock frequency is ≤ 1 Hz, the timer is stopped. If the timer source clock frequency is ≥ 6 4Hz, the timer operates. 6. If the FOUT source clock frequency is ≤ 1 Hz, the cycle changes when the digital correction function is used. If the FOUT source clock frequency is ≥ 3 2Hz, the cycle is not affected when the digital correction function is used. 7. If the FOUT source clock frequency is ≤ 1 Hz, the cycle changes. If the FOUT source clock frequency is ≥ 3 2Hz, the cycle does not change. 8. If the FOUT source clock frequency is ≤ 1 Hz, the timer is stopped. If the FOUT source clock frequency is ≥ 3 2Hz, the timer operates. NIPPON PRECISION CIRCUITS—13 S M8580AM Clock and Calendar Registers (Bank 0, Registers 0 to E) Clock counters (registers 0 to 5) Bank A d dress 0 Second registers 1 2 0 3 4 Hour registers 5 s Register Bit 3 8 FOS 8 Bit 2 4 40 4 40 Bit 1 2 20 2 20 2 20 Bit 0 1 10 1 10 1 10 Minute registers 8 4 Data in these registers is interpreted in BCD format. For example, if the seconds registers 1 and 0 contain 0101 1001, then the contents are interpreted as the value 59 seconds. s Hour register contents are values expressed in 24hour mode. FOS (oscillator failed detect bit (register 1, bit 3) ) s The FOS bit is the oscillator failure flag. It indicates that the oscillator has stopped due to supply voltage reduction during operation. It is set to 1 when the oscillator stops, and remains 1 until reset by writing 0 to FOS. It is not affected by the function of other bits. A 1 is written to FOS when power is applied. Day-of-week counter (register 6) Bank 0 s A d dress 6 Register D a y of week register Bit 3 Bit 2 4 Bit 1 2 Bit 0 0 1 0 1 0 1 0 Bit 0 1 W e e k d ay S u n d ay M o n d ay Tuesday W ednesday Thursday Friday Saturday The day-of-week register contains values representing the day of the week as shown in the following table. Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Calendar registers (registers 7 to E) Bank A d dress 7 Date registers 8 9 Month registers A 0 B C Year registers D E s Register Bit 3 8 Bit 2 4 Bit 1 2 20 Bit 0 1 10 1 10 8 4 2 8 80 800 TEST s 4 40 400 TEMP 2 20 200 2000 1 10 100 1000 Registers B to E are 4 digits forming the western calendar year. Leap-year adjustment is automatic for years 1901 to 2099. NIPPON PRECISION CIRCUITS—14 S M8580AM Alarm Registers (Bank 1, Registers 0 to 8, E) Alarm control register (register E) Bank 1 s A d dress E Register Alarm control s Bit 3 Bit 2 Bit 1 AF Bit 0 AIE AF bit (alarm flag) The AF bit is set to 1 when an alarm event is occurred, when the settings in the alarm set registers (bank 1, registers 0 to 8) match the settings in the day, clock and calendar registers (bank 0, registers 0 to 8). The AF bit remains 1 until reset by writing 0 to AF. A logic 1 cannot be written to AF. AIE bit (alarm interrupt enable) This bit enables the output on AIRQN when an alarm interrupt is occurred. If the AIE is not set to 1, then no output occurs even if the AF bit is set to 1. The AIRQN output is high impedance when AIE is set to 0. Alarm set registers (registers 0 to 8) Bank A d dress 0 Second registers 1 2 Minute registers 3 1 4 Hour registers 5 6 7 Date registers 8 s s Register Bit 3 8 AE 8 AE 8 AE Bit 2 4 40 4 40 4 * 4 4 * Bit 1 2 20 2 20 2 20 2 2 20 Bit 0 1 10 1 10 1 10 1 1 10 D a y of week register AE 8 AE s s These registers set the alarm time and date. When the corresponding bank 0 registers match these bank 1 registers, an alarm event occurs and AIRQN goes LOW if AIE is set to 1. An alarm can be set for date, day-of-week, hour, minute, and second. Each of these have a corresponding AE (alarm enable) bit which allows easy combination to create alarm events every second, every minute, hourly, daily, and weekly alarms. s Note that alarms cannot be set for multiple days within the same week (such as an alarm on Mondays and Fridays only). When an AE bit is set to 0, the relevant register and corresponding bank 0 register are compared. When an AE bit is set to 1, the data is disregarded and all bits considered as “don’t care” bits. Day-of-week alarm bits (register 6) s The day-of-week register contains values representing the day of the week as shown in the following table. Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0 W e e k d ay S u n d ay M o n d ay Tuesday W ednesday Thursday Friday Saturday NIPPON PRECISION CIRCUITS—15 S M8580AM Timer Registers (Bank 2, Registers 4 to 8, E) Timer control registers (registers 8, E) Bank 2 E s A d dress 8 Register Timer setting Timer control Bit 3 TE Bit 2 TI/TP Bit 1 Bit 0 TF TIE s s s TE bit (timer enable) Timer countdown stop/start control bit. When set to 1, the timer starts counting down. When set to 0 during countdown, the timer stops. TF bit (timer flag) The timer flag is set to 1 when the timer counter counts down to zero, occurring a timer event. It is held at 1 until 0 is written to this bit. A 1 cannot be written to TF. TIE bit (timer interrupt enable) This bit enables the timer interrupt output on TIRQN when a timer event is occurred. If the TIE is not set to 1, then no output occurs even if the TF bit is set to 1. The TIRQN output is high impedance when TIE is set to 0. TI/TP bit (level/periodic interrupt mode select bit) Sets the timer interrupt signal output mode. The SM8580AM supports two timer function modes. • TI/TP = 0 (level interrupt mode) When a timer interrupt is occurred, TIRQN goes LOW (if TIE = 1) and TF is set to 1. TIRQN remains LOW and TF is held at 1 until a 0 is written to the TF bit. The timer operates by counting down until the data is zero, then the TE bit is cleared and the count stops automatically. However, if the timer is started when the TF bit is 1, then the TE bit is not cleared. The timer count register contents remain zero after the count down stops. • TI/TP = 1 (periodic interrupt mode) When a timer interrupt is occurred, TIRQN goes LOW (if TIE = 1) and TF is set to 1. TIRQN subsequently goes high impedance after a fixed interval, but TF is held at 1 until a 0 is written to the TF bit. The timer operates by counting down until the data is zero, then the timer register data is reloaded automatically after a fixed interval, and the countdown restarts. This mode can be used as a repetitive interval timer. Timer source clock set register (register 8) Bank 2 s A d dress 8 Register Timer setting Bit 3 Bit 2 Bit 1 TD1 Bit 0 TD0 The register 8 bits 0 and 1 set the timer source clock to one of four frequencies listed in the following table. TD1 0 0 1 1 TD0 0 1 0 1 Timer source clock 4096Hz 64Hz 1Hz 1/60Hz (1 minute) NIPPON PRECISION CIRCUITS—16 S M8580AM Timer counter set registers (registers 4 to 7) Bank A d dress 4 Timer counter set registers 5 2 6 Timer counter output registers 7 s Register Bit 3 8 128 8 128 Bit 2 4 64 4 64 Bit 1 2 32 2 32 Bit 0 1 16 1 16 s s s Registers 4 and 5 set an 8-bit presettable binary down-counter value for the timer interrupt function. The value of the count can be determined by reading the values of registers 6 and 7 during the count. The presettable binary down-counter is updated when the data is written to registers 4 and 5. The data written to registers 4 and 5 are stored and are not changed until replacement data is written. s s This allows these bits to function as RAM bits if the timer interrupt mode is not used (when TIE = 0). When TE is set to 1, periodic interrupts are not output on TIRQN, even if registers 4 and 5 are set to zero. The timer error once a timer operation is started is a maximum of one cycle of the source clock. Timer operations started and stopped in less than one cycle of the source clock are not counted. Timer interrupt function example Example of an hourly periodic timer interrupt Bank A d dress 4 Timer counter set registers 5 2 8 E Timer set register Timer control TE TEST 1 TEMP 1 TF 1 1 0 0 1 1 Register Bit 3 1 Bit 2 1 Bit 1 0 Bit 0 0 The timer start timing is set up in write mode when the WRN rising edge corresponding to the TE bit occurs, as shown in the following timing diagram. Address 8 WRN pin D3 pin Timer TE TIRQN pin Count down start Finish NIPPON PRECISION CIRCUITS—17 S M8580AM CE1 Control Register (Bank 1, Register B) Bank 1 s A d dress B Register CE1 control s Bit 3 CTEMP Bit 2 CDT_ON Bit 1 Bit 0 s s This register determines whether the temperature sensor function and digital correction function in combination with the CE1 input pin. CTEMP determines the temperature sensor operation, and CDT_ON determines the digital correction function operation. CTEMP bit When CTEMP is set to 0, the temperature sensor operates only when the CE1 pin is HIGH. When CTEMP is set to 1, the temperature sensor operates without any relationship to the CE1 input state. Note that the temperature sensor operation also depends on the bank 2 TEMP bit to be active. CDT_ON bit When CDT_ON is set to 0, the digital correction function operates only when the CE1 pin is HIGH. When CDT_ON is set to 1, the digital correction function operates without any relationship to the CE1 input state. Note that the digital correction function also depends on the bank 2 DT_ON bit to be active. Function operation tables CE1 pin × LOW HIGH LOW HIGH CTEMP bit × 0 0 1 1 TEMP bit 0 1 1 1 1 Temperature sensor Not operating Not operating Operating Operating Operating CE1 pin × LOW HIGH LOW HIGH CDT_ON bit × 0 0 1 1 DT_ON bit 0 1 1 1 1 Digital correction Not operating Not operating Operating Operating Operating Frequency Set Registers (Bank 1, Registers C, D) Bank 1 D s A d dress C Register FOUT divider set register FOUT frequency set register Bit 3 Bit 2 FD2 Bit 1 FD1 FD4 Bit 0 FD0 FD3 FE FD3, FD4 bit FOUT source clock frequency set bits. FD4 0 0 1 1 FD3 0 1 0 1 S o u rce clock FD2 1 1 FD1 0 0 1 1 FD0 0 1 0 1 F r e q u e n cy divider ratio 1/5 1/10 1/15 1/30 FOUT output duty 1/5 1/2 1/3 1/2 32768Hz 1 1024Hz 1 32Hz 1Hz s s FD0 to FD2 bits Frequency divider set bits for the FOUT source clock set by FD3 and FD4. FD2 0 0 0 0 FD1 0 0 1 1 FD0 0 1 0 1 F r e q u e n cy divider ratio 1/1 1/2 1/3 1/6 FOUT output duty 1/2 1/2 1/3 1/2 FE bit FOUT frequency signal set by FD0 to FD4 output enable bit. When FCON is HIGH and FE is set to 1, then the frequency signal set by FD0 to FD4 is output on FOUT. When FE is set to 0, the FOUT output is high impedance. When FCON is LOW, a standard 32.768kHz signal is output on FOUT without reference to the settings in the C and D registers. NIPPON PRECISION CIRCUITS—18 S M8580AM Digital Correction Registers (Bank 2, Registers 0, 1) Bank 2 1 s A d dress 0 Register Digital correction registers Bit 3 DT3 DT_ON s Bit 2 DT2 DT6 Bit 1 DT1 DT5 Bit 0 DT0 DT4 s s These registers enable and set the level of digital correction applied to oscillator clock. DT_ON enables the correction function, and bits DT0 to DT6 set the level of correction to be applied. This function adjusts the number of 1 second cycles which occur every 10 seconds. When digital correction is not used, a 0 should be written to DT_ON to disable correction. Correction range and resolution (correction range depends on the frequency) Correction range Correction resolution Correction cycle 3.05ppm 10 seconds Correction value calculation • Positive correction (leading time) [DT6:0] = correction ÷ 3.05 (with decimal round-off) Example: for correction of 192.15ppm [DT6:0] = 192.15 ÷ 3.05 = 6310 = 01111112 • Negative correction (lagging time) [DT6:0] = 128 + correction ÷ 3.05 (with decimal round-off) Example: for correction of −158.6ppm [DT6:0] = 128 + (−158.6 ÷ 3.05) = 7610 = 10011002 −195.20 to +192.15ppm s DT bits and digital correction (correction value depends on the frequency) Digital correction bits DT6 0 0 DT5 1 1 DT4 1 1 DT3 1 1 ↓ 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 ↓ 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 DT2 1 1 DT1 1 1 DT0 1 0 Correction (ppm) +192.15 +189.10 ↓ +6.10 +3.05 ±0.00 −3.05 −6.10 ↓ −192.15 −195.20 NIPPON PRECISION CIRCUITS—19 S M8580AM INTERRUPT OPERATION Alarm Interrupt When AIE is 1 and an alarm event occurs (AF bit is set to 1), AIRQN output goes LOW. If AIE is 0, however, AIRQN is in a high-impedance state. The alarm interrupt is output when a carry from the seconds register to the minute register occurs. "1" AIE bit "0" AIRQN pin "1" "1" *No output while AIE bit is "0". Hi-Z "L" level "1" "0" Interrupt is active. Setting AF bit to "0". "0" AF bit Timer Interrupt The timer interrupt mode (level interrupt or periodic interrupt) is selected by the setting of TI/TP. Level interrupt mode (TI/TP = 0) When TIE is 1 and a timer interrupt event occurs (TF bit is set to 1), TIRQN goes LOW. When TIE is 0, however, TIRQN is in a high-impedance state. "1" TIE bit "0" TIRQN pin "1" "1" *No output while TIE bit is "0". Hi-Z "L" level "1" "0" TF bit "0" Interrupt is active. Setting TF bit to "0". NIPPON PRECISION CIRCUITS—20 S M8580AM Periodic interrupt mode (TI/TP = 1) When TIE is 1 and a timer interrupt event occurs (TF bit is set to 1), TIRQN goes LOW. If TIE is 0, however, TIRQN is in a high-impedance state, and the TF bit remains set to 1. "1" TIE bit "0" tRTN TIRQN pin Auto-return Hi-Z "L" level "1" TF bit "0" Interrupt is active. Setting TF bit to "0". The auto-return time (tRTN), shown in the following figure and table, is determined by the source clock frequency set by register D in bank 1 bits FD3 and FD4. Source CLK Hi-Z TIRQN pin Auto return time (tRTN) Interrupt cycle "0" S o u rce clock 4096Hz 64Hz 1Hz 1/60Hz A uto-return time (t R T N ) 0.122ms 7.81ms 7.81ms 7.81ms NIPPON PRECISION CIRCUITS—21 S M8580AM APPLICATION NOTES Setting the Alarm Alarms can be set for day, weekday, hour, minute, and second. However, it is not possible to set an alarm for more than one weekday. Note that it is recommended that AF and AIE be set to 0 at the same time to avoid accidental hardware interrupts while setting the alarm. After the alarm data is entered, initialization occurs when AF is again set to 0. If the interrupt output is not used by setting AIE set to 0, an alarm can still be controlled by software monitoring of the AF bit. Example 1 To set an alarm for 6pm of the following day: • Set bits AIE and AF to 0. • Set the day register AE bit to 1. • Acquire the current weekday setting from bank 0 register 6, add 1 to the current value (except in • • • • • the case of Saturday), and write the updated data. Note that the day following 6H (Saturday) is 0H (Sunday). Write 18H to the hour alarm register. Write 00H to the minute alarm register. Write 00H to the seconds alarm register. Set bit AF to 0. Set bit AIE to 1. Example 2 To set an alarm for 6am on every for Sunday: • • • • • • • • Set bits AIE and AF to 0. Set the day alarm register AE bit to 1. Write 0H to the weekday alarm register. Write 06H to the hour alarm register. Write 00H to the minute alarm register. Write 00H to the seconds alarm register. Set bit AF to 0. Set bit AIE to 1. Using the Temperature Sensor The SM8580AM temperature sensor can be used to monitor the surrounding temperature. The temperature sensor information can then be used to adjust the clock for any temperature variations in the oscillator frequency which affect the accuracy of the clock. One method of utilizing the temperature sensor to adjust timing errors is by using the clock error correction function (digital correction), as described below. 1. Based on the known temperature characteristics of the oscillator crystal, store temperature correction values for various temperatures in an external non-volatile EEPROM. 2. Use an A/D converter, such as in a general-purpose CPU, to convert the VTEMP temperature sensor output voltage into a digital value. 3. Use the digital value of the current temperature to access the temperature correction data stored in the EEPROM, and then write the corresponding data into the digital correction registers. This procedure is useful in implementing a highaccuracy clock function. Monitoring Digital Correction Using the test mode allows the 64Hz digital correction clock to be output on pin FOUT. The test mode works as follows. 1. 2. 3. 4. Apply a HIGH-level on FCON. Set the FOUT frequency set register FE bit to 1. Set the CE1 control register CDT_ON bit to 1. Set correction data in the digital correction register DT0 to DT6 bits, and then set DT_ON to 1. 5. Set the bank 2 register C, bit 1 to 1. 6. When CE0N is LOW and CE1 is HIGH and the test mode set register TEST bit is set to 1, the digital correction cycle changes from 10 seconds to 1/64 seconds, and the clock output on FOUT is the 64Hz clock after timing correction. The output is the corrected timing for the set digital correction value corresponding to a 64Hz clock × 64[ppm]. Measuring this output provides a quick method for monitoring the digital correction function. 7. When CE0N goes HIGH, the TEST bit is reset to 1 and test mode is released. NIPPON PRECISION CIRCUITS—22 S M8580AM NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9915AE 2000.05 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—23