SM8761 series Spread Spectrum Clock Generator
OVERVIEW
The SM8761 series are compact clock generator ICs that have a spread spectrum (SS) function to reduce undesirable EMI radiation. They have a built-in crystal oscillator circuit, PLL, and loop filter. They accept an input clock signal, generated using an external crystal or direct external clock input, and output an SS-modulated clock signal. In addition, versions are available for center spread and down spread modulation mode, and all have a mode control pin to select the SS modulation function.
FEATURES
I I I
Spread spectrum clock output to reduce EMI Correspond to wide range of output frequency Low jitter
SM8761AA
I I I
Operating supply voltage: 3.3 ± 0.3V Multiplication: 1-time multiplication Package: 8-pin SOP
SM8761AB Center spread ± 0.75% to ± 2.25% 12MHz to 32MHz 12MHz to 32MHz 12MHz to 32MHz 1-time multiplication 200ps (typ) @16MHz
Spectrum modulation mode Spectrum modulation rate*1 Crystal element connection Input frequency External input clock Output frequency Multiplication Jitter (Cycle-to-Cycle)
Down spread – 1.0% to – 3.8% 20MHz to 40MHz 20MHz to 108MHz 20MHz to 108MHz 1-time multiplication 200ps (typ) @33MHz 120ps (typ) @75MHz
*1. The modulation rate that can be selected varies with the input frequency.
PINOUT
(Top view)
PACKAGE DIMENSIONS
(Unit: mm)
+ 0.15 − 0.1
0.05
XT VDD VSS CLKOUT
1 2 3 4
8 7 6 5
XTN MSEL1 MSEL0
0.695typ
6.2 ± 0.3
4.4 ± 0.2
TSTN
5.2 ± 0.3
0.05 ± 0.05
1.5 ± 0.1
1.27
0.4 ± 0.2
APPLICATIONS
I I I I I
0.10 0.4 ± 0.1
0 to 10°
0.12 M
Printer (laser/inkjet) Photocopiers, scanners LCD/PDP displays Projectors Miscellaneous electronic equipment
ORDERING INFORMATION
Device SM8761AAS SM8761ABS Package 8-pin SOP
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SM8761 series
BLOCK DIAGRAM
VDD
VSS
XT XTN
X'tal OSC
R Counter
Phase Detector & Charge Pump
LPF
N Counter
(PLL)
VCO
Post Divider
CLKOUT
SS Control
Mode, R/N Counter setting, Divider setting, etc.
SS Control
Control Logic
MSEL0
MSEL1
TSTN
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 Name XT VDD VSS CLKOUT TSTN MSEL0 MSEL1 XTN I/O*1 I PWR GND O Ip I I O Function Crystal oscillator element connection or external clock input Supply voltage Ground SS clock output Test (Tie HIGH or leave open circuit) SS modulation rate setting SS modulation rate setting Crystal oscillator element connection
*1. Built-in pull-up resistor
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SM8761 series
SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage range Input voltage range Output voltage range Power dissipation Storage temperature range Symbol VDD VIN VOUT PD TSTG Rating −0.3 to +6.5 −0.3 to VDD + 0.3 −0.3 to VDD + 0.3 300 −55 to +125 Unit V V V mW °C
Recommended Operating Conditions
SM8761AA VSS = 0V unless otherwise noted.
Rating Parameter Supply voltage range Output load capacitance Symbol VDD CL fIN TOPR CLKOUT output pin Crystal oscillator element connection External clock input Operating temperature range Condition min +3.0 – 20 20 –20 typ – – – – – max +3.6 15 40 MHz 108 +80 °C V pF Unit
Master clock frequency
SM8761AB VSS = 0V unless otherwise noted.
Rating Parameter Supply voltage range Output load capacitance Symbol VDD CL fIN TOPR CLKOUT output pin Crystal oscillator element connection External clock input Operating temperature range Condition min +3.0 – 12 12 –20 typ – – – – – max +3.6 15 32 MHz 32 +80 °C V pF Unit
Master clock frequency
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SM8761 series
ELECTRICAL CHARACTERISTICS
DC Characteristics
SM8761AA VDD = 3.3 ± 0.3V, VSS = 0V, Ta = −20 to +80°C unless otherwise noted.
Rating Parameter Symbol Pins Condition min VDD = 3.3V, Ta = 25°C, external input clock, fin = 33MHz, all outputs unloaded IDD VDD VDD = 3.3V, Ta = 25°C, external input clock, fin = 75MHz, all outputs unloaded – 0.85VDD MSEL0, MSEL1 VDD = 3.3V 0.45VDD – TSTN VDD = 3.3V 0.85VDD – 0.80VDD – – –1 – –100 – –40 VDD – 0.4 – 16 – 0.50VDD – – – – – – – – – – – – – 24 – 0.55VDD 0.15VDD – 0.15VDD – 0.20VDD 1 – 1 – 40 – – V 0.4 µA V – typ 11 max 16 mA Unit
Current consumption
VIH1 VIM1 VIL1 Input voltage VIH2 VIL2 VIH3 VIL3 IIH1 IIL1 Input current IIH2 IIL2 IIH3 IIL3 Output voltage VOH VOL CLKOUT XT TSTN MSEL0, MSEL1 XT
VDD = 3.3V VIN = VDD VIN = 0V VIN = VDD, built-in pull-up resistor VIN = 0V, built-in pull-up resistor VIN = VDD VIN = 0V IOH = −2mA IOL = 2mA
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SM8761 series SM8761AB VDD = 3.3 ± 0.3V, VSS = 0V, Ta = −20 to +80°C unless otherwise noted.
Rating Parameter Symbol Pins Condition min VDD = 3.3V, Ta = 25°C, external input clock, fin = 12MHz, all outputs unloaded IDD VDD VDD = 3.3V, Ta = 25°C, external input clock, fin = 24MHz, all outputs unloaded – 0.85VDD MSEL0, MSEL1 VDD = 3.3V 0.45VDD – TSTN VDD = 3.3V 0.85VDD – 0.80VDD – – –1 – –100 – –40 VDD – 0.4 – 6 – 0.50VDD – – – – – – – – – – – – – 10 – 0.55VDD 0.15VDD – 0.15VDD – 0.20VDD 1 – 1 – 40 – – V 0.4 µA V – typ 5 max 8 mA Unit
Current consumption
VIH1 VIM1 VIL1 Input voltage VIH2 VIL2 VIH3 VIL3 IIH1 IIL1 Input current IIH2 IIL2 IIH3 IIL3 Output voltage VOH VOL CLKOUT XT TSTN MSEL0, MSEL1 XT
VDD = 3.3V VIN = VDD VIN = 0V VIN = VDD, built-in pull-up resistor VIN = 0V, built-in pull-up resistor VIN = VDD VIN = 0V IOH = −2mA IOL = 2mA
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SM8761 series
AC Characteristics
SM8761AA VDD = 3.3 ± 0.3V, VSS = 0V, Ta = −20 to +80°C unless otherwise noted.
Parameter Symbol Pins Condition Crystal connection External clock input*1 CL = 15pF, VOL = 0.2VDD to VOH = 0.8VDD transition time CL = 15pF, VOH = 0.8VDD to VOL = 0.2VDD transition time Cycle-to-cycle jitter, Ta = 25°C, CL = 15pF, VO = 0.5VDD fin = 33MHz fin = 75MHz Rating min 20 20 – – – – 45 – typ – – 2.0 2.0 200 120 50 1 max 40 108 – – – ps – 55 5 % ms Unit
Clock frequency Output clock rise time*2 Output clock fall time*2 Output clock jitter*2 Output clock duty cycle*2 Power-up time*2,*3
fin tr tf tjitter Dt tp
XT CLKOUT CLKOUT
MHz ns ns
CLKOUT CLKOUT CLKOUT
Ta = 25°C, CL = 15pF, VO = 0.5VDD
*1. When using an external clock input, it is recommended that the clock on XT have 50% duty and VDD level signal amplitude. Note that the input signal voltage must not exceed the absolute maximum rating, otherwise it may cause the device to breakdown. *2. Measured using the circuit in Figure 1 on the NPC standard evaluation board. *3. The power-up time is the time from when the supply reaches 3.0V after the supply is turned ON until each output clock reaches its designated frequency to within ± 0.1%.
SM8761AB VDD = 3.3 ± 0.3V, VSS = 0V, Ta = −20 to +80°C unless otherwise noted.
Parameter Symbol Pins Condition Crystal connection External clock input*1 CL = 15pF, VOL = 0.2VDD to VOH = 0.8VDD transition time CL = 15pF, VOH = 0.8VDD to VOL = 0.2VDD transition time fin = 12MHz Output clock jitter*2 tjitter CLKOUT Cycle-to-cycle jitter, Ta = 25°C, CL = 15pF, VO = 0.5VDD fin = 16MHz fin = 20MHz fin = 27MHz Output clock duty cycle*2 Power-up time*2,*3 Dt tp CLKOUT CLKOUT Ta = 25°C, CL = 15pF, VO = 0.5VDD Rating min 12 12 – – – – – – 45 – typ – – 2.0 2.0 450 200 300 180 50 1 max 32 32 – – – – – – 55 5 % ms ps Unit
Clock frequency Output clock rise time*2 Output clock fall time*2
fin tr tf
XT CLKOUT CLKOUT
MHz ns ns
*1. When using an external clock input, it is recommended that the clock on XT have 50% duty and VDD level signal amplitude. Note that the input signal voltage must not exceed the absolute maximum rating, otherwise it may cause the device to breakdown. *2. Measured using the circuit in Figure 1 on the NPC standard evaluation board. *3. The power-up time is the time from when the supply reaches 3.0V after the supply is turned ON until each output clock reaches its designated frequency to within ± 0.1%.
X'tal
+ +
DUT
Active Probe (HP1152A)
Oscilloscope (Infinium HP54845A)
Jitter Measurement System (ASA, M1)
DUT: Device Under Testing Passive Probe (HP10435A)
Frequency & Time Interval Analyzer (HP5371A)
Figure 1. Measurement circuit
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SM8761 series
FUNCTIONAL DESCRIPTION
Master Clock
The SM8761 series master clock can be generated by the crystal oscillator formed by connecting a crystal between XT (pin 1) and XTN (pin 8) as shown in Figure 2. Alternatively, an external master clock can be input directly on XT (pin 1) as shown in Figure 3. If an external clock is input on XT, it is recommended that the clock have 50% duty and VDD level voltage amplitude. Note that the input clock amplitude voltage must not exceed the absolute maximum rating, otherwise it may cause the SM8761 series to breakdown.
C1
XT (Pin1) Oscillator Internal Circuits
C2 C1, C2 = 5 to 33pF
XTN (Pin8)
Figure 2. Crystal element connection
External Clock
XT (Pin1) Oscillator Internal Circuits
Open XTN (Pin8)
Figure 3. External clock input
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SM8761 series
Function Controls
The SM8761 series power-down and SS modulation ON/OFF functions are controlled using the MSEL0 and MSEL1 input pins as shown in Table 1. SM8761AA
MSEL1 (Pin 7) L L L M M M H H H MSEL0 (Pin 6) L M H L M H L M H 50 to 108 (High range) Down spread –1.0 –1.2 20 to 54 (Low range) Down spread Input/Output frequency range [MHz] SS mode SS modulation*1 [%] –2.3 –3.2 −2.8 –1.9 –3.8 –2.5 –1.9
*1. The modulation rates in the table above are reference values at 30MHz to 40MHz (Low range) and 70MHz to 80MHz (High range). The modulation rate varies with the input/output frequency. Note. Signal level “H” represents VDD level, “L” represents VSS level, and “M” represents 1/2VDD.
SM8761AB
MSEL1 (Pin 7) L L L M M M H H H MSEL0 (Pin 6) L M H L M H L M H 18 to 32 (High range) Center spread (reserved)*2 ± 2.25 ± 1.25 ± 0.75 ± 1.75 12 to 18 (Low range) Center spread Input/Output frequency range [MHz] SS mode SS modulation*1 [%] ± 1.25 ± 0.75 ± 1.75 ± 2.25
*1. The modulation rates in the table above are reference values at 12MHz (Low range) and 24MHz (High range). The modulation rate varies with the input/output frequency. *2. If MSEL1 (pin 7) and MSEL0 (pin 6) are both simultaneously "M" level, then SM8761AB operation cannot be guaranteed. Note. Signal level “H” represents VDD level, “L” represents VSS level, and “M” represents 1/2VDD.
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SM8761 series
Typical Connection Circuit
A typical connection circuit diagram is shown in Figure 4. 1) The SM8761 series oscillator circuit between XT and XTN has a built-in feedback resistor (approximately 250kΩ). 2) The oscillator circuit capacitances C101 and C102 connected to XTN and XT, to match the crystal load capacitor. 3) If using an external clock input on XT, then connections to XT and XTN should be as shown in figure 3. 4) R201 is impedance matching resistor for board pattern. 5) C201 and C202 are bypass capacitors inserted between the supply voltage lines. C201 is a 0.1µF (approximately) multi-layer ceramic capacitor connected directly alongside the SM8761 series. C202 is a 33µF (approximately) electrolytic capacitor.
C101 VSS X'tal VDD XT C202 33µF C201 0.1µF
+
C102 VSS
XTN MSEL1 MSEL0 TSTN IC1 SM8761 MSEL1 MSEL0
VDD VSS
VSS Application Load R201 0 to 22Ω
CLKOUT
VSS
Note. This is a sample connection diagram only, and its use is not a guarantee of SM8761 series device characteristics.
Figure 4. Typical connection circuit
MSEL1 and MSEL0 Connection Method
MSEL1 and MSEL0 both support a 1/2VDD "M" level for 3-value ("H", "M", "L") DC voltage input control. Typical connection circuits for each input level shown in figure 5. "H" level is input by connection to VDD, and "L" level by connection to VSS. "M" level is input by connection to the center tap of two identical resistances in series between VDD and VSS. The recommended resistance is 4.7kΩ.
VDD VDD
R301 4.7kΩ XTN MSEL1 MSEL0 TSTN XTN MSEL1 MSEL0 TSTN R302 4.7kΩ XTN MSEL1 MSEL0 TSTN
VSS
VSS
(a)“H” level
(b)“M” level Figure 5. MSEL1 and MSEL0 typical connections
(c)“L” level
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SM8761 series
CLKOUT Output Spectrum Sample (SM8761AA)
A sample SM8761AA CLKOUT output spectrum is shown in Figure 6.
MKR:33.200MHz 9.37dBm RL:10.0dBm 10dB/AT30dB
W:A ST 3s D:PK
CNF:33.2MHz
SPF:3.3MHz
RB3kHz
VB1kHz
(a) NPC test mode: SS OFF, fin = 33.2MHz
MKR:32.434MHz −5.19dBm RL:10.0dBm 10dB/AT30dB
W:A ST 3s D:PK
CNF:33.2MHz
SPF:3.3MHz
RB3kHz
VB1kHz
(b) MSEL1 = "L"/ MSEL0 = “H”: down spread –2.8%, fin = 33.2MHz Figure 6. Output spectrum sample
Note. The output spectrum sample in figure (a) is for NPC test mode with the SS function OFF. Note. These spectrum diagrams were obtained using the NPC evaluation board. These spectrum diagrams are not guaranteed SM8761 series device characteristics.
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SM8761 series
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NC0408AE 2004.12
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