SM9403BM

SM9403BM NIPPON PRECISION CIRCUITS INC. DVDRAM Servo-amplifier LSI OVERVIEW The SM9403BM is a DVDROM and DVDRAM servo preprocessor LSI, designed for double-speed format DVDROM and DVDRAM drives. The SM9403BM is fabricated using a BiCMOS process, and incorporates an analog signal processing circuit that generates signals needed by the digital servo processor, a DPD signal processing circuit (DVDROM), and a CAPA (Complementary Allocated Pit Address) detection circuit (DVDRAM) all in a single chip. It operates from a single 5 V supply, and is available in 36-pin plastic SSOP packages. FEATURES s s s s s s s s s s s s s PINOUT 36-pin SSOP (Top View) DPD signal processor Tracking error signal output Focus error signal output Tracking error signal sample-and-hold Focus error signal sample-and-hold CAPA detection function Track count pulse generator Off-track detection 2V and 4V reference voltage generator Serial interface for setting internal parameters Sleep-mode function Single 5 V supply 36-pin plastic SSOP NC NC FER FHOLD FSUB ISET DPDD DPDC DPDB DPDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 DPDG DPDI DEFECT DGND SCLK SDATA SENB DVCC CAPSEEK CAPSEL CAPIN AVCC CAPOUT CAPAREA TRP TROFF VREF2 VREF4 SM9403BM NPC APPLICATIONS s s AGND MMTI Double-speed DVDROM drives Double-speed DVDRAM drives CAPAN CAPAP CAPLFC ORDERING INFORMATION D e vice SM9403BM P ackag e 36-pin SSOP TSUB THOLD TRE NIPPON PRECISION CIRCUITS—1 S M9403BM PACKAGE DIMENSIONS (Unit: mm) 15.20 to 15.40 0.85 0.63 ± 0.10 0 to 8° 7° 7.40 to 7.60 R0.63 to 0.89 0.51 ± 0.20 45° 0.51 to 1.01 0.23 to 0.32 0.29 to 0.39 0.80 0.10 to 0.30 2.44 to 2.64 BLOCK DIAGRAM DEFECT FSUB DPDA DPDB S/H LPF * Equalizer Delay Phase comparator Voltage reference Serial interface LPF DVCC DGND SCLK SDATA SENB DPDC DPDD ISET SWB TSUB S/H * THOLD * CAPAP CAPAN Analog signal processor Mono-multiviblator S/H control LPF SWA Track Pulse Generator TRE TRP TROFF VREF2 NIPPON PRECISION CIRCUITS—2 10.11 to 10.51 7° FHOLD CAPLFC VREF4 VREF2 AGND DPDG AVCC DPDI FER MMTI CAPIN CAPOUT CAPAREA CAPSEL CAPSEEK S M9403BM PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name NC NC FER FHOLD FSUB ISET DPDD DPDC DPDB DPDA AG N D MMTI C A PA N C A PA P CAPLFC TSUB THOLD TRE VREF4 VREF2 TROFF TRP C A PA R E A CAPOUT AV C C CAPIN CAPSEL CAPSEEK DV C C SENB S D ATA SCLK DGND DEFECT DPDI DPDG I/O 1 O O O – I I I I I I – I I I – I – O O O O O O O – O Ipd Ipd – I I/O I – Ipd I I No connection No connection Focus error signal output Focus error hold capacitor connection Focus error signal input DPD signal equalizer, reference current set resistor connection DPD signal input D DPD signal input C DPD signal input B DPD signal input A Analog circuit ground M o n o - m ultivibrator time-constant set resistor connection ID data signal differential inverting input ID data signal differential non-inverting input Slice-level detect capacitor connection Tracking error signal input Tracking error hold capacitor connection Tracking error signal output 4V reference voltage output 2V reference voltage output Off-track detect signal output. LOW when off-track. Track count pulse output. HIGH-level pulse for land to outer tracking. ID interval detect signal output. ID interval detected when HIGH. Outer offset ID detect signal output. Outer offset ID interval detected when HIGH. Analog circuit pow er supply Inner offset ID detect signal output. Inner offset ID interval detected when HIGH. ID interval signal input. ID interval selected when HIGH. Seek operation signal input. Seek operation selected when HIGH. Logic circuit pow er supply Serial interface enable input. Enabled when HIGH. Serial interface data input/acknowledge output Serial interface clock input Logic circuit ground Defect position signal input. Defect position indicated when HIGH. DPD signal hold delay set resistor connection DPD signal phase difference to voltage converter coefficient set resistor connection F unction 1 . I = input, Ipd = Input with built-in pull-down resistor, I/O = input/output (N-channel open-drain when output), O = output NIPPON PRECISION CIRCUITS—3 S M9403BM SPECIFICATIONS Absolute Maximum Ratings GND = 0 V P arameter S upply voltage range Input voltage range Operating temperature range Storage temperature range Pow er dissipation Soldering temperature Soldering time Symbol VCC V IN T o pr T s tg PD T s ld ts ld Condition Rating −0 .5 to 7.0 − 0 .5 to V C C + 0 .5 0 t o 70 −4 0 to 125 2 50 2 60 10 Unit V V °C °C mW °C s Recommended Operating Conditions GND = 0 V P arameter S pecifications supply voltage range Operating supply voltage range Operating temperature range Symbol VCC VCC T o pr Condition Rating 4 .75 to 5.25 4 .5 to 5.5 0 t o 70 Unit V V °C Recommended External Components P in No. 4 6 12 15 17 19 20 35 36 Pin name FHOLD ISET MMTI CAPLFC THOLD VREF4 VREF2 DPDI DPDG Component 1000pF capacitor 47k Ω r esistor 0.01µF capacitor 120k Ω r esistor 0.01µF capacitor 1000pF capacitor 0.1µF capacitor 0.1µF capacitor 47k Ω r esistor 33k Ω r esistor Tolerance K (±10%) ±1% Z (+80% to −2 0 % ) ±1% Z (+80% to −2 0 % ) K (±10%) Z (+80% to −2 0 % ) Z (+80% to −2 0 % ) ±1% ±1% NIPPON PRECISION CIRCUITS—4 S M9403BM DC Electrical Characteristics VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Symbol IC C 1 IC C 2 C urrent consumption 1 IC C 3 IC C 4 ∆I C C C A P S E E K , C A P S E L , D E F E C T, SENB, SDATA, SCLK HIGH-level input voltage C A P S E E K , C A P S E L , D E F E C T, SENB, SDATA, S C L K L OW -level input voltage C A P S E E K , C A P S E L , D E F E C T H I G H - l evel input current S E N B , SDATA, SCLK HIGH-level input current C A P S E E K , C A P S E L , D E F E C T, SENB, SDATA, S C L K L OW -level input current C A PA R E A , C A P I N , C A P O U T, T R P, T R O F F HIGH-level output voltage C A PA R E A , C A P I N , C A P O U T, T R P, T R O F F L O W -level output voltage S D ATA L OW -level output voltage V IH V IL II H1 II H2 II L VOH VOL1 VOL2 V IN = V C C V IN = V C C V IN = G N D I O H = −0 . 2 m A IO L = 0 .8mA IO L = 7 mA Condition min O perating mode S leep mode 1 S leep mode 2 S leep mode 3 IC C 1 − IC C 2 – – – – 9 0 .8V C C – 50 – −3 V C C − 0 .2 – – typ 28 17 2.0 – – – – 100 – – – – – max 34 21 2.6 1.0 – – 0.2V C C 200 3 – – 0.4 1.0 V V µA µA µA V V V mA Unit 1 . 33k Ω r esistor connected between DPDG and AG N D 47k Ω r esistor connected between DPDI and AG N D 120k Ω r esistor connected between MMTI and AG N D 47k Ω r esistor connected between ISET and AG N D 1000pF capacitor connected between FHOLD and AG N D 1000pF capacitor connected between T H O L D a n d AG N D 0.1µF capacitor connected between VREF4 and AG N D 0.1µF capacitor connected between VREF2 and AG N D 0.01µF capacitor connected between CAPLFC and AG N D 0.01µF capacitor connected between ISET and AG N D C A PA P, CAPA N , D P DA , D P D B, D P D C, D P D D, FSUB, TSUB connected to VREF2 or other 2V supply. S E N B , SDATA, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit. Sleep mode 1: DPD system only in sleep condition. Sleep mode 2: All blocks except reference supply voltage generator in sleep condition. Sleep mode 3: All blocks in sleep condition. NIPPON PRECISION CIRCUITS—5 S M9403BM Focus Sample-and-Hold, Low-pass Filter Characteristics (FSUB → FER) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C, FSUB and FER signals in phase Rating P arameter F SUB input signal range FER output voltage range FER output offset voltage FER output offset voltage temperature drift FER output signal slew rate FER output load regulation FSUB input impedance F ER output signal gain FER output signal bandwidth 1 FER output gain peaking 1 Hold time FER output droop characteristic S/H acquisition time FER output hold error Pow er-down state FER output impedance 1 . C L = 2 0pF, R L = 5 00 Ω V I N = 1 .5Vp-p, −3 dB from DC LPF off (FFE = HIGH) LPF on (FFE = LOW ) Condition min VREF2 reference VREF2 reference VREF2 reference, V I N = V R E F 2 VREF2 reference LPF off IO U T = ± 3mA, V I N = V R E F 2 −1 .25 −1 .25 – – 1 – 100 −0 .17 500 115 −3 – – – 1 typ 0 0 – – – – – 0 – 160 – – – – – max +1.25 +1.25 ±8.0 ±45 – ±10 – +0.17 – kHz 230 +0.5 0.025 1 ±4 – dB %/µs µs mV MΩ V V mV µV/ °C V/µs mV kΩ dB Unit D C to −3 dB frequency V I N = 2 00mVp-p, C F H O L D = 1 000pF ∆V I N = 2 00mV, target value ± 10% With respect to the previous value Tracking Sample-and-Hold, Low-pass Filter Characteristics (TSUB → TRE) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C, TSUB and TRE signals in phase Rating P arameter T SUB input signal range TRE output voltage range TRE output offset voltage TRE output offset voltage temperature drift TRE output load regulation TSUB input impedance T RE output signal gain TRE output signal bandwidth 1 TRE output gain peaking 1 Hold time TRE output droop characteristic S/H acquisition time TRE output hold error Pow er-down state TRE output impedance 1 . C L = 2 0pF, R L = 5 00 Ω V I N = 1 .5Vp-p, −3 dB from DC TFE = HIGH TFE = LOW Condition min VREF2 reference VREF2 reference VREF2 reference, V I N = V R E F 2 VREF2 reference IO U T = ± 3mA, V I N = V R E F 2 −1 .25 −1 .25 – – – 100 −0 .17 24 115 −3 – – – 1 typ 0 0 – – – – 0 35 160 – – – – – max +1.25 +1.25 ±8.0 ±45 ±10 – +0.17 50 kHz 230 +0.5 0.025 1 ±4 – dB %/µs µs mV MΩ V V mV µV/ °C mV kΩ dB Unit D C to −3 dB frequency V I N = 2 00mVp-p, C T H O L D = 1 000pF ∆V I N = 2 00mV, target value ±10% With respect to the previous value NIPPON PRECISION CIRCUITS—6 S M9403BM DPD Error Signal Detector Characteristics (DPDA/DPDB/DPDC/DPDD → TRP) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C P arameter 1 D P D A/DPDB/DPDC/DPDD input voltage range D P D A/DPDB/DPDC/DPDD input impedance Signal gain relative accuracy Gain relative to DPDA , D P D B, D P D C, DPDD inputs D G 2 = L OW 1MHz setting DG2 = HIGH Equalizer gain D G 2 = L OW 5MHz setting DG2 = HIGH Peak gain frequency (EQE = HIGH) Equalizer frequency response Equalizer frequency response relative accuracy A C coupling time circuit −3dB frequency A C coupling time constant relative accuracy Delay control range Phase difference detector minimum time Phase difference detector maximum time Phase difference detector minimum repeat time Phase difference to voltage conversion coefficient Phase difference to voltage conversion coefficient change accuracy Phase difference output offset voltage Phase difference output offset voltage temperature drift DEFECT signal response time D P D e n a ble response time Abnor mal waveform TRP droop characteristic TRP output voltage range TRP output signal frequency response DPE flag V O U T = V R E F 2 ± 2 00mV, VREF2 reference VREF2 reference −3dB frequency VREF2 reference VREF2 reference −3dB frequency (EQE = LOW ) fpeak , (A + C) vs. (B + D) Time constant 1 Time constant 2 D G 2 = L OW DG2 = HIGH 6.1 3.75 11 – 56 17 – 6.7 5.0 22 – 84 24 – See table 4. 2 – 120 – – – – – – – −1.25 500 – – – See table 5. See table 8. – – – – – 0 – – 1 – typ ± 20% ±1 ±0.1 ±570 1 2 0.1 +1.25 – 7.2 6.25 MHz 33 ±1.5 109 kHz 32 ±2 % ns ns µs ns mV/ns dB V µV/ °C µs µs %/µs V kHz −3dB frequency, (A + C) vs. (B + D) See table 4. DG1 = DG2 = LOW DG1 = DG2 = HIGH Input pulse interval DG1 = DG2 = LOW % 5.5 6.1 6.6 1.8 2.2 2.9 dB Rating Condition min VREF2 reference −0.55 1 – 1.2 typ – – – 1.6 max +1 – ±0.17 2.3 V MΩ dB Unit 1. The tracking error signal TRE is positive with respect to VREF2 if the (DPDA + DPDC) signal phase difference is leading. The detected phase difference is the difference between the point when one internal comparator output changes (from CMA and CMB both HIGH or both LOW) until the second output changes before the first changes again. The phase difference is conver ted to a voltage and sampled for output. Other signals are held constant in the output stage when a phase difference is detected. NIPPON PRECISION CIRCUITS—7 S M9403BM Header Position Detector Characteristics (CAPAP/N → CAPAREA, CAPIN, CAPOUT) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter C A PAP/N input voltage range Analog signal processor frequency response Analog signal quantization slice level M o n o - m ultivibrator time constant M o n o - m ultivibrator time constant switching accuracy M o n o - m ultivibrator time-constant block interval accuracy C A P I N , C A P O U T, CAPAREA output rise time and fall time C L = 2 0pF V IN = V R E F 2 ± 0 .5V, −3dB from DC Condition min 1 13 – typ − 5 % – – – typ – – See table 9. See table 10. – – – max 3 – typ ± 15% typ + 45% ±5 ±2.5 15 V MHz V µs % % ns Unit Sample-and-Hold Control Signal Generator Characteristics VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Condition min M o n o - m ultivibra t o r / C A P S E L / C A P S E E K → FSHCNT/TSHCNT Serial interface (HRE, FHE, THE, HAE) → FSHCNT/TSHCNT – – typ – – max 100 2 ns µs Unit FER, TRE output response time 1 1. F S H C N T a n d TSHCNT are the focus and tracking sample-and-hold internal control signals, respectively. Tracking Error Signal Switching Characteristics (SWA, SWB) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Switching response time Condition min Serial interface timing – typ – max 1 µs Unit NIPPON PRECISION CIRCUITS—8 S M9403BM Track Count Pulse Generator Characteristics (TSUB → TRP, TROFF) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter TSUB input signal range TSUB signal limiter voltage level TSUB signal amplifier gain Quantization level offset set value TRP output comparator hysteresis 1 Minimum hysteresis, target value ± 10% Minimum ↔ m aximum hysteresis value Condition min VREF2 reference VREF2 reference f = 5kHz −1.25 ±1.0 5.83 typ − 1 5 % typ − 1 0 % – – typ − 1 0 % Minimum ↔ m aximum window value – typ – – 6.0 See table 15 See table 16 – – See table 17 – max +1.25 – 6.17 typ + 15% typ + 10% 600 2 typ + 10% 5 V V dB mV mV ns µs mV µs Unit TRP output comparator hysteresis response time TRP output comparator hysteresis switching response time T R OFF output comparator window T R OFF output comparator window switching response time 1. TRP has the same polarity as TRE (i.e. TRP is HIGH when TRE > VREF2). T R OFF is HIGH when the input signal is inside the window , and LOW when outside the window . Reference Voltage Generator Characteristics (VREF2, VREF4) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter VREF4 output voltage VREF2 output voltage VREF4 output voltage temperature drift VREF2 output voltage temperature drift VREF4 output voltage supply voltage dependency VREF2 output voltage supply voltage dependency VREF4 output voltage load regulation VREF2 output voltage load regulation Relative output voltage accuracy 1 Condition min V C C = 5 V, T a = 2 5 °C , IO U T = 0 3.84 1.92 – – – V C C = 5 V ± 5%, T a = 2 5 °C , IO U T = 0 – V C C = 5 V, T a = 2 5 °C V C C = 5 V, IO U T = 0 V C C = 5 V, T a = 0 t o 70 °C , IO U T = 0 V C C = 5 V ± 5%, T a = 2 5 °C , IO U T = 0 IO U T = 0 t o 8mA IO U T = 0 t o ±5mA – – – – – 13 1 – – – – – – – – ±3 −20 ±10 ±20 ±10 ±1 – – mV mV mV mV µV/ °C mV kΩ MΩ typ 4.0 2.0 – – – max 4.16 2.08 ±400 ±200 ±6 V V µV/ °C µV/ °C mV Unit V C C = 5 V, T a = 0 t o 70 °C , IO U T = 0 Relative output voltage temperature drift Relative output-voltage supply-voltage dependency V R E F 4 p ow er-down output impedance V R E F 2 p ow er-down output impedance 1. D e fi ned as (VREF2 − ( VREF4 ÷ 2)). NIPPON PRECISION CIRCUITS—9 S M9403BM Serial Interface Characteristics (SCLK, SDATA, SENB) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter SCLK pulse cycle SCLK HIGH-level pulsewidth S C L K L OW -level pulsewidth SENB setup time SENB hold time S D ATA setup time S D ATA hold time A CK setup A CK hold time 1 Symbol tc y S C K tw h S C K tw l S C K ts S E N th S E N ts S DA th S D A ts AC K th AC K ti n S E N Condition min 100 40 40 20 40 15 15 0 – 100 typ – – – – – – – – – – max – – – – – – – 20 50 – ns ns ns ns ns ns ns ns ns ns Unit time 1 SENB inter val 1. A CK is the acknowledge output (n-channel open-drain). LOW -level output when the data received is valid. S D ATA load capacitance is 15pF. tinSEN SENB tsSEN twhSCK twlCLK tcySCK SCLOCK tsSDA thSDA SDATA Controller SDATA Port bit 0 LSB bit 1 bit 15 MSB ACK High Impedance tsACK thSEN thACK NIPPON PRECISION CIRCUITS—10 S M9403BM FUNCTIONAL DESCRIPTION Serial Interface The SM9403BM uses a serial interface comprising 5 ports to control and set all functions. The address and bit configuration of each port is shown in table 1 Table 1. Port address and bit configuration1 Bit nu m b e r 15 14 13 12 Data MSB DPE OF3 THE EQE TS3 HAE OF2 FHE CG3 TS2 FFE OF1 HRE CG2 TS1 TFE WD2 MM2 CG1 – SWB WD1 MM1 DL4 – SWA HS3 LS3 DL3 – SL2 HS2 LS2 DL2 DG2 SL1 HS1 LS1 DL1 DG1 × × × × × LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH LOW LOW HIGH LOW HIGH LOW HIGH LOW × × × × × 11 10 9 8 7 6 5 4 3 2 1 0 A d dress LSB × × × × × 1. × = d on’t care, – = unassigned Serial data is input on SDATA with the LSB first, in sync with the falling edge of the SCLK clock. After the 16th SCLK falling edge and 16 bits of valid data has been input, the SDATA n-channel open-drain output goes LOW as an acknowledge signal. If the number of SCLK cycles which occur when SENB (serial interface enable) is HIGH is less than 16, the received data is ignored and the internal port is not updated. If the number of SCLK cycles is greater than 16, the data is still considered value up to the 16th SCLK falling edge, the data is latched into the internal port, and the acknowledge signal is output. The acknowledge signal is held until SENB goes LOW again. Focus Sample-and-Hold/Low-pass Filter (FSUB → FER) This stage, the signal which is generated from the header position detector signal samples and holds the focus error signal. The output then passes through a low-pass filter. This low-pass filter can be turned ON or OFF using the serial interface control bit FFE. Table 2. Focus low-pass filter ON/OFF control FFE LOW HIGH 1. Default is ON L o w-pass filter 1 ON OFF Tracking Sample-and-Hold/Low-pass Filter (TSUB → TRE) This stage, the signal which is generated from the header position detector signal samples and holds the tracking error signal. The output then passes through a low-pass filter. This low-pass filter cutoff frequency can be switched using the serial interface control bit TFE. Table 3. Tracking low-pass filter cutoff frequency TFE LOW HIGH 1. Default is 160kHz L o w-pass filter 1 fC = 1 60kHz fC = 3 5kHz NIPPON PRECISION CIRCUITS—11 S M9403BM DPD Error Signal Detector (DPDA/DPDB/DPDC/DPDD → TRP) This stage compares the DPD signals, passes the comparator output through a low-pass filter to obtain the DPD tracking error signal. The DPD signals are first added, (DPDA + DPDC) and (DPDB + DPDD), then passed to an equalizer. A relative time delay is added for offset correction. The signals are then converted to a pulse waveform by comparators with hysteresis characteristics. The phase comparator then compares the phase of the pulse waveforms to obtain a time signal equivalent to the tracking error. The time signal is then converted to a voltage. The converted voltage is passed to the output stage, undergoes sampling timing compensation before being integrated to generate the tracking error signal output. The phase comparator incorporates a detector function which prevents abnormal waveform signals getting to the output by holding the output constant. In addition, serial interface control bit DPE and input DEFECT can be used to force the tracking error signal to the reference voltage VREF2. These controls can be used when powering up a system or to prevent output saturation from occurring during periods when the input signal is unstable. The relative time delay setting and time-to-voltage conversion coefficient can be controlled using serial interface control bits. Also, the equalizer used to compensate for the previous stage can be turned ON or OFF using serial interface control. NIPPON PRECISION CIRCUITS—12 S M9403BM Table 4. DPD delay time settings DPD delay (ns) 1 DG2 DG1 DL4 LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW LOW HIGH +17 +14 +12 +10 +7.5 +5.6 +3.7 +2.0 0 −3.8 −7.0 −11 −16 −20 −26 −34 +44 +33 +25 +20 +15 +10 +7.0 +3.6 +24 +20 +17 +13 +11 +7.7 +5.5 +3.0 0 −4.5 −8.5 −13 −18 −23 −30 −38 +49 +37 +29 +22 +17 +12 +7.9 +4.3 +29 +23 +19 +15 +13 +9.0 +6.2 +3.4 0 −6.0 −11 −17 −24 −32 −42 −55 HIGH HIGH HIGH LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW LOW HIGH +74 +52 +38 +29 +22 +17 +11 +5.6 HIGH LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW LOW HIGH +124 +108 +80 +58 +42 +29 +18 +9.0 +167 +120 +88 +65 +47 +33 +21 +10 +210 +194 +130 +90 +64 +45 +31 +16 DL3 LOW LOW LOW LOW DL2 LOW LOW DL1 min LOW HIGH 0 −2.2 −4.2 −6.0 −7.5 −10 −12 −14 typ 0 −3.0 −5.6 −8.0 −11 −14 −17 −20 max 0 −3.3 −6.4 −9.5 −13 −16 −20 −24 HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW LOW HIGH +90 +70 +55 +42 +31 +22 +14 +7.2 0 −9.5 −19 −30 −42 −60 −80 +100 +78 +61 +47 +36 +26 +17 +8.2 0 −11 −22 −35 −48 −67 −90 −122 +136 +102 +76 +60 +45 +34 +23 +12 0 −17 −32 −49 −74 −105 −150 −205 LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH DG2 DG1 DL4 DL3 DL2 DL1 min 0 −7.0 −15 −22 −32 −43 −55 −70 typ 0 −8.5 −17 −27 −37 −48 −62 −78 max 0 −13 −24 −36 −50 −65 −83 −108 Table 4. DPD delay time settings (Continued) DPD delay (ns) 1 HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH HIGH LOW HIGH HIGH HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH LOW LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH HIGH LOW HIGH HIGH HIGH HIGH HIGH LOW H I G H H I G H H I G H −110 HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH 1. Default is 0 ns (DL4 = DL3 = DL2 = DL1 = LOW ) The DPD delay is positive when (A+C) leads (B+D). NIPPON PRECISION CIRCUITS—13 S M9403BM Table 5. Phase difference to voltage converter coefficient CG3 LOW LOW LOW LOW HIGH HIGH HIGH HIGH CG2 LOW LOW HIGH HIGH LOW LOW HIGH HIGH CG1 LOW HIGH LOW HIGH LOW HIGH LOW HIGH C o e f fi cient (mV/ns) 1 5.38 7.58 10.7 15.2 21.4 30.3 42.7 60.6 1. Default is 15.2 mV/ns Table 6. Equalizer control EQE LOW HIGH 1. Default is OFF Equalizer 1 OFF ON Table 7. DPD output control DPE LOW × HIGH DEFECT × HIGH LOW DPD output 1 Forced to V R E F 2 Forced to V R E F 2 Active 1. Default is VREF2 (DPE = LOW ) Table 8. DPD delay time coefficient, phase difference to voltage converter coefficient, AC coupling time constant DG2 DG1 Phase to voltag e coefficient (relative to values in table 5) 1 ×1 × 1 /2 × 1 /4 × 1 /8 25 kHz 1-times CD 100 kHz 4-times CD 2-times CD D P D - AC coupling time constant circuit −3dB frequency Selected media LOW LOW HIGH HIGH LOW HIGH LOW HIGH 8-times CD, DV D - R A M 1. Default is DG2 = DG1 = LOW NIPPON PRECISION CIRCUITS—14 S M9403BM Header Position Detector (CAPAP/N → CAPAREA, CAPIN, CAPOUT) This stage converts a high-speed push-pull signal (CAPAP/CAPAN) to single-ended signals, passes the outputs through low-pass filters to form quantized logic levels which are used as reference signals. These reference signals are level shifted to form plus and minus signals for use by comparators. The amount of level shift can be controlled by serial interface control bits. After quantization logic conversion, retriggerable mono-multivibrators convert the pulse strings to continuous signals. This creates inner shifted header CAPIN and an outer shifted header CAPOUT output signals. In addition, the single-ended signal is also passed through a high-pass filter, which similarly converts to quantized logic signals. Retriggerable mono-multivibrators then convert the pulse strings to continuous signals to create a header area CAPAREA signal. The mono-multivibrator time constants are controlled by serial interface control bits. Table 9. Slice level shift voltages LS3 LOW LOW LOW LOW HIGH HIGH HIGH HIGH 1. Default is ±25 mV LS2 LOW LOW HIGH HIGH LOW LOW HIGH HIGH LS1 LOW HIGH LOW HIGH LOW HIGH LOW HIGH L evel shift (mV) 1 ±25 ±50 Table 11. CAPOUT/CAPIN/CAPAREA logic C A PA R E A LOW LOW ±75 ±100 ±125 ±150 1. Default is LOW ±200 ±250 HIGH LOW Header signal output Header signal output Header signal output Header signal output HAE1 CAPOUT Header signal output LOW CAPIN Header signal output LOW LOW HIGH HIGH HIGH Table 10. Mono-multivibrator time constants MM2 LOW LOW HIGH HIGH MM1 LOW HIGH LOW HIGH CAPOUT/CAPIN output (µs) 1 4 8 12 16 C A PAREA (µs) 1 8+α 16 + α 24 + α 32 + α 1. Default is 4 µs and (8 + α), where α ≈ 6 × l n(2V L S /V H ), V H = i nput signal amplitude, V L S = s lice level absolute value shown in table 9. NIPPON PRECISION CIRCUITS—15 S M9403BM Sample-and-Hold Control Signal Generator This stage takes the OR-logic of the CAPIN and CAPOUT signals, generated by the header position detector, the CAPSEL and CAPSEEK input signals, and the serial interface control bit HRE and uses them to create a sample-and-hold circuit control signal SHCNT. Table 12. Sample-and-hold logic CAPIN HIGH × LOW HIGH × × × 1. Default is LOW × = d on’t care. CAPOUT × HIGH LOW × HIGH × × CAPSEL × × × × × HIGH LOW CAPSEEK LOW LOW LOW LOW LOW HIGH HIGH HRE1 HIGH HIGH × LOW LOW × × SHCNT HIGH HIGH LOW LOW LOW HIGH LOW The SHCNT is then used in conjunction with serial interface select bits FHE and THE to form the focus sample-and-hold (FSHCNT) and tracking sampleand-hold (TSHCNT) signals. Table 13. Sample-and-hold signal control logic FHE1 LOW × HIGH × THE1 × LOW × HIGH FSHCNT2 LOW × SHCNT × TSHCNT2 × LOW × SHCNT 1. Default is LOW 2. FSHCNT is the focus sample-and-hold control signal, and T S H C N T i s the tracking sample-and-hold control signal. × = d on’t care. Tracking Error Signal Switching (SWA, SWB) This stage performs tracking error signal switching during DVDRAM write/read and DVDROM and CD Table 14. Tracking error signal select S WA LOW HIGH 1. Default is S/H SWB LOW HIGH Tracking error signal select 1 S/H DPD playback. Switching is controlled by serial interface control bits. NIPPON PRECISION CIRCUITS—16 S M9403BM Track Count Pulse Generator (TSUB → TRP, TROFF) This stage filters the tracking error signal through a 6th-order Butterworth low-pass filter which effectively filters off header signal leakage effects. An offset voltage is added and the signal passes through a comparator with hysteresis to generate a track count pulse signal output on TRP. Simultaneously, the window comparator corresponding to the tracking error signal is output as the off-track signal on TROFF (LOW for off-track). The offset voltage, hysteresis level and window width are controlled by serial interface bits. Table 15. Offset voltage setting OF3 LOW LOW LOW LOW HIGH HIGH HIGH HIGH 1. Default is 0 mV OF2 LOW LOW HIGH HIGH LOW LOW HIGH HIGH OF1 LOW HIGH LOW HIGH LOW HIGH LOW HIGH Offset voltag e (mV) 1 0 −200 −400 −600 +800 +600 +400 +200 LOW LOW HIGH HIGH 1. Default is ±125 mV LOW HIGH LOW HIGH Table 16. TRP comparator hysteresis HS3 LOW LOW LOW LOW HIGH HIGH HIGH HIGH HS2 LOW LOW HIGH HIGH LOW LOW HIGH HIGH HS1 LOW HIGH LOW HIGH LOW HIGH LOW HIGH Hysteresis (mV) 1 ±100 ±200 ±300 ±400 ±500 ≥ 5 00 ≥ 5 00 ≥ 5 00 1. Default is ±100 mV Table 17. TROFF comparator window WD2 WD1 Comparator w i n d ow (mV) 1 ±125 ±250 ±375 ±475 Sleep Mode The SM9403BM features 3 sleep modes which can be used when the device is not operating to signifiTable 18. Sleep mode settings SL2 LOW LOW HIGH HIGH SL1 LOW HIGH LOW HIGH Mode description 1 Sleep mode OFF (nor mal operation) DPD in sleep condition All except reference voltage supply in sleep condition All blocks in sleep condition cantly reduce current consumption. The sleep modes are controlled by serial interface bits. 1. Default is OFF (SL2 = SL1 = LOW ) Preset Function When power is applied or in sleep modes 2 and 3, all serial interface flags are reset to their default values with the exception of the sleep mode flags SL2 and SL1 (see the section “Serial Interface”). However, when writing data to SL2 and SL1 to cancel sleep mode, other flags in the same data word have precedence when writing to the port. NIPPON PRECISION CIRCUITS—17 S M9403BM NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9813AE 1999.09 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—18