SM9501B

SM9501B Radio Controlled Clock Receiver IC OVERVIEW *1: Radio controlled clock FEATURES I I I PINOUT (Top view) pre lim ina I I I I I I I Operating supply voltage range: 4.5 to 5.5V Operating current consumption: 55µA (typ) @5V Standby current consumption: 0.1µA (max) @5V High sensitivity: 0.5µVrms input Wide frequency range (35kHz to 80kHz) Include analog switch for antennatuning capacitors change AGC gain hold function External crystal filter connection BiCMOS process Package:16-pin VSOP ORDERING INFORMATION Device Package SM9501BV 16-pin VSOP PACKAGE DIMENSIONS (Unit: mm) 4.4 ± 0.2 6.4 ± 0.2 0.275TYP 5.1 ± 0.2 0.10 + 0.1 0.22 − 0.05 0.12 M SEIKO NPC CORPORATION —1 0.10 ± 0.05 0.65 1.15 ± 0.1 0 to 10 ° 0.5 ± 0.2 ry VDDA IN1 IN3 IN2 1 16 The SM9501B is a BiCMOS RCC*1 receiver IC. It accepts low frequency standard wave input received from an external antenna, amplifies it, detects the data signal, and outputs a digital time code signal. VDD PON OUT VSS HLDN CP CB LF FCN XO VSSA XI 8 9 + 0. 0.15 − 1 0.05 SM9501B BLOCK DIAGRAM PON OUT VSS HLDN CP CB VDD VDDA Bias IN1 AGC Amp IN3 IN2 FCN XO VSSA XI PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 Name lim I/O1 − I I I A/D2 A IN1 IN3 IN2 A A A Ipu O − I D A XO A XI A LF O A CB CP O O A A Ipu − D A VSS O D Ipu − D A (+) supply input TN Ipu D VDDA FCN pre 10 11 12 HLDN 13 14 15 OUT PON VDD 16 − 1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin 2. A: analog signal, D: digital signal VSSA ina ry Decoder Peak/Bottom Hold Det. AGC Control Post Amp Rectifier LPF LF Description AGC amplifier (+) supply input Antenna input 1 (fixed input) Antenna input 3 (via analog switch) Antenna input 2 (analog switch bypass) Analog switch control input (active LOW) Output for crystal filter AGC amplifier (–) supply input Input from crystal filter Rectifier LPF capacitor connection Bottom hold detector capacitor connection Peak hold detector capacitor connection AGC gain hold control (active LOW) Substrate (–) supply input Clock time code output (active LOW) Standby state control input (active LOW) AGC amplifier gain control switch (active LOW, for test mode) SEIKO NPC CORPORATION —2 SM9501B SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Supply voltage range Input voltage range Power dissipation Storage temperature range Symbol VDD VIN PD Tstg Condition Rating −0.3 to +7.0 −0.3 to VDD +0.3 150 Unit V V Recommended Operating Conditions VSS = 0V Parameter Supply voltage range Operating temperature range Symbol VDD Topr pre SEIKO NPC CORPORATION —3 lim ina ry −55 to +125 Condition Rating 4.5 to 5.5 −40 to +85 mW °C Unit V °C SM9501B Electrical Characteristics VDD = 4.5 to 5.5V, VSS = 0V, Ta = −40 to +85°C unless otherwise noted. Rating Parameter Supply voltage Maximum operating current consumption1 Operating current consumption1 Symbol VDD IDDM VDD = 5.0V, Ta = 25°C, no input signal, PON: VSS, OUT: OPEN Condition min 4.5 – typ 5.0 65 max 5.5 100 V µA Unit IDDT VDD = 5.0V, Ta = 25°C, 500ms pulsewidth, 0.1mVrms input (differential input), PON: VSS, OUT: OPEN ina ry – 55 – – – 0.1 – 0.5 – 1.0 – 80 35 – – 80 – 15 8 – – – – 8 1 – – – – 0.5 – 0.8VDD – – – –3.2 0.1 – – 160 200 300 650 900 9 – 10 –10 – – 100 400 700 – – – – – – 200 500 800 – f [kHz] 40 60 L1 [kH] 6.70280 5.17396 C1 [fF] 2.36228 1.36007 R1 [kΩ] 11.4492 13.4826 C0 [pF] 1.42773 1.04927 µA Standby mode current consumption Minimum input voltage range Maximum input voltage range Input frequency Analog switch resistance Startup time2 Startup time2 (PON) Gain hold time Input voltage IST VFMIN VFMAX FIN RA tON tPON tHLD VIL VIH PON: VDD or OPEN, FCN: VDD or OPEN, HLDN: VDD or OPEN µA IN1–IN2 differential input, FIN = 40kHz, 60kHz Ta = 25°C µVrms IN1–IN2 differential input, FIN = 40kHz, 60kHz IN1–IN2 differential input VIN2 = 0V, VIN3 = 50mV When supply is applied From standby mode ± 3dB change mVrms kHz Ω sec sec sec V V µA µA µA µA ms ms ms ms ms dB PON, FCN, HLDN pins PON, FCN, HLDN pins Input current LOW-level output current HIGH-level output current Fall time output propagation delay3 Rise time output propagation delay3 LOW-level output pulsewidth4 (200ms) LOW-level output pulsewidth4 (500ms) LOW-level output pulsewidth4 (800ms) Noise rejection ratio5 pre L1 C1 R1 C0 1. Measured using the standard circuit. 2. The time taken under stable wave input conditions from when power is applied or standby is released, using PON, until stable digital output occurs within ratings. 3. The time taken, with 10:1 input signal amplitude ratio and 500ms pulsewidth, from when a change in signal input occurs until the output OUT changes. Note that this characteristic is very dependent on the antenna and crystal filter characteristics. The standard crystal used here has the following equivalent circuit coefficients. 4. Values obtained when using the standard crystal employed here. Note that these values are dependent on the crystal characteristics, and should be considered as reference values. 5. Time averaged rms values, where the noise is white noise and the measurement bandwidth is determined by the crystal filter equivalent used in the standard circuit. lim IIH IOL VDD = 4.5V, OUT = 0.5V IOH tDN tUP VDD = 4.5V, OUT = 4.0V T200 T500 T800 S/N IIL VIL = 0V, PON, FCN, HLDN pins VIH = VDD, PON, FCN, HLDN pins FIN = 40/60kHz, standard crystal, NPC standard jig VIN = 1µVrms to 80mVrms SEIKO NPC CORPORATION —4 SM9501B STANDARD CIRCUIT VDD 0.1µF VDDA IN1 IN3 IN2 VDD PON OUT + − 50Ω *1 100kΩ 12pF 40kHz 5.1kΩ 12pF 60kHz *1. These values are obtained when using NPC's standard crystal and should be considered as reference values. In case of using differnt crystal, the values are different. APPLICATION CIRCUIT lim ANT. VDD 0.1µF *1 pre 100kΩ 5.1kΩ 12pF 12pF 40kHz 60kHz *1. These values are obtained when using NPC's standard crystal and should be considered as reference values. In case of using differnt crystal, the values are different. ina ry VSS FCN XO HLDN CP CB LF VSSA XI 0.22µF 1µF 1µF VDDA IN1 IN3 IN2 VDD PON CONTROLLER OUT VSS HLDN CP CB LF 0.22µF 1µF 1µF FCN XO VSSA XI SEIKO NPC CORPORATION —5 SM9501B FUNCTIONAL DESCRIPTION Antenna Input and Tuning Capacitor Switching Function L1 There are three antenna inputs: IN1, IN2, and IN3. When FCN is open (or HIGH), the internal analog switch is OFF and IN1–IN2 are the antenna inputs (60kHz mode). When FCN is LOW, the analog switch is ON, connecting IN3 and IN2. C2 is then connected in parallel to C1 in the tuning circuit, reducing the resonant frequency (40kHz mode). FCN Open or HIGH LOW Analog switch OFF ON Antenna input Tuning capacitor C1 Receiver frequency 60kHz AGC Amplifier and Gain Hold Function The input voltage from the antenna is amplified by the AGC amplifier. The gain can be monitored by the voltage on pin CP, and can be changed by varying the CP voltage. An external capacitor Cp can be connected to CP to stabilize the voltage, but the gain tracking time is dependent on the capacitance. When HLDN is open (or HIGH), the gain automatically adjusts to follow the post-amplifier detector signal. When HLDN is LOW, the immediately preceding gain is held for an interval determined by the Cp capacitance. HLDN Open or HIGH LOW lim Gain tracking Auto tracking Gain held fixed FCN should be left open if not using the tuning capacitor switching function, and IN2 should be connected to IN3 externally. pre ina ry FCN C1 C2 IN1 IN3 AGC IN2 Between IN1 and IN2 Between IN1 and IN2, IN3 C1 + C2 parallel 40kHz HLDN CP Peak Hold Detector AGC Amp Bottom Hold Detector Cb Cp CB SEIKO NPC CORPORATION —6 SM9501B Crystal Filter Circuit XO Rx40 Cx40 Rx60 Cx60 XI 40kHz 60kHz External crystals are used as filters. Multiple frequencies (40kHz and 60kHz) are supported by connecting crystals in parallel. The center frequency and bandwidth of the filters is determined by the crystal characteristics. If the center frequency is lower than the target frequency, C×40 and C×60 can be added to change the resonant frequency. And R×40 and R×60 can be added to adjust the filter Q factor. Internally, pin XO is linked to pin XI by a phase-inverted signal passed through a capacitor, which cancels the high-frequency components that pass through the crystal parallel capacitances. Detector Circuit The amplified signal is full-wave rectified and passed through a lowpass filter detector. The detector output is input to peak hold (pin CP) and bottom hold (pin CB) circuits to form the decoder reference potentials and peak hold potential for AGC control. Amplifier Rectifier LPF lim VSS potential VSS potential Decoder Circuit The detector output and peak/bottom hold mid-level potential reference are used to decode the time code signal, which is output on pin OUT. The output is active-LOW, so that the output is LOW when the input amplitude is HIGH. Rectifier LPF LPF waveform pre VSS potential Peak hold Peak/ Bottom Hold Mid-level potential Bottom hold VSS potential Standby Function When PON is open (or HIGH), the device is in standby mode and the current consumption is reduced. Receiver operation starts when PON goes LOW. PON Open (or HIGH) LOW Mode Standby Operating OUT HIGH Time code ina ry Peak/ Bottom Hold Peak hold Bottom hold VSS potential VDD potential Decoder OUT output VSS potential SEIKO NPC CORPORATION —7 SM9501B Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. pre S EIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp NP0706AE 2007.07 SEIKO NPC CORPORATION —8 lim ina ry