100336

100336 Low Power 4-Stage Counter/Shift Register August 1998 100336 Low Power 4-Stage Counter/Shift Register General Description The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (Sn) inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable (CEP, CET) inputs are provided for ease of cascading in multistage counters. One Count Enable (CET) input also doubles as a Serial Data (D0) input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In counting operations the Terminal Count (TC) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3 output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The individual Preset (Pn) inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flip-flops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 kΩ pull-down resistors. Features n n n n n 40% power reduction of the 100136 2000V ESD protection Pin/function compatible with 100136 Voltage compensated operating range = −4.2V to −5.7V Standard Microcircuit Drawing (SMD) 5962-9230601 Logic Symbol Pin Names CP CEP D0/CET S0–S2 MR DS100307-1 Description Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs P0–P3 D3 TC Q0–Q3 Q0–Q3 © 1998 National Semiconductor Corporation DS100307 www.national.com Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak DS100307-3 DS100307-2 www.national.com 2 Logic Diagram DS100307-5 3 www.national.com Function Select Table S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H Function Parallel Load Complement Shift Left Shift Right Count Down Clear Count Up Hold Truth Table Q0 = LSB Inputs MR L L L L L L L L L L L L H H H H H H H H H S2 L L L L H H H H H H H H L L L L H H H H H S1 L L H H L L L L H H H H L L H H L L L H H S0 L H L H L L L H L L L H L H L H L L H L H CEP X X X X L H X X L H X X X X X X X X X X X D0/CET X X X X L L H X L L H X X X X X L H X X X D3 X X X X X X X X X X X X X X X X X X X X X CP N N N N N Outputs Q3 P3 Q3 D3 Q2 Q3 Q3 L Q3 Q3 Q3 L L L L L L L L L Q2 P2 Q2 Q3 Q1 Q2 Q2 L Q2 Q2 Q2 L L L L L L L L L Q1 P1 Q1 Q2 Q0 Q1 Q1 L Q1 Q1 Q1 L L L L L L L L L Q0 P0 Q0 Q1 D0 Q0 Q0 L Q0 Q0 Q0 L L L L L L L L L TC L L D3 Q3(Note 1) 1 1 H H 2 2 H H L L L L L H H H H Asynchronous Master Reset Invert Shift to LSB Shift to MSB Count Down Count Down with CEP not active Count Down with CET not active Clear Count Up Count Up with CEP not active Count Up with CET not active Hold Mode Preset (Parallel Load) (Q0–3) minus 1 X X N N (Q0–3) plus 1 X X X X X X X X X X X X 1 = L if Q0–Q3 = LLLL H if Q0–Q3 ≠ LLLL 2 = L if Q0–Q3 = HHHH H if Q0–Q3 ≠ HHHH H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care N = LOW-to-HIGH Transition Note 1: Before the clock, TC is Q3 After the clock, TC is Q2 www.national.com 4 Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3) −65˚C to +150˚C +175˚C −7.0V to +0.5V VEE to +0.5V −50 mA ≥2000V Recommended Operating Conditions Case Temperature (TC) Military Supply Voltage (VEE) −55˚C to +125˚C −5.7V to −4.2V Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Military Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, T Symbol VOH Parameter Output HIGH Voltage Min −1025 −1085 VOL Output LOW Voltage C = −55˚C to +125˚C Units mV mV mV mV mV mV TC 0˚C to +125˚C VIN = VIH (Max) Max −870 −870 Conditions Loading with 50Ω to −2.0V Notes −55˚C 0˚C to +125˚C −55˚C 0˚C to +125˚C or VIL (Min) (Notes 4, 5, 6) −1830 −1620 −1830 −1555 VOHC Output HIGH Voltage −1035 −1085 VIN = VIH (Min) Loading with 50Ω to −2.0V (Notes 4, 5, 6) −55˚C 0˚C to +125˚C −55˚C −55˚C to +125˚C −55˚C to +125˚C −55˚C to +125˚C 0˚C to +125˚C −55˚C −55˚C to +125˚C or VIL (Max) VOLC Output LOW Voltage −1610 −1555 mV mV mV mV µA VIH VIL IIL IIH Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current −1165 −870 Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VEE = −4.2V VIN = VIL (Min) VEE = −5.7V VIN = VIH(Max) Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V (Notes 4, 5, 6, 7) (Notes 4, 5, 6, 7) (Notes 4, 5, 6) −1830 −1475 0.50 240 340 µA µA mA (Notes 4, 5, 6) IEE Power Supply Current −185 −195 −70 −70 (Notes 4, 5, 6) Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 5: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 7: Guaranteed by applying specified input conditon and testing VOH/VOL. 5 www.national.com Military Version AC Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fshift tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL ts Parameter Shift Frequency Propagation Delay CP to Qn, Q n TC = −55˚C Min 325 0.40 1.30 1.20 0.60 2.30 2.10 0.70 1.30 0.20 2.30 3.90 4.60 2.90 5.20 4.30 3.20 4.10 1.90 Max TC = +25˚C Min 325 0.50 1.70 1.50 0.80 2.70 2.20 1.00 1.50 0.20 2.20 3.80 4.60 2.80 5.20 4.10 3.20 4.20 1.80 Max TC = +125˚ Min 325 0.40 1.70 1.60 0.90 2.90 2.40 1.30 1.70 0.20 2.50 4.20 5.20 3.20 5.90 4.70 4.10 4.90 2.00 Max Units MHz ns ns ns ns ns ns ns Conditions Notes (Note 11) (Notes 8, 9, 10, 12) Figures 2, 3 Figures 1, 3 Figures 1, 7, 8 Figures 1, 9 Figures 1, 4 Propagation Delay CP to TC (Shift) Propagation Delay CP to TC (Count) Propagation Delay MR to Qn, Q n (Notes 8, 9, 10, 12) (Notes 8, 9, 10, 12) Propagation Delay MR to TC (Count) Propagation Delay MR to TC (Shift) Propagation Delay D0/CET to TC Propagation Delay Sn to TC Transition Time 20% to 80%, 80% to 20% Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) Figures 1, 12 Figures 1, 10, 11 (Notes 8, 9, 10, 12) Figures 1, 5 ns ns (Notes 8, 9, 10, 12) Figures 1, 3 (Note 11) 1.40 1.70 1.80 1.80 3.30 2.60 0.90 1.00 0.70 0.60 0.00 1.60 2.00 1.40 1.70 1.80 1.80 3.30 2.60 0.90 1.00 0.70 0.60 0.00 1.60 2.00 1.40 1.70 1.80 1.80 3.30 2.60 0.90 1.00 0.70 0.60 0.00 1.60 2.00 ns ns ns Figure 6 (Note 11) th Hold Time D3 Pn D0/CET CEP Sn Pulse Width HIGH: CP MR Figure 6 (Note 11) tpw(H) Figures 3, 4 (Note 11) Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold tempertures. Note 9: Screen tested 100% on each device at +25˚C temperature only, Subgroups A9. Note 10: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroups A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 11: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data). Note 12: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. www.national.com 6 Test Circuitry DS100307-6 Notes: VCC, VCCA = +2V, VEE = −2.5V L1, L2 and L3 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and V EE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF Pin numbers shown are for flatpak; for DIP see logic symbol FIGURE 1. AC Test Circuit 7 www.national.com Test Circuitry (Continued) DS100307-7 Notes: For shift right mode, +1.05V is applied at S0. The feedback path from output to input should be as short as possible. FIGURE 2. Shift Frequency Test Circuit (Shift Left) Switching Waveforms DS100307-8 FIGURE 3. Propagation Delay (Clock) and Transition Times www.national.com 8 Switching Waveforms (Continued) DS100307-9 FIGURE 4. Propagation Delay (Reset) DS100307-10 FIGURE 5. Propagation Delay (Serial Data, Selects) 9 www.national.com Switching Waveforms (Continued) DS100307-11 Notes: ts is the minimum time before the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 6. Setup and Hold Time DS100307-15 Note: Shift Right Mode; S0 = H, S1 = H, S2 = L. FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode) DS100307-16 Note: Shift Left Mode; S0 = L, S1 = H, S2 = L. FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode) www.national.com 10 Switching Waveforms (Continued) DS100307-17 Note: *Decimal representation of binary outputs. Count Up: S0 = L, S1 = H, S2 = H; Count Down: S0 = L, S 1 = L, S2 = H. Measurement taken at 50% point of waveform. FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes) DS100307-18 Note: Shift Right Mode; S0 = H, S1 = H, S2 = L. FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode) DS100307-19 Note: Shift Left Mode; S0 = L, S1 = H, S2 = L. FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode) 11 www.national.com Switching Waveforms (Continued) DS100307-20 Note: *Decimal representation of binary outputs. Count Up Mode: S0 = L, S1 = H, S2 = H. DS100307-21 Note: *Decimal representation of binary outputs. Count Down Mode: S0 = L, S1 = L, S2 = H. FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes) Applications 3-Stage Divider, Preset Count Down Mode DS100307-12 Note: If S0 = S1 = S2 = LOW, then TC = LOW www.national.com 12 Applications (Continued) Slow Expansion Scheme DS100307-13 Fast Expansion Scheme DS100307-14 13 www.national.com 14 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E 24-Lead Quad Cerpak (F) NS Package Number W24B 15 www.national.com 100336 Low Power 4-Stage Counter/Shift Register LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.