11C06DCQR

11C06 750 MHz D-Type Flip-Flop Not Intended For New Designs August 1992 11C06 750 MHz D-Type Flip-Flop General Description The 11C06 is a high-speed ECL D-Type Master-Slave FlipFlop capable of toggle rates over 750 MHz Designed primarily for high-speed prescaling it can also be used in any application which does not require preset inputs The circuit is voltage-compensated which makes input thresholds and output levels insensitive to VEE variations Complementary Q and Q outputs are provided as are two Data inputs Clock and Clock Enable inputs The 11C06 is pin-compatible with the Motorola MC1690L but is a higher-frequency replacement Logic Symbol Connection Diagrams 16-Pin DIP 16-Pin Flatpak TL F 9890–3 TL F 9890 – 2 TL F 9890 – 1 Truth Table Pin Names Dn CP CE QQ Description Data Input Clock Input Clock Enable (Active LOW) Outputs CE L L L L H CP L H L L X D X X L H X Qn Qnb1 Qnb1 L H Qnb1 H e HIGH Voltage Level L e LOW Voltage Level X e Don’t Care L e LOW to HIGH Transition Qnb1 e Previous State C1995 National Semiconductor Corporation TL F 9890 RRD-B30M115 Printed in U S A Absolute Maximum Ratings Above which the useful life may be impaired If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 65 C to a 150 C Storage Temperature Maximum Junction Temperature (TJ) Supply Voltage Range Input Voltage (DC) Output Current (DC Output HIGH) a 150 C b 7 0V to GND Operating Range Lead Temperature (Soldering 10 sec ) b 5 7V to b 4 7V 300 C Recommended Operating Conditions Min Supply Voltage (VEE) Ambient Temperature (TA) b 5 7V Typ b 5 2V Max b 4 7V a 75 C VEE to GND b 50 mA 0C DC Electrical Characteristics VEE e b5 2V VCC e GND Symbol VOH Parameter Output Voltage HIGH Min b 1000 b 960 b 900 b 1870 b 1850 b 1830 b 1020 b 980 b 920 b 1615 b 1600 b 1575 b 1135 b 1095 b 1035 b 1870 b 1850 b 1830 b 840 b 810 b 720 b 1500 b 1485 b 1460 Typ Max b 840 b 810 b 720 b 1635 b 1620 b 1595 Units mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mA mA mA TA 0C a 25 C a 75 C 0C a 25 C a 75 C Conditions VIN e VIH (Max) or VIL (Min) per Truth Table Loading 50X to b2V VOL Output Voltage LOW VOHC Output Voltage HIGH 0C a 25 C a 75 C VIN e VIH (Min) or VIL (Max) for Dn Inputs Loading 50X to b2V VOLC Output Voltage LOW 0C a 25 C a 75 C VIH Input Voltage HIGH 0C a 25 C a 75 C Guaranteed Input Voltage HIGH for All Inputs Guaranteed Input Voltage LOW for All Inputs VIN e VIH (Max) VIL Input Voltage LOW 0C a 25 C a 75 C a 25 C a 25 C a 25 C a 25 C IIH Input Current HIGH Clock Input Data Input Input Current LOW Power Supply Current 05 b 59 b 40 250 270 IIL IEE VIN e VIH (Min) All Inputs Open mA AC Electrical Characteristics VEE e b5 2V VCC e GND TA e a 25 C Symbol tPHL tPLH tTLH tTHL tS tH fTOG (MAX) Parameter Propagation Delay (CP-Q) Propagation Delay (CP-Q) Transition Time 20% to 80% Transition Time 80% to 20% Set-up Time Hold Time Toggle Frequency (CP) 650 Min 07 07 05 05 Typ 10 10 08 08 02 02 750 Max 12 12 10 10 Units ns ns ns ns ns ns MHz See Figure 2 Note See Figure 1 Conditions Note The device is guaranteed for fTOG (CP) t 600 MHz fTOG(CE) t 550 MHz over the 0 C to a 75 C temperature range 2 Functional Description While the clock is LOW the slave is held steady and the information on the D input is permitted to enter the master The next transition from LOW to HIGH locks the master in its present state making it insensitive to the D input This transition simultaneously connects the slave to the master causing the new information to appear on the outputs Master and slave clock thresholds are internally offset in opposite directions to avoid race conditions or simultaneous master-slave changes when the clock has slow rise or fall times The CP and CE inputs are logically identical but physical constraints associated with the Dual-In-Line package make the CE input slower at the upper end of the toggle range To prevent new data from entering the master on the next CP LOW cycle CE should go HIGH while CP is still HIGH TL F 9890 – 4 RT e 50X termination of scope L1 e 50X impedance lines All input transition times are 2 0 ns g 0 2 ns FIGURE 1 Propagation Delay (CP to Q) RT e 50X termination of scope L1 e 50X impedance lines Adjust VBIAS for a 0 7V baseline of 800 mV peak-to-peak sinewave input All input transition times are 2 0 ns g 0 2 ns TL F 9890 – 5 FIGURE 2 Toggle Frequency Test Circuit 3 Typical Waveforms TL F 9890 – 6 Horizontal Scale e 1 0 ns div Vertical Scale e 200 mV div Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 11C06 Device Number (basic) Package Code D e Ceramic Dual-In-Line F e Flatpak D C QR Special Variations QR e Commercial grade device with burn-in Temperature Range C e Commercial (0 C to a 85 C) 4 Physical Dimensions inches (millimeters) 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 5 11C06 750 MHz D-Type Flip-Flop Physical Dimensions inches (millimeters) (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications