54ABT16374W-QML

54ABT16374 16-Bit D Flip-Flop with TRI-STATE Outputs July 1998 54ABT16374 16-Bit D Flip-Flop with TRI-STATE ® Outputs General Description The ABT16374 contains sixteen non-inverting D flip-flops with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. Features Separate control logic for each byte 16-bit version of the ABT374 Edge-triggered D-type inputs Buffered Positive edge-triggered clock High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Guaranteed latch-up protection n Standard Microcircuit Drawing (SMD) 5962-9320101 n n n n n Ordering Code: Commercial 54ABT16374W-QML Package Number WA48A 48-Lead Cerpack Package Description Connection Diagram Pin Assignment for Cerpack Logic Symbol DS100224-1 Pin Description Pin Names OEn CPn D0–D15 O0–O15 TRI-STATE Output Enable Input (Active Low) Clock Pulse Input (Active Rising Edge) Data Inputs TRI-STATE Outputs Description DS100224-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS100224 www.national.com 54ABT16374 Functional Description The ABT16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Truth Tables Inputs CP1 N N L X OE1 L L L H Inputs CP2 N N L X OE2 L L L H D8–D15 H L X X D0–D7 H L X X Outputs O0–O7 H L (Previous) Z Outputs O8–O15 H L (Previous) Z H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance Logic Diagrams Byte 1 (0:7) DS100224-3 Byte 2 (8:15) DS100224-4 www.national.com 2 54ABT16374 Absolute Maximum Ratings (Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) −350 mA −500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100mV/ns −0.5V to 5.5V −0.5V to VCC twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE ICCD Dynamic ICC (Note 4) Note 3: For 8-bit toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. ABT16374 Min Typ Max 2.0 0.8 −1.2 54ABT 54ABT 54ABT 2.5 2.0 0.55 5 5 7 −5 −5 4.75 50 −50 −100 −275 50 100 2.0 62 2.0 2.5 2.5 2.5 Units V V V V V V µA µA µA V µA µA mA µA µA mA mA mA mA mA mA mA/ VCC Conditions Recognized HIGH Signal Recognized LOW Signal Min Min Min Min Max Max Max 0.0 0−5.5V 0−5.5V Max Max 0.0 Max Max Max Max IIN = −18 mA IOH = −3 mA IOH = −24 mA IOL = 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded VOUT = 2.7V; OE = 2.0V VOUT = 0.5V; OE = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others VCC or GND All Outputs HIGH All Outputs LOW OE = VCC; All Others at VCC or GND VI = VCC − 2.1V Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND No Load 0.30 Max Outputs Open OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle MHz 3 www.national.com 54ABT16374 DC Electrical Characteristics Conditions Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Min Max 1.1 -0.45 Units V V VCC 5.0 5.0 CL = 50 pF, RL = 500Ω TA = 25˚C (Note 5) TA = 25˚C(Note 5) Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. AC Electrical Characteristics 54ABT TA = −55˚C to +125˚C Symbol Parameter Min fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Max Clock Frequency Propagation Delay CP to On Output Enable Time 1.5 1.5 0.8 1.2 1.5 1.5 6.9 6.9 6.5 6.5 9.6 7.2 ns ns ns 150 VCC = 4.5V to 5.5V CL = 50 pF Max MHz Units AC Operating Requirements 54ABT TA = −55˚C to +125˚C Symbol Parameter Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Pulse Width, CP HIGH or LOW 1.3 1.3 1.5 1.5 3.3 3.3 ns ns VCC = 4.5V to 5.5V CL = 50 pF Max ns Units Capacitance Symbol CIN COUT (Note 6) Parameter Input Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF Conditions (TA = 25˚C) VCC = 0V VCC = 5.0V Note 6: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 4 54ABT16374 AC Loading DS100224-6 *Includes jig and probe capacitance DS100224-10 FIGURE 1. Standard AC Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100224-7 FIGURE 2. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100224-11 FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms DS100224-8 FIGURE 3. Test Input Pulse Requirements FIGURE 7. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100224-12 Amplitude 3.0V Rep Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 4. Test Input Signal Requirements 5 www.national.com 54ABT16374 16-Bit D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Cerpack NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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