54ABT16646W-QML

54ABT16646 16-Bit Transceivers and Registers with TRI-STATE Outputs July 1998 54ABT16646 16-Bit Transceivers and Registers with TRI-STATE ® Outputs General Description The ’ABT16646 consists of bus transceiver circuits with TRI-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. Features n Independent registers for A and B buses n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9450202 Ordering Code Military 54ABT16646W-QML Package Number WA56A 56-Lead Cerpack Pin Names A0–A15 B0–B15 CPABn, CPBAn SABn, SBAn OEn DIR DS100226-1 Package Description Logic Symbol Description Data Register A Inputs/ TRI-STATE Outputs Data Register B Inputs/ TRI-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS100226 www.national.com 54ABT16646 Connection Diagram Pin Assignment for Cerpack DS100226-2 Real Time Transfer A-Bus to B-Bus Storage from Bus to Register DS100226-3 DS100226-5 FIGURE 1. Real Time Transfer B-Bus to A-Bus FIGURE 3. Transfer from Register to Bus DS100226-4 FIGURE 2. DS100226-6 FIGURE 4. www.national.com 2 54ABT16646 Function Table Inputs OE1 H H H L L L L L L L L DIR1 X X X H H H H L L L L CPAB1 H or L N X X N H or L N X X X X CPBA1 H or L X N X X X X X N H or L N X = Immaterial N = LOW-to-HIGH Transition. Data I/O (Note 1) SAB1 X X X L L H H X X X X SBA1 X X X X X X X L L H H Output Input Input Output Input Input A0–7 B0–7 Isolation Output Operation Mode Clock An Data into A Register Clock Bn Data Into B Register An to Bn — Real Time (Transparent Mode) Clock An Data to A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An — Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins. 3 www.national.com 54ABT16646 Logic Diagram DS100226-7 www.national.com 4 54ABT16646 Absolute Maximum Ratings (Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns −0.5V to +5.5V −0.5V to VCC twice the rated IOL (mA) −500 mA Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 5) No Load 0.23 mA/MHz Max −100 −5 50 −50 −275 50 100 2.0 60 2.0 2.5 µA µA µA mA µA µA mA mA mA mA Max 0V–5.5V 0V–5.5V Max Max 0.0V Max Max Max Max VIN = 0.5V (Non-I/O Pins) (Note 5) VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); OE = 2.0V VOUT = 0.5V (An, Bn); OE = 2.0V VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs TRI-STATE; All Others GND VI = VCC − 2.1V All Other Outputs at VCC or GND Outputs Open OE, DIR, and SEL = GND, Non-I/O = GND or VCC (Note 4) One Bit toggling, 50% duty cycle 100 µA Max VIN = 5.5V (An, Bn) 54ABT 54ABT 54ABT 4.75 5 7 2.5 2.0 0.55 V V µA µA Min 0.0 Max Max 2.0 0.8 −1.2 ABT16646 Typ Max V V V Min Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −24 mA, (An, Bn) IOL = 48 mA, (An, Bn) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 5) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) Units VCC Conditions 5 www.national.com 54ABT16646 DC Electrical Characteristics Note 4: For 8-bit toggling, ICCD < 1.4 mA/MHz. Note 5: Guaranteed but not tested. (Continued) Symbol VOLP VOLV Parameter Min Max Units VCC Conditions CL = 50 pF, RL = 500Ω Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL 1.0 −1.5 V V 5.0 5.0 TA = 25˚C (Note 6) TA = 25˚C (Note 6) Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics 54ABT TA = −55˚C to +125˚C Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Max Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBAn or SABn to An to Bn Enable Time OEn to An or Bn Disable Time OEn to An or Bn Enable Time DIRn to An or Bn Disable Time DIRn to An or Bn 125 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 6.9 7.7 5.8 7.0 7.1 7.2 6.4 6.5 7.6 6.5 6.4 6.7 8.1 7.1 ns ns ns ns ns ns VCC = 4.5V–5.5V CL = 50 pF Max MHz ns Units AC Operating Requirements 54ABT TA = −55˚C to +125˚C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Pulse Width, HIGH or LOW 4.3 ns 0.5 ns 4.0 VCC = 4.5V–5.5V CL = 50 pF Max ns Units Capacitance Symbol CIN CI/O (Note 7) Parameter Input Capacitance Output Capacitance Typ 5 11 Units pF pF Conditions TA = 25˚C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) www.national.com 6 54ABT16646 Capacitance AC Loading (Continued) Note 7: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012. DS100226-9 *Includes jig and probe capacitance FIGURE 5. Standard AC Test Load DS100226-12 FIGURE 9. Propagation Delay, Pulse Width Waveforms DS100226-10 FIGURE 6. VM = 1.5V Input Pulse Requirements FIGURE 10. TRI-STATE Output HIGH and LOW Enable and Disable Times Amplitude 3V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns tf 2.5 ns DS100226-13 FIGURE 7. Test Input Signal Requirements DS100226-14 FIGURE 11. Setup Time, Hold Time and Recovery Time Waveforms DS100226-11 FIGURE 8. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 7 www.national.com 54ABT16646 16-Bit Transceivers and Registers with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Cerpack NS Package Number WA56A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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