54ABT373W-QML

54ABT373 Octal Transparent Latch with TRI-STATE Outputs July 1998 54ABT373 Octal Transparent Latch with TRI-STATE ® Outputs General Description The ’ABT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching, noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9321801 Features n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability of 24 mA Ordering Code Military 54ABT373J-QML 54ABT373W-QML 54ABT373E-QML Package Number J20A W20A E20A 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description 20-Lead Ceramic Dual-In-Line Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100206-2 DS100206-1 Pin Names D0–D7 LE OE O0–O7 Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) TRI-STATE Latch Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100206 www.national.com Functional Description The ’ABT373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs LE H H L X OE L L L H Dn H L X X Output On H L On (no change) Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance State Logic Diagram DS100206-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. −0.5V to +5.5V −0.5V to VCC twice the rated IOL (mA) DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE ICCD Dynamic ICC (Note 4) No Load 0.12 −100 4.75 50 −50 −275 50 100 50 30 50 2.5 2.5 2.5 54ABT 54ABT 54ABT 2.5 2.0 0.55 5 5 7 −5 −5 V µA µA mA µA µA µA mA µA mA mA mA mA/ MHz Max Max 0.0 0 − 5.5V 0 − 5.5V Max Max 0.0 Max Max Max µA µA Max Max V V µA Min Min Max Parameter Min 2.0 0.8 −1.2 ABT373 Typ Max V V V Min Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA IOH = −3 mA IOH = −24 mA IOL = 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded VOUT = 2.7V; OE = 2.0V VOUT = 0.5V; OE = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH All Outputs LOW OE = VCC All Others at VCC or GND VI = VCC − 2.1V Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND Outputs Open, LE = VCC OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. Units VCC Conditions 3 www.national.com AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V CL = 50 pF Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.0 1.0 1.0 1.5 1.0 1.5 1.7 1.0 Max 6.8 7.0 7.7 7.7 6.7 7.2 8.0 7.0 ns ns ns ns Units AC Operating Requirements Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V CL = 50 pF Min ts(H) ts(L) th(H) th(L) tw(H) Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE Pulse Width, LE HIGH 2.5 2.5 2.5 2.5 3.3 ns ns Max ns Units Capacitance Symbol CIN COUT (Note 5) Parameter Input Capacitance Output Capacitance Typ 5 9 Units pF pF Conditions (TA = 25˚C) VCC = 0V VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Output tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Output DS100206-11 DS100206-12 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 4 Capacitance (Continued) tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100206-13 DS100206-14 tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100206-15 DS100206-16 tSET LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE tSET HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE DS100206-17 DS100206-18 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 5 www.national.com Capacitance (Continued) tHOLD HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE tHOLD LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to LE DS100206-19 DS100206-20 tPLH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching Data to Output tPHL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching Data to Output DS100206-21 DS100206-22 tPZH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output tPZL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output DS100206-23 DS100206-24 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 6 Capacitance (Continued) tPHZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output tPLZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output DS100206-25 DS100206-26 tPLH vs Load Capacitance TA = 25˚C, 1 Output Switching Data to Output tPHL vs Load Capacitance TA = 25˚C, 1 Output Switching Data to Output DS100206-27 DS100206-28 tPLH vs Load Capacitance TA = 25˚C, 8 Outputs Switching Data to Output tPHL vs Load Capacitance TA = 25˚C, 8 Outputs Switching Data to Output DS100206-29 DS100206-30 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 www.national.com Capacitance (Continued) tPZH vs Load Capacitance TA = 25˚C, 8 Outputs Switching OE to Output tPZL vs Load Capacitance TA = 25˚C, 8 Outputs Switching OE to Output DS100206-31 DS100206-32 tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching LE to Output tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching LE to Output DS100206-35 DS100206-36 tPLH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching LE to Output tPHL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching LE to Output DS100206-37 DS100206-38 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 8 Capacitance (Continued) tPLH and tPHL vs Number Outputs Switching CL = 50 pF, TA = 25˚C, VCC = 5.0V, Outputs In Phase Data to Output Typical ICC vs Output Switching Frequency CL = 0 pF, VCC = VIH = 5.5V, LE = GND, 1 Output Switching at 50% Duty Cycle Data to Output, Transparent Mode with Unused Data Inputs = VIH DS100206-33 DS100206-34 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 9 www.national.com AC Loading DS100206-5 DS100206-4 *Includes jig and probe capacitance FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 1. Standard AC Test Load DS100206-7 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100206-6 FIGURE 2. Test Input Signal Levels Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements DS100206-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100206-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions www.national.com 10 11 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 20-Lead Ceramic Flatpak (F) NS Package Number W20A 13 www.national.com 54ABT373 Octal Transparent Latch with TRI-STATE Outputs LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. 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