54ABT543E-QML

54ABT543 Octal Registered Transceiver with TRI-STATE Outputs November 2002 54ABT543 Octal Registered Transceiver with TRI-STATE ® Outputs General Description The ’ABT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. n A and B outputs have current sourcing capability of 24 mA and current sinking capability of 48 mA n Separate controls for data flow in each direction n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Military Drawing (SMD) 5962-9231401 Features n Back-to-back registers for storage n Bidirectional data path Ordering Code: Military 54ABT543J-QML 54ABT543W-QML 54ABT543E-QML Package Number J24F W24C E28A 24-Lead Ceramic Dual-In-Line 24-Lead Cerpack 28-Lead Ceramic Leadless Chip Carrier, Type C Package Description Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC 10021802 10021801 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2002 National Semiconductor Corporation DS100218 www.national.com 54ABT543 Pin Descriptions Pin Names OEAB , OEBA LEAB , LEBA CEAB , CEBA A0–A7 B0–B7 Description Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or TRI-STATE Outputs Side B Inputs or TRI-STATE Outputs Functional Description The ’ABT543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB ) input must be low in order to enter data from the A port or take data from the B port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB ) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA , LEBA and OEBA . CEAB H X L X L LEAB X H L X X Data I/O Control Table Inputs OEAB X X X H L Latched Latched Transparent — — Latch Status Output Buffers High Z — — High Z Driving H = High Voltage Level L = Low Voltage Level X = Immaterial Logic Diagram 10021803 www.national.com 2 54ABT543 Absolute Maximum Ratings (Note 1) in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) −500 mA 10V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output −0.5V to +5.5V −0.5V to VCC −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +175˚C −65˚C to +150˚C −55˚C to +125˚C Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns −55˚C to +125˚C DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current 54ABT 54ABT 54ABT 4.75 2.5 2.0 0.55 V V V Min Min 0.0 2.0 0.8 −1.2 ABT543 Typ Max V V V Min Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −24 mA, (An, Bn) IOL = 48 mA, (An, Bn) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded 5 µA Max VIN = 2.7V (Non-I/O Pins) (Note 3) VIN = VCC (Non-I/O Pins) IBVI IBVIT IIL Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current −5 µA Max VIN = 0.5V (Non-I/O Pins)(Note 3) VIN = 0.0V (Non-I/O Pins) IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCLH ICCL ICCZ Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current −100 50 −50 −275 50 100 50 30 50 µA µA mA µA µA µA mA µA 0V–5.5V VOUT = 2.7V (An, Bn); OEAB or CEAB = 2V 0V–5.5V VOUT = 0.5V (An, Bn); OEAB or CEAB = 2V Max Max 0.0V Max Max Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs TRI-STATE All Others at VCC or GND 7 100 µA µA Max Max VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) Units VCC Conditions 3 www.national.com 54ABT543 DC Electrical Characteristics Symbol ICCT ICCD Parameter (Continued) ABT543 Min Typ Max 2.5 mA Max VI = VCC − 2.1V All Others at VCC or GND Outputs Open, CEAB 0.18 mA/MHz Max and OEAB = GND,CEBA = VCC, One Bit Toggling, 50% Duty Cycle, (Note 4) Units VCC Conditions Additional ICC/Input Dynamic ICC (Note 3) No Load Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Note 3: Guaranteed but not tested. Note 4: For 8-bit toggling. ICCD < 1.4 mA/MHz. DC Electrical Characteristics Conditions Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Min Max 1.1 -0.45 Units V V VCC 5.0 5.0 CL = 50 pF, RL = 500Ω TA = 25˚C (Note 5) TA = 25˚C(Note 5) Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. AC Electrical Characteristics 54ABT TA = −55˚C to +125˚C Symbol Parameter Min tPLH tPHL tPLH tPHL Propagation Delay An to Bn or Bn to An Propagation Delay LEAB to Bn, LEBA to An OEBA or OEAB to An or Bn tPZH tPZL Enable Time LEAB to Bn, LEBA to An OEBA or OEAB to An or Bn tPHZ tPLZ Disable Time CEBA or CEAB to An or Bn 1.3 1.8 2.0 1.5 6.4 7.4 7.2 7.0 Figure 6 ns Figure 6 1.6 1.6 6.6 6.4 ns Figure 4 1.6 1.6 VCC = 4.5V–5.5V CL = 50 pF Max 6.4 6.2 ns Figure 4 Units Fig. No. ns www.national.com 4 54ABT543 AC Operating Requirements 54ABT TA = −55˚C to +125˚C Symbol Parameter VCC = 4.5V–5.5V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(L) Setup Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An or Bn to LEBA or LEAB Setup Time, HIGH or LOW An or Bn to CEAB or CEBA Hold Time, HIGH or LOW An or Bn to CEAB or CEBA Pulse Width, LOW 3.5 3.0 2.0 2.0 3.3 2.5 2.0 2.0 3.5 ns Figure 5 ns Figure 7 ns Figure 7 ns Figure 7 Max ns Figure 7 Units Fig. No. Capacitance Symbol CIN CI/O(Note 6) Parameter Input Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF Conditions: TA = 25˚C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) Note 6: CI/O is measured at frequency, f = 1 MHz, PER MIL-STD-883, METHOD 3012. AC Loading 10021804 10021806 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. VM = 1.5V Input Pulse Requirements Amplitude Rep. Rate 3V 1 MHz tw 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements 5 www.national.com 54ABT543 AC Loading (Continued) 10021808 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms 10021805 10021807 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 10021809 www.national.com 6 54ABT543 Physical Dimensions unless otherwise noted inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) Order Number 54ABT543E-QML NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package Order Number 54ABT543J-QML NS Package Number J24F 7 www.national.com 54ABT543 Octal Registered Transceiver with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak Package (F) Order Number 54ABT543W-QML NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.