54ABT573E-QML

54ABT573 Octal D-Type Latch with TRI-STATE Outputs July 1998 54ABT573 Octal D-Type Latch with TRI-STATE ® Outputs General Description The ’ABT573 is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the ’ABT373 but has different pinouts. n Functionally identical to ’ABT373 n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability of 24 mA n Output switching specified for both 50 pF and 250 pF loads n Guaranteed latchup protection n High impedance glitch-free bus loading during entire power up and power down n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9321901 Features n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Useful as input or output port for microprocessors Ordering Code Military 54ABT573J-QML 54ABT573W-QML 54ABT573E-QML Package Number J20A W20A E20A 20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description Connection Diagram Pin Assignment for DIP and Cerpack Pin Assignment for LCC DS100219-39 DS100219-1 Pin Names D0–D7 LE OE O0–O7 Data Inputs Description Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100219 www.national.com Functional Description The ’ABT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. OE L L L H H H L X Function Table Inputs LE D H L X X Outputs O H L O0 Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle Logic Diagram DS100219-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Storage Temperature −65˚C to +150˚C Ambient Temperature under Bias −55˚C to +125˚C Junction Temperature under Bias Ceramic −55˚C to +175˚C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to +5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) Twice the rated IOL (mA) DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE ICCD Dynamic ICC (Note 4) No Load 0.12 −100 4.75 50 −50 −275 50 100 50 30 50 2.5 2.5 2.5 −5 −5 V µA µA mA µA µA µA mA µA mA mA mA mA/ MHz Max Max 0.0 0 − 5.5V 0 − 5.5V Max Max 0.0 Max Max Max µA Max VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded VOUT = 2.7V; OE = 2.0V VOUT = 0.5V; OE = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH All Outputs LOW OE = VCC All Others at VCC or GND VI = VCC − 2.1V Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND Outputs Open OE = GND, LE = VCC (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed but not tested. ABT573 Typ Max 2.0 0.8 −1.2 54ABT 54ABT 54ABT 2.5 2.0 0.55 5 5 7 Units V V V V V µA µA VCC Conditions Recognized HIGH Signal Recognized LOW Signal Min Min Min Max Max IIN = −18 mA IOH = −3 mA IOH = −24 mA IOL = 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V 3 www.national.com DC Electrical Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Min Max 0.9 -1.7 Units V V VCC 5.0 5.0 Conditions CL = 50 pF, RL = 500Ω TA = 25˚C (Note 5) TA = 25˚C (Note 5) Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V CL = 50 pF Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.0 1.5 1.0 1.5 0.8 1.5 1.5 1.0 Max 6.4 6.7 7.1 7.5 6.5 7.2 7.7 7.0 ns ns ns ns Units Fig. No. Figure 4 Figure 4 Figure 6 Figure 6 AC Operating Requirements Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V CL = 50 pF Min ts(H) ts(L) th(H) th(L) tw(H) Set Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE Pulse Width, LE HIGH 2.5 2.5 2.5 2.5 3.3 ns ns Max ns Units Fig. No. Figure 7 Figure 7 Figure 5 Capacitance Symbol CIN COUT (Note 6) Parameter Input Capacitance Output Capacitance Typ 5 9 Units pF pF Conditions (TA = 25˚C) VCC = 0V VCC = 5.0V Note 6: COUT is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012. www.national.com 4 Capacitance (Continued) TPHL vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to Output TPLH vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to Output DS100219-10 DS100219-11 TPZH vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output TPZL vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output DS100219-12 DS100219-13 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 5 www.national.com Capacitance (Continued) TPLZ vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output TPHZ vs Temperature (TA), CL = 50 pF, 1 Output Switching, OE to Output DS100219-14 DS100219-15 TSET LOW vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE TSET HIGH vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE DS100219-16 DS100219-17 THOLD HIGH vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE THOLD LOW vs Temperature (TA), CL = 50 pF, 1 Output Switching, Data to LE DS100219-18 DS100219-19 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 6 Capacitance (Continued) TPHL vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, Data to Output TPLH vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, Data to Output DS100219-20 DS100219-21 TPZH vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output TPZL vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output DS100219-22 DS100219-23 TPHZ vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output TPLZ vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, OE to Output DS100219-24 DS100219-25 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 www.national.com Capacitance (Continued) TPHL vs Load Capacitance TA = 25˚C, 1 Output Switching, Data to Output TPLH vs Load Capacitance TA = 25˚C, 1 Output Switching, Data to Output DS100219-26 DS100219-27 TPLH vs Load Capacitance TA = 25˚C, 8 Outputs Switching, Data to Output TPHL vs Load Capacitance TA = 25˚C, 8 Outputs Switching, Data to Output DS100219-28 DS100219-29 TPZH vs Load Capacitance TA = 25˚C, 8 Outputs Switching, OE to Output TPZL vs Load Capacitance TA = 25˚C, 8 Outputs Switching, OE to Output DS100219-30 DS100219-31 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 8 Capacitance (Continued) TPHL vs Temperature (TA), CL = 50 pF, 1 Output Switching, LE to Output TPLH vs Temperature (TA), CL = 50 pF, 1 Output Switching, LE to Output DS100219-34 DS100219-35 TPLH vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, LE to Output TPHL vs Temperature (TA), CL = 50 pF, 8 Outputs Switching, LE to Output DS100219-36 DS100219-37 TPLH and TPHL vs Number Outputs Switching, CL = 50 pF, TA = 25˚C, VCC = 5.0V, Outputs In Phase Data to Output Typical ICC vs Output Switching Frequency, CL = 0 pF, VCC = VIH = 5.5V, LE = GND, 1 Output Switching at 50% Duty Cycle, Data to Output, Transparent Mode with Unused Data Inputs = VIH DS100219-32 DS100219-33 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 9 www.national.com AC Loading DS100219-4 *Includes jig and probe capacitance FIGURE 1. Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100219-5 DS100219-6 DS100219-7 FIGURE 2. Test Input Signal Levels FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times tf 2.5 ns Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns FIGURE 3. Test Input Signal Requirements DS100219-9 DS100219-8 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier NS Package Number E20A 20-Lead Ceramic Dual-In-Line NS Package Number J20A 11 www.national.com 54ABT573 Octal D-Type Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpack NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. 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