54ABT646F

54ABT646 Octal Transceivers and Registers with TRI-STATE Outputs July 1998 54ABT646 Octal Transceivers and Registers with TRI-STATE ® Outputs General Description The ’ABT646 consists of bus transceiver circuits with TRI-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. Features n Independent registers for A and B buses n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9457701 Ordering Code Military 54ABT646J-QML 54ABT646W-QML 54ABT646E-QML Package Number J24A W24C E28A 24-Lead Cerpack 28-Lead Ceramic Leadless Chip Carrier, Type C Package Description 24-Lead Ceramic Dual-In-Line TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100209 www.national.com Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100209-4 DS100209-3 Pin Descriptions Pin Names A0–A7 B0–B7 CPAB, CPBA SAB, SBA OE DIR Select Inputs Output Enable Input Direction Control Input Data Register A Inputs/ TRI-STATE Outputs Data Register B Inputs/ TRI-STATE Outputs Clock Pulse Inputs Description www.national.com 2 Connection Diagrams (Continued) Storage from Bus to Register Real Time Transfer A-Bus to B-Bus DS100209-7 DS100209-5 FIGURE 3. Transfer from Register to Bus FIGURE 1. Real Time Transfer B-Bus to A-Bus DS100209-8 DS100209-6 FIGURE 4. FIGURE 2. Inputs OE H H H L L L L L L L L DIR X X X H H H H L L L L CPAB H or L N Data I/O (Note 1) X X X L L H H X X X X X X X X X X X L L H H Output Input Input Output Input Input Isolation Function CPBA SAB SBA A0–A7 B0–B7 H or L X N Clock An Data into A Register Clock Bn Data into B Register An to Bn — Real Time (Transparent Mode) Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An — Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An X X N X X X X X N H or L N X X X X H or L N H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. 3 www.national.com Logic Diagram DS100209-9 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 4 Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns −0.5V to +5.5V −0.5V to VCC twice the rated IOL (mA) −500 mA Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 54ABT 54ABT 54ABT 4.75 5 5 Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 5) No Load −100 7 100 −5 −5 50 −50 −275 50 100 250 30 50 2.5 0.18 µA µA mA µA µA µA mA µA mA mA/MHz 0V–5.5V 0V–5.5V Max Max 0.0V Max Max Max Max Max µA µA µA Max Max Max 2.5 2.0 0.55 V V µA 2.0 0.8 −1.2 ABT646 Min Typ Max V V V V Min Min 0.0 Max Min Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −24 mA, (An, Bn) IOL = 48 mA, (An, Bn) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 5) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) VIN = 0.5V (Non-I/O Pins) (Note 5) VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); OE = 2.0V VOUT = 0.5V (An, Bn); OE = 2.0V VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs TRI-STATE; All Others GND VI = VCC − 2.1V All Other Outputs at VCC or GND Outputs Open OE and DIR = GND, Non-I/O = GND or VCC (Note 4) One Bit toggling, 50% duty cycle Units VCC Conditions Input Leakage Test Input HIGH Current 5 www.national.com DC Electrical Characteristics Note 4: For 8-bit toggling, ICCD < 1.4 mA/MHz. Note 5: Guaranteed but not tested. (Continued) AC Electrical Characteristics 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V CL = 50 pF Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Max Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An to Bn Enable Time OE to An or Bn Disable Time OE to An or Bn Enable Time DIR to An or Bn Disable Time DIR to An or Bn 125 2.2 1.7 1.5 1.5 1.5 1.5 1.0 1.9 1.5 1.5 1.0 2.2 1.5 1.5 8.8 8.8 7.9 7.9 8.1 8.9 7.3 8.8 9.3 9.3 7.7 9.5 8.7 9.2 ns ns ns ns ns ns Max MHz ns Fig. Units No. Symbol Parameter Figure 8 Figure 8 Figure 8 Figure 10 Figure 10 Figure 10 Figure 10 AC Operating Requirements 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Pulse Width, HIGH or LOW 4.0 ns 1.0 ns 3.5 Max ns Fig. Units No. Symbol Parameter Figure 11 Figure 11 Figure 9 Capacitance Symbol CIN CI/O (Note 6) Parameter Input Capacitance Output Capacitance Typ 5 11 Units pF pF Conditions TA = 25˚C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) Note 6: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 6 Capacitance (Continued) tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus DS100209-18 DS100209-19 tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus DS100209-20 DS100209-21 tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus DS100209-22 DS100209-23 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 www.national.com Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Bus tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Bus DS100209-24 DS100209-25 tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Bus DS100209-26 DS100209-27 tPZH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus tPHZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus DS100209-28 DS100209-29 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 8 Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus tPLZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus DS100209-30 DS100209-31 tPZL vs Load Capacitance 8 Outputs Switching, TA = 25˚C OE to Bus tPZH vs Load Capacitance 8 Outputs Switching, TA = 25˚C OE to Bus DS100209-32 DS100209-33 tPLH and tPHL vs Number Output Switching VCC = 5.0V, TA = 25˚C CL = 50 pF, Clock to Bus DS100209-34 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 9 www.national.com Capacitance (Continued) ICC vs Frequency, Average, TA = 25˚C, VCC = 5.5V All Outputs Unloaded/Unterminated; All Outputs Switching in phase @50% Duty Cycle DS100209-35 tSET LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock tSET HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock DS100209-36 DS100209-37 tHOLD LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock tHOLD HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock DS100209-38 DS100209-39 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 10 AC Loading DS100209-10 *Includes jig and probe capacitance FIGURE 5. Standard AC Test Load DS100209-11 FIGURE 9. Propagation Delay, Pulse Width Waveforms DS100209-12 FIGURE 6. Test Input Signal Levels Input Pulse Requirements DS100209-13 FIGURE 10. TRI-STATE Output HIGH and LOW Enable and Disable Times tf 2.5 ns Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns FIGURE 7. Test Input Signal Requirements DS100209-15 DS100209-14 FIGURE 8. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 11. Setup Time, Hold Time and Recovery Time Waveforms 11 www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-in-Line Package (D) NS Package Number J24A 13 www.national.com 54ABT646 Octal Transceivers and Registers with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak Package (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.