54ABT652

54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs August 1998 54ABT652 Octal Transceivers and Registers with TRI-STATE ® Outputs General Description The ’ABT652 consists of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9324201 Features n Independent registers for A and B buses Ordering Code: Commercial 54ABT652J-QML 54ABT652W-QML 54ABT652E-QML Package Number J24A W24C E28A 24-Lead Ceramic Dual-in-line 24-Lead Cerpack 28-Lead Ceramic Leadless Chip Carrier, Type C Package Description Connection Diagram Pin Assignment for DIP and Flatpack DS100220-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100220 www.national.com Connection Diagram (Continued) Pin Assignment for LCC DS100220-48 www.national.com 2 Pin Descriptions Pin Names A0–A7 B0–B7 CPAB, CPBA SAB, SBA OEAB, OEBA Description Data Register A Inputs/TRI-STATE Outputs Data Register B Inputs/TRI-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs Logic Diagram DS100220-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Functional Description In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ’ABT652C. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. 3 www.national.com Functional Description (Continued) Note C: Storage Note A: Real-Time Transfer Bus B to Bus A DS100220-6 DS100220-4 OEAB OEAB L OEBA L CPAB X CPBA X SAB X SBA L X L L OEBA H X H CPAB N X N CPBA X N N SAB X X X SBA X X X Note B: Real-Time Transfer Bus A to Bus B Note D: Transfer Storage Data to A or B DS100220-7 DS100220-5 OEAB OEAB H OEBA H CPAB X CPBA X SAB L SBA X H OEBA L CPAB H or L CPBA H or L SAB H SBA H FIGURE 1. www.national.com 4 Functional Description Inputs OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CPAB H or L N N N H or L N X X X H or L H or L CPBA H or L N H or L N N N X H or L X X H or L (Continued) Inputs/Outputs (Note 1) SAB X X X X X X X X L H H SBA X X X X X X L H X X H Output Output Input Output Input Input Not Specified Output Output Not Specified Output Input Input Input A0 thru A7 Input B0 thru B7 Input Isolation Store A and B Data Store A, Hold B Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus Operating Mode H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW to HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. 5 www.national.com Absolute Maximum Ratings (Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns −0.5V to +5.5V −0.5V to VCC twice the rated IOL (mA) −500 mA Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input −50 −2 50 −50 −180 50 250 30 250 2.5 µA µA µA mA µA µA mA µA mA Max 0V–5.5V 0V–5.5V Max Max Max Max Max Max VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); OEBA = 2.0V and OEAB = GND = 2.0V VOUT = 0.5V (An, Bn); OEBA = 2.0V and OEAB = GND = 2.0V VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) All Outputs HIGH All Outputs LOW Outputs TRI-STATE; All others at VCC or GND VI = VCC − 2.1V All others at VCC or GND Note 4: Guaranteed but not tested. Note 5: For 8 outputs toggling, ICCD < 1.4 mA/MHz. Note 6: Guaranteed, but not tested. ABT652 Min Typ 2.0 0.8 −1.2 2.5 2.0 0.55 2 7 100 Max Units V V V V V µA µA µA VCC Conditions Recognized HIGH Signal Min Min Min Max Max Max 54ABT 54ABT 54ABT Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −24 mA, (An, Bn) IOL = 48 mA, (An, Bn) VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) www.national.com 6 DC Electrical Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Max 1.2 -1.8 Units V V VCC 5.0 5.0 Conditions CL = 50 pF, RL = 500Ω TA = 25˚C (Note 7) TA = 25˚C (Note 7) Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V CL = 50 pF Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Max Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An to Bn Enable Time OEBA or OEAB to An or Bn Disable Time OEBA or OEAB to An or Bn 125 1.4 1.2 1.5 1.5 1.2 1.2 1.3 2.0 1.5 1.5 7.8 8.4 6.7 6.7 6.9 7.7 5.6 7.8 8.2 7.3 ns ns ns ns Max MHz ns Fig. Units No. Symbol Parameter Figure 5 Figure 5 Figure 5 Figure 7 Figure 7 AC Operating Requirements 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Pulse Width, HIGH or LOW 4.0 ns 1.5 ns 3.5 Max ns Fig. Units No. Symbol Parameter Figure 8 Figure 8 Figure 6 7 www.national.com Capacitance Symbol CIN CI/O (Note 8) Parameter Input Capacitance I/O Capacitance Max 14.0 19.5 Units pF pF Conditions (TA = 25˚C) VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) Note 8: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883D, Method 3012. www.national.com 8 Capacitance (Continued) tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus DS100220-16 DS100220-17 tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Bus tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Bus DS100220-18 DS100220-19 tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching SBA or SAB to An or Bn tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching SBA or SAB to An or Bn DS100220-20 DS100220-21 9 www.national.com Capacitance (Continued) tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus DS100220-22 DS100220-23 tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C Bus to Bus tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C Bus to Bus DS100220-24 DS100220-25 tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C SBA or SAB to An or Bn tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C SBA or SAB to An or Bn DS100220-26 DS100220-27 www.national.com 10 Capacitance (Continued) tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus DS100220-28 DS100220-29 tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C Bus to Bus tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C Bus to Bus DS100220-30 DS100220-31 tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C SBA or SAB to An or Bn tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C SBA or SAB to An or Bn DS100220-32 DS100220-33 11 www.national.com Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100220-34 DS100220-35 tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100220-36 DS100220-37 tPZH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching tPHZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching DS100220-38 DS100220-39 www.national.com 12 Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching tPLZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching DS100220-40 DS100220-41 tPZL vs Load Capacitance 8 Outputs Switching TA = 25˚C tPZH vs Load Capacitance 8 Outputs Switching TA = 25˚C DS100220-42 DS100220-43 tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF Clock to Bus tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF Bus to Bus DS100220-44 DS100220-45 13 www.national.com Capacitance (Continued) tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF SBA or SAB to Anor Bn DS100220-46 www.national.com 14 AC Loading DS100220-8 *Includes jig and probe capacitance FIGURE 2. Standard AC Test Load FIGURE 6. Propagation Delay, Pulse Width Waveforms DS100220-9 DS100220-10 FIGURE 3. Test Input Signal Levels DS100220-11 FIGURE 7. TRI-STATE Output HIGH and LOW Enable and Disable Times Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns tf 2.5 ns FIGURE 4. Test Input Signal Requirements DS100220-13 DS100220-12 FIGURE 8. Setup Time, Hold Time and Recovery Time Waveforms FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 15 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-in-line NS Package Number J24A 24-Lead Cerpack NS Package Number W24C www.national.com 16 54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. 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