54ACT112

54ACT112 Dual JK Negative Edge-Triggered Flip-Flop OBSOLETE 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 'ACT112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: July 20, 2009 LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features ■ 'ACT112 has TTL-compatible inputs ■ Outputs source/sink 24 mA ■ Standard Microcircuit Drawing (SMD) 5962-8995001 Connection Diagrams Pin Assigment for DIP and Flatpack Pin Descriptions Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs Description 10097603 Pin Assigment for LCC 10097605 FACT™ is a trademark of Fairchild Semiconductor © 2009 National Semiconductor Corporation 100976 Print Date/Time: 2009/07/20 16:20:36 www.national.com 100976 Version 2 Revision 2 54ACT112 Logic Symbols IEEE/IEC 10097601 10097604 10097602 Truth Table Inputs SD L H L H H H H CD H L L H H H H CP X X X M M M M J X X X h l h l K X X X h h l l Outputs Q H L H Q0 L H Q0 Q L H H Q0 H L Q0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial M = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. www.national.com 100976 Version 2 Revision 2 2 Print Date/Time: 2009/07/20 16:20:36 54ACT112 Logic Diagram (One Half Shown) 10097606 3 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 www.national.com 54ACT112 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + O.5 DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC +0.5V ±50 mA ±50 mA −65°C to +150°C 175°C Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (ΔV/Δt) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC −55°C to +125°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT™ circuits outside databook specifications. DC Characteristics for 'ACT Family Devices Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 TA = −55°C to +125°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 VIN = VIL or VIH 3.70 4.70 0.1 0.1 VIN = VIL or VIH 0.5 0.5 ± 1.0 1.6 50 −50 80.0 μA mA mA mA μA V IOL = 24 MA IOL = 24 mA V V IOH = −24 mA IOH = −24 mA V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 μA Units Conditions (Note 2) IOUT = 50 μA (Note 2) VI = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. www.national.com 100976 Version 2 Revision 2 4 Print Date/Time: 2009/07/20 16:20:36 54ACT112 AC Electrical Characteristics for 'ACT Family Devices Symbol Parameter VCC (V) TA = −55°C to +125°C CL = 50 pF Min 80 1.0 1.0 1.0 1.0 14.0 14.0 13.5 13.5 Max MHz ns ns ns ns Units Fig. No. (Note 4) fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Note 4: Voltage Range 5.0 is 5.0V ±0.5V 5.0 5.0 5.0 5.0 5.0 AC Operating Requirements: Symbol Parameter VCC (V) TA = −55°C to +125°C CL = 50 pF Guaranteed Minimum 8.0 1.5 5.0 3.0 ns ns ns ns Units Fig. No. (Note 5) tS tH tW trec Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn Pulse Width CPn or CDn or SDn Recovery Time CDn or SDn to CPn Note 5: Voltage Range 5.0 is 5.0V ±0.5V 5.0 5.0 5.0 5.0 Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Max 10.0 60 Units pF pF Conditions VCC = OPEN VCC = 5.0V 5 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 www.national.com 54ACT112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Ceramic Dual-in-line Package Number J16A 16-Lead Cerpack Package Number W16A www.national.com 100976 Version 2 Revision 2 6 Print Date/Time: 2009/07/20 16:20:36 54ACT112 20-Lead Ceramic Leadless Chip Carrier Package Number E20A 7 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 www.national.com 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero PowerWise® Design University Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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Copyright© 2009 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: support@nsc.com www.national.com Tel: 1-800-272-9959 National Semiconductor Europe Technical Support Center Email: europe.support@nsc.com National Semiconductor Asia Pacific Technical Support Center Email: ap.support@nsc.com National Semiconductor Japan Technical Support Center Email: jpn.feedback@nsc.com 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36