54ACT 74ACT534 Octal D Flip-Flop with TRI-STATE Outputs
March 1993
54ACT 74ACT534 Octal D Flip-Flop with TRI-STATE Outputs
General Description
The ’ACT534 is a high-speed low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops The ’ACT534 is the same as the ’ACT374 except that the outputs are inverted
Features
Y Y Y Y Y Y Y
ICC and IOZ reduced by 50% Edge-triggered D-type inputs Buffered positive edge-triggered clock TRI-STATE outputs for bus-oriented applications Outputs source sink 24 mA ’ACT534 has TTL-compatible inputs Inverted output version of ’ACT374
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment for DIP Flatpak and SOIC
TL F 9965–1
TL F 9965 – 2 TL F 9965 – 3
Pin Names D0 – D7 CP OE O0 – O7
Description Data Inputs Clock Pulse Input TRI-STATE Output Enable Input Complementary TRI-STATE Outputs
Pin Assignment for LCC
TL F 9965 – 4
TRI-STATE is a registered trademark of National Semiconductor Corporation FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
TL F 9965
RRD-B30M75 Printed in U S A
Functional Description
The ’ACT534 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE complementary outputs The buffered clock and buffered Output Enable are common to all flip-flops The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition With the Output Enable (OE) LOW the contents of the eight flip-flops are available at the outputs When the OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect the state of the flip-flops
Logic Diagram
TL F 9965 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
Function Table Inputs CP L L L X OE L L L H D H L X X Output O L H O0 Z
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition Z e High Impedance O0 e Value stored from previous clock cycle
2
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0 5V VI e VCC a 0 5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0 5V VO e VCC a 0 5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP PDIP
b 0 5V to a 7 0V b 20 mA a 20 mA b 0 5V to VCC a 0 5V b 20 mA a 20 mA b 0 5V to VCC a 0 5V
g 50 mA g 50 mA
Recommended Operating Conditions
Supply Voltage (VCC) ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 74ACT 54ACT Minimum Input Edge Rate (DV Dt) ’ACT Devices VIN from 0 8V to 2 0V VCC 4 5V 5 5V 4 5V to 5 5V 0V to VCC 0V to VCC
b 40 C to a 85 C b 55 C to a 125 C
125 mV ns
b 65 C to a 150 C
175 C 140 C
Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of FACT TM circuits outside databook specifications
DC Characteristics for ’ACT Family Devices
74ACT Symbol Parameter VCC (V) TA e a 25 C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 45 55 45 55 45 55 45 55 VOL Maximum Low Level Output Voltage 45 55 45 55 IIN IOZ ICCT Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC Input 55 55 55 06 0 001 0 001 15 15 15 15 4 49 5 49 20 20 08 08 44 54 3 86 4 86 01 01 0 36 0 36
g0 1 g 0 25
54ACT
74ACT Conditions
TA e TA e Units b 55 C to a 125 C b 40 C to a 85 C Guaranteed Limits 20 20 08 08 44 54 3 70 4 70 01 01 0 50 0 50
g1 0 g5 0
20 20 08 08 44 54 3 76 4 76 01 01 0 44 0 44
g1 0 g2 5
V V V
VOUT e 0 1V or VCC b 0 1V VOUT e 0 1V or VCC b 0 1V IOUT e b50 mA VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA VIN e VIL or VIH 24 mA IOL 24 mA VI e VCC GND VI e VIL VIH VO e VCC GND VI e VCC b 2 1V
V V
V mA mA mA
16
15
All outputs loaded thresholds on input associated with output under test
3
DC Characteristics for ’ACT Family Devices (Continued)
74ACT Symbol Parameter VCC (V) TA e a 25 C Typ IOLD IOHD ICC Minimum Dynamic Output Current Maximum Quiescent Supply Current 55 55 55 40 54ACT TA e b 55 C to a 125 C 74ACT TA e b 40 C to a 85 C Units Conditions
Guaranteed Limits 50
b 50
75
b 75
mA mA mA
VOLD e 1 65V Max VOHD e 3 85V Min VIN e VCC or GND
80 0
40 0
Maximum test duration 2 0 ms one output loaded at a time Note ICC for 54ACT 25 C is identical to 74ACT 25 C
AC Electrical Characteristics
74ACT Symbol Parameter VCC (V) Min fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Output Enable Time Output Enable Time Output Disable Time Output Disable Time 50 50 50 50 50 50 50 25 20 25 20 15 15 TA e a 25 C CL e 50 pF Typ 100 65 60 65 60 70 55 11 5 10 5 12 0 11 0 12 5 10 5 Max 54ACT TA e b55 C to a 125 C CL e 50 pF Min 85 15 15 15 15 15 15 14 0 13 0 14 0 13 0 14 5 11 5 Max 74ACT TA e b40 C to a 85 C CL e 50 pF Min 120 20 20 20 20 10 10 12 5 12 0 12 5 11 5 13 5 10 5 Max MHz ns ns ns ns ns ns Units
Voltage Range 5 0 is 5 0V g 0 5V
AC Operating Requirements
74ACT Symbol Parameter VCC (V) TA e a 25 C CL e 50 pF Typ ts th tw Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW 50 50 50 10
b1 0
54ACT TA e b55 C to a 125 C CL e 50 pF
74ACT TA e b40 C to a 85 C CL e 50 pF Units
Guaranteed Minimum 35 10 35 50 30 50 40 15 35 ns ns ns
20
Voltage Range 5 0 is 5 0V g 0 5V
4
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 45 40 0 Units pF pF Conditions VCC e OPEN VCC e 5 0V
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74ACT Temperature Range Family 74ACT e Commercial TTL-Compatible 54ACT e Military TTL-Compatible Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) 534 P C QR Special Variations X e Devices shipped in 13 reels QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (b40 C to a 85 C) M e Military (b55 C to a 125 C)
Physical Dimensions inches (millimeters)
20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A
5
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A
16 Lead Small Outline Integrated Circuit (S) NS Package Number M16A
6
Physical Dimensions inches (millimeters) (Continued)
16 Lead Plastic Dual-In-Line Package (P) NS Package Number N16E
7
54ACT 74ACT534 Octal D Flip-Flop with TRI-STATE Outputs
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Flatpak (F) NS Package Number W16A
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