54ETL16245

54 74ETL16245 16-Bit Data Transceiver with Incident Wave Switching PRELIMINARY May 1994 54 74ETL16245 16-Bit Data Transceiver with Incident Wave Switching General Description The 54 74ETL16245 contains sixteen non-inverting bidirectional buffers with TRI-STATE outputs designed with incident wave switching live insertion support and enhanced noise margin for TTL backplane applications Both the A and B ports include a bus hold circuit to latch the output to the value last forced on that pin The B port of this device includes 25X series output resistors which minimize undershoot and ringing Y Y Y Y Y Y Y Y Y Features Y Y Supports the VME64 ETL specification Functionally and pin compatible with industry standard TTL 16245 SSOP pinout Y Improved TTL-compatible input threshold range High drive TTL-compatible outputs (IOH e b60 mA IOL e 90 mA) Supports 25X incident wave switching on the A port BiCMOS design significantly reduces power dissipation Distributed VCC and GND pin configuration minimizes high-speed switching noise 25X series-dampening resistor on B-port Available in 48-pin SSOP and ceramic flatpak Guaranteed output skew Guaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed latchup protection Logic Symbol Connection Diagram Pin Assignment for SSOP and Flatpak TL F 11654 – 1 Pin Description Pin Names DIR OE An Bn Description Transmit Receive Input Output Enable Input (Active LOW) Backplane Bus Data Local Bus Data TL F 11654 – 2 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11654 RRD-B30M105 Printed in U S A Functional Description The device uses byte-wide Direction (DIR) control and Output Enable (OE) controls The DIR inputs determine the direction of data flow through the device The OE inputs disable the A and the B ports The part contains active circuitry which keeps all outputs disabled when VCC is less than 2 2V to aid in live insertion applications Truth Table (Each 8-bit Section) Inputs OE L L H DIR L H X A Data to B Bus B Data to A Bus Isolation Operation Logic Diagrams (Positive Logic) TL F 11654–3 TL F 11654 – 4 ETL’s Improved Noise Immunity TTL input thresholds are typically determined by temperature-dependent junction voltages which result in worst case input thresholds between 0 8V and 2 0V By contrast ETL provides greater noise immunity because its input thresholds are determined by current mode input circuits similar to those used for ECL or BTL ETL’s worst case input thresholds between 1 4V and 1 6V are compensated for temperature voltage and process variations Incident Wave Switching When TTL logic is used to drive fully loaded backplanes the combination of low backplane bus characteristic impedance wide TTL input threshold range and limited TTL drive generally require multiple waveform reflections before a valid signal can be received across the backplane The VME International Trade Association (VITA) defined ETL to provide incident wave switching which increases the data transfer rate of a VME backplane and extends the life of VME applications TTL compatibility with existing VME backplanes and modules was maintained Improved Input Threshold Characteristics of ETL TL F 11654–5 TL F 11654 – 6 ABTC Worst Case VOUT – VIN ETL Worst Case VOUT –VIN 2 Incident Wave Switching (Continued) To demonstrate the incident wave switching capability consider a VME application A VME bus must be terminated to a 2 94V with 190X at each end of its 21 card backplane The surge impedance presented by a fully loaded VME backplane is approximately 25X If the output voltage current of an ABTC driver is plotted with this load the intersection at 1 2V for a falling edge and at 1 6V for a rising edge does not reach the worst case input threshold of a second ABTC circuit This is shown in the two figures below However an ETL driver located at one end of the backplane is able to provide incident wave switching because it has a higher drive and a tighter input threshold Estimated ETL ABTC Initial Falling Edge Step TL F 11654 – 7 Because ETL has a much more precise input threshold region an ETL receiver will interpret its predicted falling input of 0 85V as a logic ZERO and the initial rising edge of 1 9V as a logic ONE This comparison is for the case of a 25X surge impedance backplane driven from one end Estimated ETL ABTC Initial Rising Edge Step TL F 11654 – 8 The resulting ABTC and ETL waveform predictions and their input thresholds are compared below This shows how ETL can achieve backplane speeds not always possible with conventional TTL compatible logic families Comparing the Incident Wave Switching of ETL with ABTC TL F 11654 – 9 3 Incident Wave Switching (Continued) The figure VCC Power-up Critical Voltages shows the relationship between OE and VCC while power is being applied and removed TL F 11654 – 10 VCC and OE Power-up Relationship 4 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) b 65 C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C b 0 5V to a 7 0V b 0 5V to a 7 0V b 50 mA to a 5 0 mA DC Latchup Source Current Over Voltage Latchup (I O) b 500 mA 10V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial Minimum Input Edge Rate Data Input Enable Input b 55 C to a 125 C b 40 C to a 85 C a 4 5V to a 5 5V a 4 5V to a 5 5V b 0 5V to 5 5V b 0 5V to VCC 128 mA (Dt DV) 20 ns V 50 ns V DC Electrical Characteristics Symbol VIH Parameter Min Input HIGH Voltage OE Other Inputs VIL Input LOW Voltage OE Other Inputs VCD VOH Input Clamp Diode Voltage Output HIGH Voltage B Port 24 20 VCC b 1 A Port VOL Output LOW Voltage 24 20 04 08 0 55 09 100 mA b 100 ETL16245 Typ Max Units VCC Conditions Recognized HIGH Signal 20 16 08 14 b1 2 V V V V V V V V V V V V V Min Min Recognized LOW Signal IIN e b18 mA (OEn DIR) IOH e b100 mA IOH e b1 mA IOH e b12 mA IOH e b1 mA IOH e b32 mA IOH e b60 mA IOL e 1 mA IOL e 12 mA IOL e 64 mA IOL e 90 mA OE e HIGH VO e 0 8V OE e HIGH VO e 2 0V VCC b 1 Min B Port A Port Min Min IHOLD Bus Hold Current A Port B Port Min IOFF II Output Current Power Down Input Current Control Pins 54ETL 74ETL 100 g 10 g5 mA mA mA mA mA 00 55 55 55 55 VCC Bias e 0V VI or VO s 4 5V VIN e 0 or VCC VIN e 0 or VCC VOUT e 2 7V OE e 2 0V VOUT e 0 5V OE e 2 0V IIH a IOZH IIL a IOZL Output Leakage Current Output Leakage Current 50 b 50 5 DC Electrical Characteristics Symbol ICCH ICCL ICCZ Parameter (Continued) ETL16245 Units Max 40 80 mA mA VCC Max Max Conditions All Outputs HIGH OE e LOW DIR e HIGH or LOW All Outputs LOW OE e LOW DIR e HIGH or LOW OE e HIGH All Others at VCC or GND DIR e HIGH or LOW Outputs Open OEn e GND DIR e HIGH One Bit Toggling 50% Duty Cycle TA e 25 C (Note 2) CL e 50 pF RL e 500X TA e 25 C (Note 2) CL e 50 pF RL e 500X TA e 25 C (Note 4) CL e 50 pF RL e 500X TA e 25 C (Note 3) CL e 50 pF RL e 500X TA e 25 C (Note 3) CL e 50 pF RL e 500X Min Power Supply Current Power Supply Current Power Supply Current Typ 40 ICCD Dynamic ICC No Load (Note 1) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Output Voltage (Note 1) Minimum High Level Dynamic Input Voltage (Note 1) Maximum Low Level Dynamic Input Voltage (Note 1) 20 b1 4 mA Max 0 15 mA MHz V V Max 50 VOLP VOLV VOHV VIHD VILD 10 50 50 50 50 27 15 12 08 V V V Note 1 Guaranteed but not tested Note 2 Max number of outputs defined as (n) n b 1 data inputs are driven 0V to 3V One output at LOW Guaranteed but not tested Note 3 Max number of data inputs (n) switching n b 1 inputs switching 0V to 3V Input-under-test switching 3V to threshold (VILD) 0V to threshold (VIHD) Guaranteed but not tested Note 4 Max number of outputs defined as (n) n b 1 data inputs are driven 0V to 3V One output HIGH Guaranteed but not tested AC Electrical Characteristics 74ETL Symbol Parameter TA e a 25 C VCC e a 5V Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tr tf Propagation Delay An to Bn Propagation Delay Bn to An Output Enable Time Output Disable Time Rise Time 1V An Outputs Fall Time 2V An Outputs 15 15 15 15 10 10 10 10 12 12 Typ Max 70 70 70 70 70 70 70 70 30 30 54ETL TA e b55 C to a 125 C VCC e 4 5V – 5 5V Min Max 74ETL TA e b40 C to a 85 C VCC e 4 5V – 5 5V Min 15 15 15 15 10 10 10 10 12 12 Max 70 70 70 70 70 70 70 70 30 30 ns ns ns ns ns ns 124 124 123 123 124 124 Units Fig No x 2V x 1V 6 Skew 74ETL Symbol Parameter TA e b40 C to a 85 C VCC e 4 5V – 5 5V 16 Outputs Switching Max tOHS (Notes 1 2) tOHS (Notes 1 2) tPS (Notes 1 2) tPS (Notes 1 2) Pin-to-Pin Skew LH HL An to Bn Pin-to-Pin Skew LH HL Bn to An Duty Cycle Skew Bn to An Duty Cycle Skew An to Bn 13 13 20 20 54ETL TA e b55 C to a 125 C VCC e 4 5V – 5 5V 16 Outputs Switching Max ns ns ns ns Units Conditions Figures 1 2 4 Figures 1 2 4 Figures 1 2 4 Figures 1 2 4 VME Extended Skew 74ETL Symbol Parameter TA e b40 C to a 85 C VCC e 4 5V – 5 5V 16 Outputs Switching Max tPV (Notes 1 2) tCP (Notes 1 2) tCP (Note 1 3) tCPV (Notes 1 2 3) Device-to-Device Skew LH HL Transitions Bn to An Device-to-Device Skew LH HL Transitions An to Bn Change in Propagation Delay with Load Bn to An Device-to-Device Change in Propagation Delay with with Load Bn to An 40 25 40 54ETL TA e b55 C to a 125 C VCC e 4 5V – 5 5V 16 Outputs Switching Max ns ns ns Units Conditions Figures 1 2 4 Figures 1 2 4 Figures 1 2 4 60 ns Figures 1 2 4 Note 1 Skew is defined as the absolute difference in delay between two outputs The specification applies to any outputs switching HIGH to LOW LOW to HIGH or any combination switching HIGH-to-LOW or LOW-to-HIGH This specification is guaranteed but not tested Note 2 This is measured with both devices at the same value of VCC g 1% and with package temperature differences of 20 C from each other Note 3 This is measured with Rx in Figure 1 at 13X for one unit and at 56X for the other unit Capacitance Symbol CIN CI O (Note 1) Parameter Input Capacitance Output Capacitance Typ 5 9 Max 8 12 Units pF pF Conditions TA e 25 C VCC e 0 0V (OEn DIR) VCC e 5 0V (An) Note 1 CI O is measured at frequency f e 1 MHz per MIL-STD-883B Method 3012 7 AC Loading Test tPHZ tPLZ tPZH tPZL tPLH tPHL tPLH tPHL tr tf Includes jig and probe capacitance TL F 11654 – 11 Port AB AB A B A A B A A SW1 a7 a7 SW2 Open Open Closed Open Closed Closed Open Closed Closed Rx Open Open Open Open Open Open Open 26 26 26 tPV tCP tCP tCPV FIGURE 1 Standard AC Test Load Note 1 Defined to emulate the range of VME bus transmission line loading as a function of board population and driver location Rx e 13X 26X or 56X depending on test 13 then 56 13 and 56 FIGURE 1a TL F 11654 – 13 TL F 11654 – 12 FIGURE 2 Input Pulse Requirements Amplitude 3 0V Rep Rate 1 MHz tw 500 ns tr 2 5 ns tf 2 5 ns FIGURE 3 TRI-STATE Output HIGH and LOW Enable and Disable Times FIGURE 2a Test Input Signal Requirements TL F 11654 – 14 FIGURE 4 Rise Fall Time and Propagation Delay Waveforms 8 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 54 74 Temperature Range Family VME74 e Commercial VME54 e Military Device Type Package Code SS e Small Outline (SSOP) FPFP e Fine Pitch Flatpak ETL16245 SS C X Special Variations X e Devices shipped in 13 reels QB e Military grade device with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (b40 C to a 85 C) M e Military (b55 C to a 125 C) Physical Dimensions inches (millimeters) 48-Lead SSOP (0 300 Wide) (SS) NS Package Number MS48A 9 54 74ETL16245 16-Bit Data Transceiver with Incident Wave Switching Physical Dimensions inches (millimeters) (Continued) 48-Pin Ceramic Flatpak (FPFP) NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications