54F161AFM

54F 74F161A  54F 74F163A Synchronous Presettable Binary Counter November 1994 54F 74F161A  54F 74F163A Synchronous Presettable Binary Counter General Description The ’F161A and ’F163A are high-speed synchronous modulo-16 binary counters They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters The ’F161A has an asynchronous Master-Reset input that overrides all other inputs and forces the outputs LOW The ’F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock The ’F161A and ’F163A are high-speed versions of the ’F161 and ’F163 Features Y Y Y Y Synchronous counting and loading High-speed synchronous expansion Typical count frequency of 120 MHz Guaranteed 4000V minimum ESD protection Commercial 74F161APC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F161ADM (Note 2) 74F161ASC (Note 1) 74F161ASJ (Note 1) 54F161AFM (Note 2) 54F161ALM (Note 2) 74F163APC 54F163ADM (Note 2) 74F163ASC (Note 1) 74F163ASJ (Note 1) 54F163AFM (Note 2) 54F163ALM (Note 2) J16A M16A M16D W16A E20A N16E J16A M16A M16D W16A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Connection Diagrams Pin Assignment for DIP SOIC and Flatpak ’F161A Pin Assignment for LCC ’F161A Pin Assignment for DIP SOIC and Flatpak ’F163A Pin Assignment for LCC ’F163A TL F 9486–1 TL F 9486 – 2 TL F 9486 – 7 TL F 9486 – 8 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9486 RRD-B30M75 Printed in U S A Logic Symbols ’F161A ’F163A TL F 9486–3 TL F 9486 – 9 IEEE IEC ’F161A IEEE IEC ’F163A TL F 9486–6 TL F 9486 – 10 Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 20 10 10 10 10 10 20 10 10 10 20 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b1 2 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b1 2 mA 20 mA b0 6 mA 20 mA b1 2 mA b 1 mA 20 mA b 1 mA 20 mA CEP CET CP MR (’F161A) SR (’F163A) P0 – P3 PE Q 0 – Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output 2 Functional Description The ’F161A and ’F163A count in modulo-16 binary sequence From state 15 (HHHH) they increment to state 0 (LLLL) The clock inputs of all flip-flops are driven in parallel through a clock buffer Thus all changes of the Q outputs (except due to Master Reset of the ’F161A) occur as a result of and synchronous with the LOW-to-HIGH transition of the CP input signal The circuits have four fundamental modes of operation in order of precedence asynchronous reset (’F161A) synchronous reset (’F163A) parallel load count-up and hold Five control inputs Master Reset (MR ’F161A) Synchronous Reset (SR ’F163A) Parallel Enable (PE) Count Enable Parallel (CEP) and Count Enable Trickle (CET) determine the mode of operation as shown in the Mode Select Table A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP With PE and MR (’F161A) or SR (’F163A) HIGH CEP and CET permit counting when both are HIGH Conversely a LOW signal on either CEP or CET inhibits counting The ’F161A and ’F163A use D-type edge triggered flip-flops and changing the SR PE CEP and CET inputs when the CP is in either state does not cause errors provided that the recommended setup and hold times with respect to the rising edge of CP are observed The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15 To implement synchronous multi-stage counters the TC outputs can be used with the CEP and CET inputs in two different ways Please refer to the ’F568 data sheet The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops counters or registers Logic Equations Count Enable e CEP  CET  PE TC e Q0  Q1  Q2  Q3  CET State Diagram Mode Select Table SR L H H H H PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge (L) Reset (Clear) Load (Pn x Qn) Count (Increment) No Change (Hold) No Change (Hold) For ’F163A only H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial TL F 9486 – 5 3 Block Diagram 4 TL F 9486 – 4 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current b 60 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 25 25 27 05 05 20 0 50 100 70 250 50 4 75 3 75 b0 6 b1 2 b 150 VOL IIH IBVI ICEX VID IOD IIL IOS ICC V mA mA mA V mA mA mA mA mA Min Max Max Max 00 00 Max Max Max Max IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (CEP CP MR P0 –P3) VIN e 0 5V (CET PE SR) VOUT e 0V 37 55 5 AC Electrical Characteristics 74F Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Maximum Count Frequency Propagation Delay CP to Qn (PE Input HIGH) Propagation Delay CP to Qn (PE Input LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay MR to Qn (’F161A) Propagation Delay MR to TC (’F161A) 100 35 35 40 40 50 50 25 25 55 45 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 120 55 75 60 60 10 0 10 0 45 45 90 80 75 10 0 85 85 14 0 14 0 75 75 12 0 10 5 Max 54F TA VCC e Mil CL e 50 pF Min 75 35 35 40 40 50 50 25 25 55 45 90 11 5 10 0 10 0 16 5 15 5 90 90 14 0 12 5 Max 74F TA VCC e Com CL e 50 pF Min 90 35 35 40 40 50 50 25 25 55 45 85 11 0 95 95 15 0 15 0 85 85 13 0 11 5 ns ns ns ns Max MHz Units ns AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tw(L) tw(L) trec Setup Time HIGH or LOW Pn to CP Hold Time HIGH or LOW Pn to CP Setup Time HIGH or LOW PE or SR to CP Hold Time HIGH or LOW PE or SR to CP Setup Time HIGH or LOW CEP or CET to CP Hold Time HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW MR Pulse Width LOW (’F161A) Recovery Time MR to CP (’F161A) 50 50 20 20 11 0 85 20 0 11 0 50 0 0 50 50 40 60 50 60 Max 54F TA VCC e Mil Min 55 55 25 25 13 5 10 5 36 0 13 0 60 0 0 50 50 50 80 50 60 Max 74F TA VCC e Com Min 50 50 20 20 11 5 95 20 0 11 5 50 0 0 50 50 40 70 50 60 ns ns ns ns Max Units ns ns ns 6 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline Package SOIC JEDEC SJ e Small Outline Package SOIC EIAJ 161A 163A S C X Special Variations QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13 reel Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 16-Lead (0 150 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M16A 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ) NS Package Number M16D 16-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F 74F161A  54F 74F163A Synchronous Presettable Binary Counter Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 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Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications