54F191PCX

54F 74F191 Up Down Binary Counter with Preset and Ripple Clock November 1994 54F 74F191 Up Down Binary Counter with Preset and Ripple Clock General Description The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting The preset feature allows the ’F191 to be used in programmable dividers The Count Enable input the Terminal Count output and Ripple Clock output make possible a variety of methods of implementing multistage counters In the counting modes state changes are initiated by the rising edge of the clock Features Y Y Y Y High-Speed 125 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Commercial 74F191PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F191DM (Note 2) 74F191SC (Note 1) 74F191SJ (Note 1) 54F191FM (Note 2) 54F191LM (Note 2) J16A M16A M16D W16A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9495–1 IEEE IEC TL F 9495 – 2 TL F 9495 – 3 TL F 9495–4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9495 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names CE CP P0 – P3 PL UD Q0 – Q3 RC TC Description Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Asynchronous Parallel Load Input (Active LOW) Up Down Count Control Input Flip-Flop Outputs Ripple Clock Output (Active LOW) Terminal Count Output (Active HIGH) UL Input IIH IIL HIGH LOW Output IOH IOL 10 30 10 10 10 10 10 10 10 10 50 33 3 50 33 3 50 33 3 20 mA b1 8 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA b 1 mA 20 mA b 1 mA 20 mA Functional Description The ’F191 is a synchronous up down 4-bit binary counter It contains four edge-triggered flip-flops with internal gating and steering logic to provide individual preset count-up and count-down operations Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number When the Parallel Load (PL) input is LOW information present on the Parallel Data inputs (P0–P3) is loaded into the counter and appears on the Q outputs This operation overrides the counting functions as indicated in the Mode Select Table A HIGH signal on the CE input inhibits counting When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input The direction of counting is determined by the U D input signal as indicated in the Mode Select Table CE and U D can be changed with the clock in either state provided only that the recommended setup and hold times are observed Two types of outputs are provided as overflow underflow indicators The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the countdown mode or reaches 15 in the count-up mode The TC output will then remain HIGH until a state change occurs whether by counting or presetting or until U D is changed The TC output should not be used as a clock signal because it is subject to decoding spikes The TC signal is also used internally to enable the Ripple Clock (RC) output The RC output is normally HIGH When CE is LOW and TC is HIGH the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again This feature simplifies the design of multistage counters as indicated in Figures 1 and 2 In Figure 1 each RC output is used as the clock input for the next higher stage This configuration is particularly advantageous when the clock source has a limited drive capability since it drives only the first stage To prevent counting in all stages it is only necessary to inhibit the first stage since a HIGH signal on CE inhibits the RC output pulse as indicated in the RC Truth Table A disadvantage of this configuration in some applications is the timing skew between state changes in the first and last stages This represents the cumulative delay of the clock as it ripples through the preceding stages A method of causing state changes to occur simultaneously in all stages is shown in Figure 2 All clock inputs are driven in parallel and the RC outputs propagate the carry borrow signals in ripple fashion In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry borrow signal to ripple through to the last stage before the clock goes HIGH There is no such restriction on the HIGH state duration of the clock since the RC output of any device goes HIGH shortly after its CP input goes HIGH The configuration shown in Figure 3 avoids ripple delays and their associated restrictions The CE input for a given stage is formed by combining the TC signals from all the preceding stages Note that in order to inhibit counting an enable signal must be included in each carry gate The simple inhibit scheme of Figures 1 and 2 doesn’t apply because the TC output of a given stage is not affected by its own CE Mode Select Table Inputs PL H H L H CE L L X H UD L H X X CP L L X X Count Up Count Down Preset (Asyn ) No Change (Hold) Mode RC Truth Table Inputs CE L H X TC H X L CP X X Output RC H H TC is generated internally H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition e LOW Pulse 2 Logic Diagram TL F 9495 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays TL F 9495 – 6 FIGURE 1 n-Stage Counter Using Ripple Clock TL F 9495 – 7 FIGURE 2 Synchronous n-Stage Counter Using Ripple Carry Borrow TL F 9495 – 8 FIGURE 3 Synchronous n-Stage Counter with Gated Carry Borrow 3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current b 60 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (except CE) VIN e 0 5V (CE) VOUT e 0V 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 25 25 27 05 05 20 0 50 100 70 250 50 4 75 3 75 b0 6 b1 8 b 150 VOL IIH IBVI ICEX VID IOD IIL IOS ICC V mA mA mA V mA mA mA mA Min Max Max Max 00 00 Max Max Max 38 55 4 AC Electrical Characteristics 74F Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Count Frequency Propagation Delay CP to Qn Propagation Delay CP to TC Propagation Delay CP to RC Propagation Delay CE to RC Propagation Delay U D to RC Propagation Delay U D to TC Propagation Delay Pn to Qn Propagation Delay PL to Qn Propagation Delay Pn to TC Propagation Delay Pn to RC Propagation Delay PL to TC Propagation Delay PL to RC 100 30 50 60 50 30 30 30 30 70 55 40 40 30 60 50 55 50 65 65 60 80 60 10 0 90 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 125 55 85 10 0 85 55 50 50 55 11 0 90 70 65 45 10 0 85 90 75 11 0 13 0 11 0 75 70 70 70 18 0 12 0 10 0 10 0 70 13 0 11 0 12 0 14 0 13 0 19 0 14 0 16 5 13 5 20 0 15 5 Max 54F TA VCC e Mil CL e 50 pF Min 75 30 50 60 50 30 30 30 30 70 55 40 40 30 60 50 55 95 13 5 16 5 13 5 95 90 90 90 22 0 14 0 13 5 12 5 90 16 0 13 0 14 5 Max 74F TA VCC e Com CL e 50 pF Min 90 30 50 60 50 30 30 30 30 70 55 40 40 30 60 50 55 50 60 65 60 80 60 10 0 90 85 12 0 14 0 12 0 85 80 80 80 20 0 13 0 11 0 11 0 80 14 0 12 0 13 0 15 0 14 0 20 0 15 0 17 5 14 5 21 0 16 0 ns ns ns ns ns ns Max MHz Units ns ns ns 5 AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(L) th(L) ts(H) ts(L) th(H) th(L) tw(L) tw(L) trec Setup Time HIGH or LOW Pn to PL Hold Time HIGH or LOW Pn to PL Setup Time LOW CE to CP Hold Time LOW CE to CP Setup Time HIGH or LOW U D to CP Hold Time HIGH or LOW U D to CP PL Pulse Width LOW CP Pulse Width LOW Recovery Time PL to CP 45 45 20 20 10 0 0 12 0 12 0 0 0 60 50 60 Max 54F TA VCC e Mil Min 60 60 20 20 10 5 0 12 0 12 0 0 0 85 70 75 Max 74F TA VCC e Com Min 50 50 20 20 10 0 ns 0 12 0 12 0 0 0 60 50 60 ns ns ns Max Units ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 191 S C X Special Variations X e Devices shipped in 13 reels QB e Military grade with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 6 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0 150 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M16A 16-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ) NS Package Number M16D 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F 74F191 Up Down Binary Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 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Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications