54F192FM

54F 74F192 Up Down Decade Counter with Separate Up Down Clocks November 1994 54F 74F192 Up Down Decade Counter with Separate Up Down Clocks General Description The ’F192 is an up down BCD decade (8421) counter Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs Separate Terminal Count Up and Terminal Count Down outputs are used as the clocks for a subsequent stage without extra logic thus simplifying multistage counter designs Individual preset inputs allow the circuit to be used as a programmable counter Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks Features Y Guaranteed 4000V minimum ESD protection Commercial 74F192PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F192DM (Note 2) 74F192SC (Note 1) 74F192SJ (Note 1) 54F192FM (Note 2) 54F192LM (Note 2) J16A M16A M16D W16A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9496–3 IEEE IEC TL F 9496 – 1 TL F 9496 – 2 TL F 9496–6 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9496 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL Input IIH IIL HIGH LOW Output IOH IOL 10 30 10 30 10 10 10 10 10 10 50 33 3 50 33 3 50 33 3 20 mA b1 8 mA 20 mA b1 8 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA b 1 mA 20 mA b 1 mA 20 mA CPU CPD MR PL P0 – P3 Q0 – Q3 TCD TCU Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output (Active LOW) Terminal Count Up (Carry) Output (Active LOW) Functional Description The ’F192 is an asynchronously presettable decade counter It contains four edge-triggered flip-flops with internal gating and steering logic to provide master reset individual preset count up and count down operations A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state Synchronous switching as opposed to ripple counting is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line thereby causing all state changes to be initiated simultaneously A LOW-to-HIGH transition on the Count Up input will advance the count by one a similar transition on the Count Down input will decrease the count by one While counting with one clock input the other should be held HIGH as indicated in the Function Table Otherwise the circuit will either count by twos or not at all depending on the state of the first flip-flop which cannot toggle as long as either clock input is LOW The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH When the circuit has reached the maximum count state 9 the next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW TCU will stay LOW until CPU goes HIGH again thus effectively repeating the Count Up Clock but delayed by two gate delays Similarly the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW Since the TC outputs repeat the clock waveforms they can be used as the clock input signals to the next higher order circuit in a multistage counter TCU e Q0  Q3  CPU TCD e Q0  Q1  Q2  Q3  CPD The ’F192 has an asynchronous parallel load capability permitting the counter to be preset When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW information present on the Parallel Data input (P0 – P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs A HIGH signal on the Master Reset input will disable the preset gates override both clock inputs and latch each Q output in the LOW state If one of the clock inputs is LOW during and after a reset or TL F 9496 – 4 load operation the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted Function Table MR H L L L L PL X L H H H CPU X X H L H CPD X X H H L Mode Reset (Asyn ) Preset (Asyn ) No Change Count Up Count Down H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition State Diagram 2 Logic Diagram TL F 9496 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current b 60 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V Except CPu CPD VIN e 0 5V CPu CPD VOUT e 0V VO e LOW 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 25 25 27 05 05 20 0 50 100 70 250 50 4 75 3 75 b0 6 b1 8 b 150 VOL IIH IBVI ICEX VID IOD IIL IOS ICCL V mA mA mA V mA mA mA mA Min Max Max Max 00 00 Max Max Max 38 55 4 AC Electrical Characteristics 74F Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPU or CPD to TCU or TCD Propagation Delay CPU or CPD to Qn Propagation Delay Pn to Qn Propagation Delay PL to Qn Propagation Delay MR to Qn Propagation Delay MR to TCU Propagation Delay MR to TCD Propagation Delay PL to TCU or TCD Propagation Delay Pn to TCU or TCD 100 40 35 40 55 30 60 50 55 65 60 70 70 70 70 65 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 125 70 60 65 95 45 11 0 85 10 0 11 0 10 5 11 5 12 0 11 5 11 5 11 0 90 80 85 12 5 70 14 5 11 0 13 0 14 5 13 5 14 5 15 5 14 5 14 5 14 0 Max 54F TA VCC e Mil CL e 50 pF Min 75 40 35 40 55 30 60 50 55 65 60 70 70 70 70 65 10 5 95 10 0 14 0 85 16 5 13 5 15 0 16 0 15 0 16 0 18 5 17 5 16 5 16 5 Max 74F TA VCC e Com CL e 50 pF Min 90 40 35 40 55 30 60 50 55 65 60 70 70 70 70 65 10 0 90 95 13 5 80 15 5 12 0 14 0 15 5 14 5 15 5 16 5 15 5 15 5 15 0 ns ns ns Max MHz ns ns ns ns Units AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) tw(L) tw(L) tw(L) Setup Time HIGH or LOW Pn to PL Hold Time HIGH or LOW Pn to PL PL Pulse Width LOW CPU or CPD Pulse Width LOW CPU or CPD Pulse Width LOW (Change of Direction) MR Pulse Width HIGH Recovery Time PL to CPU or CPD Recovery Time MR to CPU or CPD 45 45 20 20 60 50 Max 54F TA VCC e Mil Min 60 60 20 20 75 70 Max 74F TA VCC e Com Min 50 50 20 20 60 50 ns ns Max Units ns 10 0 60 60 40 12 0 60 80 45 10 0 60 60 40 ns ns ns ns tw(H) trec trec 5 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 192 S C X Special Variations X e Devices shipped in 13 reels QB e Military grade with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 6 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0 150 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M16A 16-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ) NS Package Number M16D 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F 74F192 Up Down Decade Counter with Separate Up Down Clocks Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck Germany Tel (81-41) 35-0 Telex 527649 Fax (81-41) 35-1 National Semiconductor Japan Ltd Sumitomo Chemical Engineering Center Bldg 7F 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture 261 Tel (043) 299-2300 Fax (043) 299-2500 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductores Do Brazil Ltda Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel (55-11) 212-5066 Telex 391-1131931 NSBR BR Fax (55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications