54F377DM

54F 74F377 Octal D Flip-Flop with Clock Enable May 1995 54F 74F377 Octal D Flip-Flop with Clock Enable General Description The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation Features Y Y Y Y Y Y Y Y Ideal for addressable register applications Clock enable for address and data synchronization applications Eight edge-triggered D flip-flops Buffered common clock See ’F273 for master reset version See ’F373 for transparent latch version See ’F374 for TRI-STATE version Guaranteed 4000V minimum ESD protection Commercial 74F377PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F377DM (QB) 74F377SC (Note 1) 74F377SJ (Note 1) 54F377FM (QB) 54F377LM (QB) J20A M20B M20D W20A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Logic Symbols IEEE IEC TL F 9525 – 1 TL F 9525 – 4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9525 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9525 – 3 TL F 9525–2 Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA D0 – D7 CE CP Q0 – Q7 Data Inputs Clock Enable (Active LOW) Clock Pulse Input Data Outputs Mode Select-Function Table Operating Mode CP Load ‘‘1’’ Load ‘‘0’’ Hold (Do Nothing) L L L X Inputs CE I I h H Dn h I X X Output Qn H L No Change No Change H e HIGH Voltage Level h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L e LOW Voltage Level I e LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X e Immaterial L e LOW-to-HIGH Clock Transition Logic Diagram TL F 9525 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Output Short-Circuit Current Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Power Supply Current 35 44 4 75 3 75 46 56 b 60 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VIN e 0 5V VOUT e 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded CP e L Dn e MR e HIGH 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 25 25 27 05 05 50 70 b0 6 b 150 VOL IIH IBVI IIL IOS ICEX VID IOD ICCH ICCL V mA mA mA mA mA V mA mA Min Max Max Max Max Max 00 00 Max 50 3 AC Electrical Characteristics 74F Symbol Parameter Min fMax tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn 130 30 40 70 90 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ Max 54F TA VCC e Mil CL e 50 pF Min 85 20 30 85 10 5 Max 74F TA VCC e Com CL e 50 pF Min 105 25 35 75 90 Max MHz ns Units AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP Setup Time HIGH or LOW CE to CP Hold Time HIGH to LOW CE to CP Clock Pulse Width HIGH or LOW 30 35 05 10 41 35 05 20 60 60 Max 54F TA VCC e Mil Min 35 40 10 10 40 50 15 25 50 50 Max 74F TA VCC e Com Min 30 35 05 10 41 40 05 20 60 60 Max ns ns ns ns ns Units Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 377 S C X Special Variations X e Devices shipped in 13 reels QB e Military grade with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 4 5 Physical Dimensions inches (millimeters) 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ) NS Package Number M20D 7 54F 74F377 Octal D Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) (Continued) 20-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be 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(55-11) 212-5066 Telex 391-1131931 NSBR BR Fax (55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications