54F410LM

54F 74F410 Register Stack August 1995 54F 74F410 Register Stack 16 x 4 RAM TRI-STATE Output Register General Description The ’F410 is a register-oriented high-speed 64-bit Read Write Memory organized as 16-words by 4-bits An edgetriggered 4-bit output register allows new input data to be written while previous data is held TRI-STATE outputs are provided for maximum versatility The ’F410 is fully compatible with all TTL families Features Y Y Y Y Y Y Edge-triggered output register Typical access time of 35 ns TRI-STATE outputs Optimized for register stack operation 18-pin package 9410 replacement 16 x 4 RAM TRI-STATE Output Register Commercial 74F410PC Military Package Number N18A Package Description 18-Lead (0 300 Wide) Molded Dual-In-Line 18-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead Cerpak 54F410DM (Note 1) 74F410SC 54F410LM J18A M20B W20A Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB LMQB Logic Symbol Connection Diagrams Pin Assignment for DIP and SOIC Pin Assignment for LCC TL F 9538–3 TL F 9538 – 1 TL F 9538 – 2 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9538 RRD-B30M105 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 10 20 10 10 Input IIH IIL Output IOH IOL 20 mA 20 mA 20 mA 20 mA 20 mA b 0 6 mA b 0 6 mA b 1 2 mA b 0 6 mA b 0 6 mA A0 – A3 D 0 – D3 CS OE WE CP Q0 – Q3 Address Inputs Data Inputs Chip Select Input (Active LOW) Output Enable Input (Active LOW) Write Enable Input (Active LOW) Clock Input (Outputs Change on LOW-to-HIGH Transition) TRI-STATE Outputs 10 20 150 40 (33 3) 20 mA b1 2 mA b 3 mA 24 mA (20 mA) Functional Description Write Operation When the three control inputs Write Enable (WE) Chip Select (CS) and Clock (CP) are LOW the information on the data inputs (D0 – D3) is written into the memory location selected by the address inputs (A0 – A3) If the input data changes while WE CS and CP are LOW the contents of the selected memory location follow these changes provided setup and hold time criteria are met Read Operation Whenever CS is LOW and CP goes from LOW-to-HIGH the contents of the memory location selected by the address inputs (A0 –A3) are edge-triggered into the Output Register The (OE) input controls the output buffers When OE is HIGH the four outputs (Q0 –Q3) are in a high impedance or OFF state when OE is LOW the outputs are determined by the state of the Output Register Block Diagram TL F 9538 – 4 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75 b0 6 b1 2 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V Min IIN e b18 mA IOH IOH IOH IOH IOH e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 3 mA 25 24 25 24 27 05 05 20 0 50 100 70 250 50 V Min VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current V mA mA mA V mA mA mA mA mA mA Min Max Max Max 00 00 Max Max Max Max 0 0V IOL e 20 mA IOL e 24 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (An Dn OE WE) VIN e 0 5V (CS CP) VOUT e 2 7V VOUT e 0 5V VOUT e 0V VOUT e 5 25V Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test b 60 50 b 50 b 150 500 3 DC Electrical Characteristics Symbol ICCH ICCL ICCZ Parameter (Continued) 54F 74F Min Typ 47 47 47 Max 70 70 70 mA mA mA Max Max Max VO e HIGH VO e LOW VO e HIGH Z Units VCC Conditions Power Supply Current Power Supply Current Power Supply Current AC Electrical Characteristics 74F Symbol Parameter TA e a 25 C VCC e a 5 0V CL e 50 pF Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay CP to Q Enable Time OE to Q Disable Time OE to Q 30 35 30 35 25 25 Max 85 90 80 90 65 70 54F TA VCC e Mil CL e 50 pF Min 25 30 25 30 20 20 Max 11 0 12 0 10 5 13 0 85 95 74F TA VCC e Com CL e 50 pF Min 25 30 25 30 20 20 Max 95 10 0 90 10 0 75 80 ns Units ns AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min READ MODE ts(H) ts(L) th(H) th(L) WRITE MODE ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw tw tw Setup Time HIGH or LOW An to WE Hold Time HIGH or LOW An to WE Setup Time HIGH or LOW Dn to WE Hold Time HIGH or LOW Dn to WE WE Pulse Width Required to Write CS Pulse Width Required to Write CP Pulse Width Required to Write 0 0 0 0 50 50 0 0 75 75 75 0 0 0 0 85 85 25 25 95 95 95 0 0 0 0 60 60 0 0 85 85 85 ns ns ns Setup Time HIGH or LOW An to CP Hold Time HIGH or LOW An to CP 15 0 15 0 0 0 23 23 0 0 17 0 17 0 0 0 Max 54F TA VCC e Mil Min Max 74F TA VCC e Com Min Max Units ns ns ns Note Military temperature range for this device is b40 C to a 85 C 4 Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP S e Small Outline (SOIC) D e Ceramic DIP L e Package Leadless Chip Carrier 410 S C X Special Variations X e Devices shipped in 13 reels QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 5 Physical Dimensions inches (millimeters) 18-Lead Ceramic Dual-In-Line Package (D) NS Package Number J18A 20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B 6 Physical Dimensions inches (millimeters) (Continued) 18-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N18A 7 16 x 4 RAM TRI-STATE Output Register Physical Dimensions inches (millimeters) (Continued) 20-Lead Cerpack NS Package Number W20A 54F 74F410 Register Stack LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications