54F533

54F 74F533 Octal Transparent Latch with TRI-STATE Outputs May 1995 54F 74F533 Octal Transparent Latch with TRI-STATE Outputs General Description The ’F533 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH When LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state The ’F533 is the same as the ’F373 except that the outputs are inverted Features Y Y Y Y Eight latches in a single package TRI-STATE outputs for bus interfacing Inverted version of the ’F373 Guaranteed 4000V minimum ESD protection Commercial 74F533PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F533DM (Note 2) 74F533SC (Note 1) 74F533SJ (Note 1) 54F533FM (Note 2) 54F533LM (Note 2) Note 1 Devices also available in 13 J20A M20B M20D W20A E20A reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9548 – 3 TL F 9548–4 TL F 9548 – 2 TL F 9548–1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9548 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 3 mA 24 mA (20 mA) D0 – D7 LE OE O0 – O 7 Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) Complementary TRI-STATE Outputs Function Table Inputs Output D H L X X O L H O0 Z LE H H L X OE L L L H H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Functional Description The ’F533 contains eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Logic Diagram TL F 9548 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75 b0 6 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V Min IIN e b18 mA IOH IOH IOH IOH IOH IOH e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA 25 24 25 24 27 27 05 05 20 0 50 100 70 10 05 250 50 V Min VOL IIH IBVI IBVIT ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current V mA mA mA mA V mA mA mA mA mA mA mA Min Max Max Max Max 00 00 Max Max Max Max 0 0V Max IOL e 20 mA IOL e 24 mA VIN e 2 7V VIN e 7 0V VIN e 5 5V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 2 7V VOUT e 0 5V VOUT e 0V VOUT e 5 25V VO e HIGH Z Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current 41 3 b 60 50 b 50 b 150 500 61 AC Electrical Characteristics 74F Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time 40 25 50 30 20 20 15 15 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 67 44 71 47 59 56 34 27 Max 90 70 11 0 70 10 0 75 65 55 54F TA VCC e Mil CL e 50 pF Min 40 25 50 30 20 20 15 15 Max 12 0 90 14 0 90 12 5 10 5 85 75 74F TA VCC e Com CL e 50 pF Min 40 25 50 30 20 20 15 15 Max 10 0 80 13 0 80 11 0 85 70 65 ns ns ns ns Units AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) tw(H) Setup Time HIGH or LOW Dn to LE Hold Time HIGH or LOW Dn to LE LE Pulse Width HIGH 20 20 30 30 60 Max 54F TA VCC e Mil Min 20 20 30 30 60 Max 74F TA VCC e Com Min 20 20 30 30 60 Max ns ns ns Units Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 533 S C X Special Variations X e Devices shipped in 13 reels QB e Military grade device with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 4 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B 20-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ) NS Package Number M20D 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 7 54F 74F533 Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant 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(55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications